stm32: update stm32-metapac.

embassy-stm32/src/rcc/f4.rs

@@ -36,18 +36,18 @@ pub struct Config {
 }
 
 #[cfg(stm32f410)]
-unsafe fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
+fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
     None
 }
 
 // Not currently implemented, but will be in the future
 #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
-unsafe fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
+fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
     None
 }
 
 #[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
-unsafe fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
+fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
     let min_div = 2;
     let max_div = 7;
     let target = match plli2s {
@@ -82,13 +82,7 @@ unsafe fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
     Some(output)
 }
 
-unsafe fn setup_pll(
-    pllsrcclk: u32,
-    use_hse: bool,
-    pllsysclk: Option<u32>,
-    plli2s: Option<u32>,
-    pll48clk: bool,
-) -> PllResults {
+fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, plli2s: Option<u32>, pll48clk: bool) -> PllResults {
     use crate::pac::rcc::vals::{Pllp, Pllsrc};
 
     let sysclk = pllsysclk.unwrap_or(pllsrcclk);
@@ -320,7 +314,7 @@ impl<'d, T: McoInstance> Mco<'d, T> {
     }
 }
 
-unsafe fn flash_setup(sysclk: u32) {
+fn flash_setup(sysclk: u32) {
     use crate::pac::flash::vals::Latency;
 
     // Be conservative with voltage ranges

embassy-stm32/src/rcc/f7.rs

@@ -25,7 +25,7 @@ pub struct Config {
     pub pll48: bool,
 }
 
-unsafe fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
+fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
     use crate::pac::rcc::vals::{Pllp, Pllsrc};
 
     let sysclk = pllsysclk.unwrap_or(pllsrcclk);
@@ -97,7 +97,7 @@ unsafe fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48
     }
 }
 
-unsafe fn flash_setup(sysclk: u32) {
+fn flash_setup(sysclk: u32) {
     use crate::pac::flash::vals::Latency;
 
     // Be conservative with voltage ranges

embassy-stm32/src/rcc/g0.rs

@@ -245,7 +245,7 @@ impl Default for Config {
 }
 
 impl PllConfig {
-    pub(crate) unsafe fn init(self) -> u32 {
+    pub(crate) fn init(self) -> u32 {
         assert!(self.n >= 8 && self.n <= 86);
         let (src, input_freq) = match self.source {
             PllSrc::HSI16 => (vals::Pllsrc::HSI16, HSI_FREQ.0),

embassy-stm32/src/rcc/h5.rs

@@ -462,7 +462,7 @@ struct PllOutput {
     r: Option<Hertz>,
 }
 
-unsafe fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
+fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
     let Some(config) = config else {
         // Stop PLL
         RCC.cr().modify(|w| w.set_pllon(num, false));
@@ -595,12 +595,9 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
 
     defmt::debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
 
-    // NOTE(unsafe) Atomic write
-    unsafe {
-        FLASH.acr().write(|w| {
-            w.set_wrhighfreq(wrhighfreq);
-            w.set_latency(latency);
-        });
-        while FLASH.acr().read().latency() != latency {}
-    }
+    FLASH.acr().write(|w| {
+        w.set_wrhighfreq(wrhighfreq);
+        w.set_latency(latency);
+    });
+    while FLASH.acr().read().latency() != latency {}
 }

embassy-stm32/src/rcc/h7.rs

@@ -253,14 +253,11 @@ fn flash_setup(rcc_aclk: u32, vos: VoltageScale) {
         },
     };
 
-    // NOTE(unsafe) Atomic write
-    unsafe {
-        FLASH.acr().write(|w| {
-            w.set_wrhighfreq(progr_delay);
-            w.set_latency(wait_states)
-        });
-        while FLASH.acr().read().latency() != wait_states {}
-    }
+    FLASH.acr().write(|w| {
+        w.set_wrhighfreq(progr_delay);
+        w.set_latency(wait_states)
+    });
+    while FLASH.acr().read().latency() != wait_states {}
 }
 
 pub enum McoClock {
@@ -474,7 +471,6 @@ pub(crate) unsafe fn init(mut config: Config) {
     // Configure traceclk from PLL if needed
     traceclk_setup(&mut config, sys_use_pll1_p);
 
-    // NOTE(unsafe) We have exclusive access to the RCC
     let (pll1_p_ck, pll1_q_ck, pll1_r_ck) = pll::pll_setup(srcclk.0, &config.pll1, 0);
     let (pll2_p_ck, pll2_q_ck, pll2_r_ck) = pll::pll_setup(srcclk.0, &config.pll2, 1);
     let (pll3_p_ck, pll3_q_ck, pll3_r_ck) = pll::pll_setup(srcclk.0, &config.pll3, 2);
@@ -756,7 +752,7 @@ mod pll {
     /// # Safety
     ///
     /// Must have exclusive access to the RCC register block
-    unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConfigResults {
+    fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConfigResults {
         use crate::pac::rcc::vals::{Pllrge, Pllvcosel};
 
         let (vco_ck_target, pll_x_p) = vco_output_divider_setup(requested_output, plln);
@@ -785,11 +781,7 @@ mod pll {
     /// # Safety
     ///
     /// Must have exclusive access to the RCC register block
-    pub(super) unsafe fn pll_setup(
-        pll_src: u32,
-        config: &PllConfig,
-        plln: usize,
-    ) -> (Option<u32>, Option<u32>, Option<u32>) {
+    pub(super) fn pll_setup(pll_src: u32, config: &PllConfig, plln: usize) -> (Option<u32>, Option<u32>, Option<u32>) {
         use crate::pac::rcc::vals::Divp;
 
         match config.p_ck {