stm32: update stm32-metapac.
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@ -60,25 +60,19 @@ macro_rules! impl_basic_16bit_timer {
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type Interrupt = crate::interrupt::typelevel::$irq;
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fn regs() -> crate::pac::timer::TimBasic {
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crate::pac::timer::TimBasic(crate::pac::$inst.0)
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unsafe { crate::pac::timer::TimBasic::from_ptr(crate::pac::$inst.as_ptr()) }
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}
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fn start(&mut self) {
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unsafe {
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Self::regs().cr1().modify(|r| r.set_cen(true));
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}
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Self::regs().cr1().modify(|r| r.set_cen(true));
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}
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fn stop(&mut self) {
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unsafe {
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Self::regs().cr1().modify(|r| r.set_cen(false));
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}
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Self::regs().cr1().modify(|r| r.set_cen(false));
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}
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fn reset(&mut self) {
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unsafe {
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Self::regs().cnt().write(|r| r.set_cnt(0));
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}
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Self::regs().cnt().write(|r| r.set_cnt(0));
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}
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fn set_frequency(&mut self, frequency: Hertz) {
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@ -90,35 +84,29 @@ macro_rules! impl_basic_16bit_timer {
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let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into());
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let regs = Self::regs();
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unsafe {
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regs.psc().write(|r| r.set_psc(psc));
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regs.arr().write(|r| r.set_arr(arr));
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regs.psc().write(|r| r.set_psc(psc));
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regs.arr().write(|r| r.set_arr(arr));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
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regs.egr().write(|r| r.set_ug(true));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
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}
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regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
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regs.egr().write(|r| r.set_ug(true));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
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}
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fn clear_update_interrupt(&mut self) -> bool {
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let regs = Self::regs();
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unsafe {
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let sr = regs.sr().read();
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if sr.uif() {
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regs.sr().modify(|r| {
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r.set_uif(false);
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});
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true
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} else {
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false
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}
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let sr = regs.sr().read();
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if sr.uif() {
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regs.sr().modify(|r| {
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r.set_uif(false);
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});
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true
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} else {
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false
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}
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}
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fn enable_update_interrupt(&mut self, enable: bool) {
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unsafe {
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Self::regs().dier().write(|r| r.set_uie(enable));
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}
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Self::regs().dier().write(|r| r.set_uie(enable));
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}
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}
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};
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@ -141,14 +129,12 @@ macro_rules! impl_32bit_timer {
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let arr: u32 = unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()));
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let regs = Self::regs_gp32();
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unsafe {
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regs.psc().write(|r| r.set_psc(psc));
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regs.arr().write(|r| r.set_arr(arr));
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regs.psc().write(|r| r.set_psc(psc));
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regs.arr().write(|r| r.set_arr(arr));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
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regs.egr().write(|r| r.set_ug(true));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
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}
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regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
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regs.egr().write(|r| r.set_ug(true));
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regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
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}
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}
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};
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@ -185,7 +171,7 @@ foreach_interrupt! {
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impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
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fn regs_gp16() -> crate::pac::timer::TimGp16 {
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crate::pac::timer::TimGp16(crate::pac::$inst.0)
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unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) }
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}
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}
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@ -206,7 +192,7 @@ foreach_interrupt! {
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impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
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fn regs_gp16() -> crate::pac::timer::TimGp16 {
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crate::pac::timer::TimGp16(crate::pac::$inst.0)
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unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) }
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}
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}
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