stm32: update stm32-metapac.
This commit is contained in:
@ -19,68 +19,64 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
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let state = T::buffered_state();
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// RX
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unsafe {
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let sr = sr(r).read();
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// On v1 & v2, reading DR clears the rxne, error and idle interrupt
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// flags. Keep this close to the SR read to reduce the chance of a
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// flag being set in-between.
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let dr = if sr.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr.ore() || sr.idle()) {
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Some(rdr(r).read_volatile())
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let sr_val = sr(r).read();
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// On v1 & v2, reading DR clears the rxne, error and idle interrupt
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// flags. Keep this close to the SR read to reduce the chance of a
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// flag being set in-between.
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let dr = if sr_val.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr_val.ore() || sr_val.idle()) {
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Some(rdr(r).read_volatile())
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} else {
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None
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};
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clear_interrupt_flags(r, sr_val);
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if sr_val.pe() {
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warn!("Parity error");
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}
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if sr_val.fe() {
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warn!("Framing error");
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}
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if sr_val.ne() {
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warn!("Noise error");
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}
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if sr_val.ore() {
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warn!("Overrun error");
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}
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if sr_val.rxne() {
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let mut rx_writer = state.rx_buf.writer();
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let buf = rx_writer.push_slice();
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if !buf.is_empty() {
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buf[0] = dr.unwrap();
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rx_writer.push_done(1);
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} else {
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None
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};
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clear_interrupt_flags(r, sr);
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if sr.pe() {
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warn!("Parity error");
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}
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if sr.fe() {
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warn!("Framing error");
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}
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if sr.ne() {
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warn!("Noise error");
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}
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if sr.ore() {
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warn!("Overrun error");
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}
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if sr.rxne() {
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let mut rx_writer = state.rx_buf.writer();
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let buf = rx_writer.push_slice();
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if !buf.is_empty() {
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buf[0] = dr.unwrap();
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rx_writer.push_done(1);
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} else {
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// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
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}
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if state.rx_buf.is_full() {
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state.rx_waker.wake();
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}
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// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
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}
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if sr.idle() {
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if state.rx_buf.is_full() {
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state.rx_waker.wake();
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}
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}
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if sr_val.idle() {
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state.rx_waker.wake();
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}
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// TX
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unsafe {
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if sr(r).read().txe() {
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let mut tx_reader = state.tx_buf.reader();
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let buf = tx_reader.pop_slice();
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if !buf.is_empty() {
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r.cr1().modify(|w| {
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w.set_txeie(true);
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});
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tdr(r).write_volatile(buf[0].into());
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tx_reader.pop_done(1);
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state.tx_waker.wake();
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} else {
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// Disable interrupt until we have something to transmit again
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r.cr1().modify(|w| {
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w.set_txeie(false);
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});
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}
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if sr(r).read().txe() {
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let mut tx_reader = state.tx_buf.reader();
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let buf = tx_reader.pop_slice();
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if !buf.is_empty() {
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r.cr1().modify(|w| {
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w.set_txeie(true);
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});
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tdr(r).write_volatile(buf[0].into());
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tx_reader.pop_done(1);
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state.tx_waker.wake();
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} else {
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// Disable interrupt until we have something to transmit again
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r.cr1().modify(|w| {
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w.set_txeie(false);
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});
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}
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}
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}
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@ -150,14 +146,12 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
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T::enable();
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T::reset();
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unsafe {
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rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
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cts.set_as_af(cts.af_num(), AFType::Input);
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T::regs().cr3().write(|w| {
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w.set_rtse(true);
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w.set_ctse(true);
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});
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}
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rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
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cts.set_as_af(cts.af_num(), AFType::Input);
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T::regs().cr3().write(|w| {
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w.set_rtse(true);
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w.set_ctse(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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}
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@ -178,12 +172,10 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
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T::enable();
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T::reset();
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unsafe {
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de.set_as_af(de.af_num(), AFType::OutputPushPull);
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T::regs().cr3().write(|w| {
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w.set_dem(true);
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});
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}
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de.set_as_af(de.af_num(), AFType::OutputPushPull);
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T::regs().cr3().write(|w| {
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w.set_dem(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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}
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@ -205,22 +197,18 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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let r = T::regs();
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unsafe {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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configure(r, &config, T::frequency(), T::KIND, true, true);
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unsafe {
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r.cr1().modify(|w| {
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#[cfg(lpuart_v2)]
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w.set_fifoen(true);
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r.cr1().modify(|w| {
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#[cfg(lpuart_v2)]
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w.set_fifoen(true);
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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}
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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