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nrf/rtc: update to new api

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This commit is contained in:
Dario Nieuwenhuis
2021-03-27 03:12:58 +01:00
parent 3eccddc44d
commit 5646926cca
14 changed files with 197 additions and 236 deletions
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136
embassy-nrf/src/lib.rs
View File

@ -106,110 +106,110 @@ pub mod uarte;
embassy_extras::peripherals! {
// RTC
rtc0: RTC0,
rtc1: RTC1,
RTC0,
RTC1,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
rtc2: RTC2,
RTC2,
// QSPI
#[cfg(feature = "52840")]
qspi: QSPI,
QSPI,
// UARTE
uarte0: UARTE0,
UARTE0,
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
uarte1: UARTE1,
UARTE1,
// SPIM
// TODO this is actually shared with SPI, SPIM, SPIS, TWI, TWIS, TWIS.
// When they're all implemented, they should be only one peripheral here.
spim0: SPIM0,
SPIM0,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
spim1: SPIM1,
SPIM1,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
spim2: SPIM2,
SPIM2,
#[cfg(any(feature = "52833", feature = "52840"))]
spim3: SPIM3,
SPIM3,
// SAADC
saadc: SAADC,
SAADC,
// GPIOTE
gpiote: GPIOTE,
gpiote_ch_0: GPIOTE_CH0,
gpiote_ch_1: GPIOTE_CH1,
gpiote_ch_2: GPIOTE_CH2,
gpiote_ch_3: GPIOTE_CH3,
gpiote_ch_4: GPIOTE_CH4,
gpiote_ch_5: GPIOTE_CH5,
gpiote_ch_6: GPIOTE_CH6,
gpiote_ch_7: GPIOTE_CH7,
GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
// GPIO port 0
p0_00: P0_00,
p0_01: P0_01,
p0_02: P0_02,
p0_03: P0_03,
p0_04: P0_04,
p0_05: P0_05,
p0_06: P0_06,
p0_07: P0_07,
p0_08: P0_08,
p0_09: P0_09,
p0_10: P0_10,
p0_11: P0_11,
p0_12: P0_12,
p0_13: P0_13,
p0_14: P0_14,
p0_15: P0_15,
p0_16: P0_16,
p0_17: P0_17,
p0_18: P0_18,
p0_19: P0_19,
p0_20: P0_20,
p0_21: P0_21,
p0_22: P0_22,
p0_23: P0_23,
p0_24: P0_24,
p0_25: P0_25,
p0_26: P0_26,
p0_27: P0_27,
p0_28: P0_28,
p0_29: P0_29,
p0_30: P0_30,
p0_31: P0_31,
P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
// GPIO port 1
#[cfg(any(feature = "52833", feature = "52840"))]
p1_00: P1_00,
P1_00,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_01: P1_01,
P1_01,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_02: P1_02,
P1_02,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_03: P1_03,
P1_03,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_04: P1_04,
P1_04,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_05: P1_05,
P1_05,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_06: P1_06,
P1_06,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_07: P1_07,
P1_07,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_08: P1_08,
P1_08,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_09: P1_09,
P1_09,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_10: P1_10,
P1_10,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_11: P1_11,
P1_11,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_12: P1_12,
P1_12,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_13: P1_13,
P1_13,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_14: P1_14,
P1_14,
#[cfg(any(feature = "52833", feature = "52840"))]
p1_15: P1_15,
P1_15,
}

86
embassy-nrf/src/rtc.rs
View File

@ -1,13 +1,12 @@
use core::cell::Cell;
use core::ops::Deref;
use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
use embassy::interrupt::InterruptExt;
use embassy::time::Clock;
use crate::interrupt;
use crate::interrupt::{CriticalSection, Interrupt, Mutex};
use crate::pac::rtc0;
use crate::pac;
use crate::{interrupt, peripherals};
// RTC timekeeping works with something we call "periods", which are time intervals
// of 2^23 ticks. The RTC counter value is 24 bits, so one "overflow cycle" is 2 periods.
@ -96,19 +95,20 @@ impl<T: Instance> RTC<T> {
}
pub fn start(&'static self) {
self.rtc.cc[3].write(|w| unsafe { w.bits(0x800000) });
let r = self.rtc.regs();
r.cc[3].write(|w| unsafe { w.bits(0x800000) });
self.rtc.intenset.write(|w| {
r.intenset.write(|w| {
let w = w.ovrflw().set();
let w = w.compare3().set();
w
});
self.rtc.tasks_clear.write(|w| unsafe { w.bits(1) });
self.rtc.tasks_start.write(|w| unsafe { w.bits(1) });
r.tasks_clear.write(|w| unsafe { w.bits(1) });
r.tasks_start.write(|w| unsafe { w.bits(1) });
// Wait for clear
while self.rtc.counter.read().bits() != 0 {}
while r.counter.read().bits() != 0 {}
self.irq.set_handler(|ptr| unsafe {
let this = &*(ptr as *const () as *const Self);
@ -120,19 +120,20 @@ impl<T: Instance> RTC<T> {
}
fn on_interrupt(&self) {
if self.rtc.events_ovrflw.read().bits() == 1 {
self.rtc.events_ovrflw.write(|w| w);
let r = self.rtc.regs();
if r.events_ovrflw.read().bits() == 1 {
r.events_ovrflw.write(|w| w);
self.next_period();
}
if self.rtc.events_compare[3].read().bits() == 1 {
self.rtc.events_compare[3].write(|w| w);
if r.events_compare[3].read().bits() == 1 {
r.events_compare[3].write(|w| w);
self.next_period();
}
for n in 0..ALARM_COUNT {
if self.rtc.events_compare[n].read().bits() == 1 {
self.rtc.events_compare[n].write(|w| w);
if r.events_compare[n].read().bits() == 1 {
r.events_compare[n].write(|w| w);
interrupt::free(|cs| {
self.trigger_alarm(n, cs);
})
@ -142,6 +143,7 @@ impl<T: Instance> RTC<T> {
fn next_period(&self) {
interrupt::free(|cs| {
let r = self.rtc.regs();
let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
let t = (period as u64) << 23;
@ -151,15 +153,16 @@ impl<T: Instance> RTC<T> {
let diff = at - t;
if diff < 0xc00000 {
self.rtc.cc[n].write(|w| unsafe { w.bits(at as u32 & 0xFFFFFF) });
self.rtc.intenset.write(|w| unsafe { w.bits(compare_n(n)) });
r.cc[n].write(|w| unsafe { w.bits(at as u32 & 0xFFFFFF) });
r.intenset.write(|w| unsafe { w.bits(compare_n(n)) });
}
}
})
}
fn trigger_alarm(&self, n: usize, cs: &CriticalSection) {
self.rtc.intenclr.write(|w| unsafe { w.bits(compare_n(n)) });
let r = self.rtc.regs();
r.intenclr.write(|w| unsafe { w.bits(compare_n(n)) });
let alarm = &self.alarms.borrow(cs)[n];
alarm.timestamp.set(u64::MAX);
@ -190,6 +193,8 @@ impl<T: Instance> RTC<T> {
return;
}
let r = self.rtc.regs();
// If it hasn't triggered yet, setup it in the compare channel.
let diff = timestamp - t;
if diff < 0xc00000 {
@ -206,12 +211,12 @@ impl<T: Instance> RTC<T> {
// by the Alarm trait contract. What's not allowed is triggering alarms *before* their scheduled time,
// and we don't do that here.
let safe_timestamp = timestamp.max(t + 3);
self.rtc.cc[n].write(|w| unsafe { w.bits(safe_timestamp as u32 & 0xFFFFFF) });
self.rtc.intenset.write(|w| unsafe { w.bits(compare_n(n)) });
r.cc[n].write(|w| unsafe { w.bits(safe_timestamp as u32 & 0xFFFFFF) });
r.intenset.write(|w| unsafe { w.bits(compare_n(n)) });
} else {
// If it's too far in the future, don't setup the compare channel yet.
// It will be setup later by `next_period`.
self.rtc.intenclr.write(|w| unsafe { w.bits(compare_n(n)) });
r.intenclr.write(|w| unsafe { w.bits(compare_n(n)) });
}
})
}
@ -232,7 +237,7 @@ impl<T: Instance> embassy::time::Clock for RTC<T> {
// `period` MUST be read before `counter`, see comment at the top for details.
let period = self.period.load(Ordering::Relaxed);
compiler_fence(Ordering::Acquire);
let counter = self.rtc.counter.read().bits();
let counter = self.rtc.regs().counter.read().bits();
calc_now(period, counter)
}
}
@ -257,31 +262,32 @@ impl<T: Instance> embassy::time::Alarm for Alarm<T> {
}
mod sealed {
pub trait Instance {}
use super::*;
pub trait Instance {
fn regs(&self) -> &pac::rtc0::RegisterBlock;
}
}
impl Instance for crate::pac::RTC0 {}
impl Instance for crate::pac::RTC1 {}
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl Instance for crate::pac::RTC2 {}
macro_rules! make_impl {
($type:ident, $irq:ident) => {
impl sealed::Instance for peripherals::$type {
fn regs(&self) -> &pac::rtc0::RegisterBlock {
unsafe { &*pac::$type::ptr() }
}
}
impl Instance for peripherals::$type {
type Interrupt = interrupt::$irq;
}
};
}
/// Implemented by all RTC instances.
pub trait Instance:
sealed::Instance + Deref<Target = rtc0::RegisterBlock> + Sized + 'static
{
pub trait Instance: sealed::Instance + 'static {
/// The interrupt associated with this RTC instance.
type Interrupt: Interrupt;
}
impl Instance for crate::pac::RTC0 {
type Interrupt = interrupt::RTC0;
}
impl Instance for crate::pac::RTC1 {
type Interrupt = interrupt::RTC1;
}
make_impl!(RTC0, RTC0);
make_impl!(RTC1, RTC1);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl Instance for crate::pac::RTC2 {
type Interrupt = interrupt::RTC2;
}
make_impl!(RTC2, RTC2);