From 56c5218292de2d0722e30ae033191de0ef8e4647 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 16 Jun 2021 16:21:16 +0200
Subject: [PATCH] Prescaler 1 means divide by 3 on WL55

---
 embassy-stm32/src/rcc/types.rs    | 2 +-
 embassy-stm32/src/rcc/wl5x/mod.rs | 6 +++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/src/rcc/types.rs b/embassy-stm32/src/rcc/types.rs
index df7917ab..1fcaa27e 100644
--- a/embassy-stm32/src/rcc/types.rs
+++ b/embassy-stm32/src/rcc/types.rs
@@ -63,7 +63,7 @@ pub enum PLLMul {
 }
 
 /// AHB prescaler
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, PartialEq)]
 pub enum AHBPrescaler {
     NotDivided,
     Div2,
diff --git a/embassy-stm32/src/rcc/wl5x/mod.rs b/embassy-stm32/src/rcc/wl5x/mod.rs
index 6fa31ce2..554a27ca 100644
--- a/embassy-stm32/src/rcc/wl5x/mod.rs
+++ b/embassy-stm32/src/rcc/wl5x/mod.rs
@@ -164,7 +164,11 @@ impl RccExt for RCC {
         unsafe {
             rcc.cfgr().modify(|w| {
                 w.set_sw(sw.into());
-                w.set_hpre(cfgr.ahb_pre.into());
+                if cfgr.ahb_pre == AHBPrescaler::NotDivided {
+                    w.set_hpre(0);
+                } else {
+                    w.set_hpre(cfgr.ahb_pre.into());
+                }
                 w.set_ppre1(cfgr.apb1_pre.into());
                 w.set_ppre2(cfgr.apb2_pre.into());
             });