From 573e6ec373c92e1c85f9d84b3b68f36f1e4d0dc9 Mon Sep 17 00:00:00 2001
From: Ben Gamari <ben@smart-cactus.org>
Date: Tue, 31 Aug 2021 01:51:49 -0400
Subject: [PATCH] stm32g0: Add support for low-power run

---
 embassy-stm32/src/rcc/g0/mod.rs | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/embassy-stm32/src/rcc/g0/mod.rs b/embassy-stm32/src/rcc/g0/mod.rs
index 74577917..c0b5b14e 100644
--- a/embassy-stm32/src/rcc/g0/mod.rs
+++ b/embassy-stm32/src/rcc/g0/mod.rs
@@ -49,7 +49,6 @@ impl Into<u8> for HSI16Prescaler {
     }
 }
 
-
 impl Into<u8> for APBPrescaler {
     fn into(self) -> u8 {
         match self {
@@ -83,6 +82,7 @@ pub struct Config {
     mux: ClockSrc,
     ahb_pre: AHBPrescaler,
     apb_pre: APBPrescaler,
+    low_power_run: bool,
 }
 
 impl Default for Config {
@@ -92,6 +92,7 @@ impl Default for Config {
             mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided),
             ahb_pre: AHBPrescaler::NotDivided,
             apb_pre: APBPrescaler::NotDivided,
+            low_power_run: false,
         }
     }
 }
@@ -114,6 +115,12 @@ impl Config {
         self.apb_pre = pre;
         self
     }
+
+    #[inline]
+    pub fn low_power_run(mut self, on: bool) -> Self {
+        self.low_power_run = on;
+        self
+    }
 }
 
 /// RCC peripheral
@@ -206,6 +213,14 @@ impl RccExt for RCC {
             }
         };
 
+        let pwr = pac::PWR;
+        if cfgr.low_power_run {
+            assert!(sys_clk.hz() <= 2_000_000.hz());
+            unsafe {
+                pwr.cr1().modify(|w| w.set_lpr(true));
+            }
+        }
+
         Clocks {
             sys: sys_clk.hz(),
             ahb: ahb_freq.hz(),