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Merge branch 'master' into center-align

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This commit is contained in:
Dion Dokter
2023-10-20 14:17:55 +02:00
parent 6f2995cd4c 88ada52146
commit 5b3f75dc72
433 changed files with 6915 additions and 7018 deletions
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14
embassy-stm32/Cargo.toml
View File

@ -33,11 +33,11 @@ flavors = [
[dependencies]
embassy-sync = { version = "0.3.0", path = "../embassy-sync" }
embassy-time = { version = "0.1.3", path = "../embassy-time", optional = true }
embassy-time = { version = "0.1.5", path = "../embassy-time", optional = true }
embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
embassy-hal-internal = {version = "0.1.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
embassy-executor = { version = "0.3.0", path = "../embassy-executor", optional = true }
@ -58,16 +58,14 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ee2862086886cd8ebaf5fd5e3bd6cfbe5baa840" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
stm32-fmc = "0.3.0"
seq-macro = "0.3.0"
cfg-if = "1.0.0"
embedded-io = { version = "0.5.0" }
embedded-io-async = { version = "0.5.0", optional = true }
embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.0", optional = true }
chrono = { version = "^0.4", default-features = false, optional = true}
bit_field = "0.10.2"
document-features = "0.2.7"
@ -78,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ee2862086886cd8ebaf5fd5e3bd6cfbe5baa840", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526", default-features = false, features = ["metadata"]}
[features]

341
embassy-stm32/build.rs
View File

@ -5,9 +5,36 @@ use std::{env, fs};
use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
use stm32_metapac::metadata::{MemoryRegionKind, METADATA};
use stm32_metapac::metadata::ir::{BlockItemInner, Enum, FieldSet};
use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, METADATA};
fn main() {
let target = env::var("TARGET").unwrap();
if target.starts_with("thumbv6m-") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv6m");
} else if target.starts_with("thumbv7m-") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv7m");
} else if target.starts_with("thumbv7em-") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv7m");
println!("cargo:rustc-cfg=armv7em"); // (not currently used)
} else if target.starts_with("thumbv8m.base") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv8m");
println!("cargo:rustc-cfg=armv8m_base");
} else if target.starts_with("thumbv8m.main") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv8m");
println!("cargo:rustc-cfg=armv8m_main");
}
if target.ends_with("-eabihf") {
println!("cargo:rustc-cfg=has_fpu");
}
let chip_name = match env::vars()
.map(|(a, _)| a)
.filter(|x| x.starts_with("CARGO_FEATURE_STM32"))
@ -50,12 +77,14 @@ fn main() {
// We *shouldn't* have singletons for these, but the HAL currently requires
// singletons, for using with RccPeripheral to enable/disable clocks to them.
"rcc" => {
if r.version.starts_with("h5") || r.version.starts_with("h7") || r.version.starts_with("f4") {
singletons.push("MCO1".to_string());
singletons.push("MCO2".to_string());
}
if r.version.starts_with("l4") {
singletons.push("MCO".to_string());
for pin in p.pins {
if pin.signal.starts_with("MCO") {
let name = pin.signal.replace('_', "").to_string();
if !singletons.contains(&name) {
println!("cargo:rustc-cfg={}", name.to_ascii_lowercase());
singletons.push(name);
}
}
}
singletons.push(p.name.to_string());
}
@ -91,6 +120,7 @@ fn main() {
struct SplitFeature {
feature_name: String,
pin_name_with_c: String,
#[cfg(feature = "_split-pins-enabled")]
pin_name_without_c: String,
}
@ -358,6 +388,47 @@ fn main() {
});
}
// ========
// Extract the rcc registers
let rcc_registers = METADATA
.peripherals
.iter()
.filter_map(|p| p.registers.as_ref())
.find(|r| r.kind == "rcc")
.unwrap();
// ========
// Generate rcc fieldset and enum maps
let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = {
let rcc_blocks = rcc_registers.ir.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.ir.fieldsets.iter().map(|f| (f.name, f)).collect();
let rcc_enums: HashMap<&str, &Enum> = rcc_registers.ir.enums.iter().map(|e| (e.name, e)).collect();
rcc_blocks
.iter()
.filter_map(|b| match &b.inner {
BlockItemInner::Register(register) => register.fieldset.map(|f| (b.name, f)),
_ => None,
})
.filter_map(|(b, f)| {
rcc_fieldsets.get(f).map(|f| {
(
b,
f.fields
.iter()
.filter_map(|f| {
let enumm = f.enumm?;
let enumm = rcc_enums.get(enumm)?;
Some((f.name, *enumm))
})
.collect(),
)
})
})
.collect()
};
// ========
// Generate RccPeripheral impls
@ -377,10 +448,8 @@ fn main() {
let rst_reg = format_ident!("{}", rst.register.to_ascii_lowercase());
let set_rst_field = format_ident!("set_{}", rst.field.to_ascii_lowercase());
quote! {
critical_section::with(|_| {
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(true));
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(false));
});
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(true));
crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(false));
}
}
None => TokenStream::new(),
@ -397,9 +466,9 @@ fn main() {
let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
let pname = format_ident!("{}", p.name);
let clk = format_ident!("{}", rcc.clock.to_ascii_lowercase());
let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
let clk = format_ident!("{}", rcc.clock);
let en_reg = format_ident!("{}", en.register);
let set_en_field = format_ident!("set_{}", en.field);
let (before_enable, before_disable) = if refcounted_peripherals.contains(ptype) {
let refcount_static =
@ -425,31 +494,82 @@ fn main() {
(TokenStream::new(), TokenStream::new())
};
let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g4", "l4"])
.contains(rcc_registers.version);
let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
// restrict mux implementation to supported versions
if !mux_supported {
return None;
}
let mux = mux?;
let fieldset = rcc_enum_map.get(mux.register)?;
let enumm = fieldset.get(mux.field)?;
Some((mux, *enumm))
};
let clock_frequency = match mux_for(rcc.mux.as_ref()) {
Some((mux, rcc_enumm)) => {
let fieldset_name = format_ident!("{}", mux.register);
let field_name = format_ident!("{}", mux.field);
let enum_name = format_ident!("{}", rcc_enumm.name);
let match_arms: TokenStream = rcc_enumm
.variants
.iter()
.filter(|v| v.name != "DISABLE")
.map(|v| {
let variant_name = format_ident!("{}", v.name);
let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" {
quote! {
#enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
}
} else {
quote! {
#enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
}
}
})
.collect();
quote! {
use crate::pac::rcc::vals::#enum_name;
#[allow(unreachable_patterns)]
match crate::pac::RCC.#fieldset_name().read().#field_name() {
#match_arms
_ => unreachable!(),
}
}
}
None => quote! {
unsafe { crate::rcc::get_freqs().#clk }
},
};
g.extend(quote! {
impl crate::rcc::sealed::RccPeripheral for peripherals::#pname {
fn frequency() -> crate::time::Hertz {
unsafe { crate::rcc::get_freqs().#clk }
#clock_frequency
}
fn enable() {
critical_section::with(|_| {
#before_enable
#[cfg(feature = "low-power")]
crate::rcc::clock_refcount_add();
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
#after_enable
})
}
fn disable() {
critical_section::with(|_| {
#before_disable
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(false));
#[cfg(feature = "low-power")]
crate::rcc::clock_refcount_sub();
})
}
fn reset() {
fn enable_and_reset_with_cs(_cs: critical_section::CriticalSection) {
#before_enable
#[cfg(feature = "low-power")]
crate::rcc::clock_refcount_add(_cs);
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
#after_enable
#rst
}
fn disable_with_cs(_cs: critical_section::CriticalSection) {
#before_disable
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(false));
#[cfg(feature = "low-power")]
crate::rcc::clock_refcount_sub(_cs);
}
}
impl crate::rcc::RccPeripheral for peripherals::#pname {}
@ -457,12 +577,14 @@ fn main() {
}
}
let mut refcount_mod = TokenStream::new();
for refcount_static in refcount_statics {
refcount_mod.extend(quote! {
pub(crate) static mut #refcount_static: u8 = 0;
});
}
let refcount_mod: TokenStream = refcount_statics
.iter()
.map(|refcount_static| {
quote! {
pub(crate) static mut #refcount_static: u8 = 0;
}
})
.collect();
g.extend(quote! {
mod refcount_statics {
@ -718,12 +840,17 @@ fn main() {
(("sdmmc", "D6"), quote!(crate::sdmmc::D6Pin)),
(("sdmmc", "D6"), quote!(crate::sdmmc::D7Pin)),
(("sdmmc", "D8"), quote!(crate::sdmmc::D8Pin)),
(("quadspi", "BK1_IO0"), quote!(crate::qspi::D0Pin)),
(("quadspi", "BK1_IO1"), quote!(crate::qspi::D1Pin)),
(("quadspi", "BK1_IO2"), quote!(crate::qspi::D2Pin)),
(("quadspi", "BK1_IO3"), quote!(crate::qspi::D3Pin)),
(("quadspi", "BK1_IO0"), quote!(crate::qspi::BK1D0Pin)),
(("quadspi", "BK1_IO1"), quote!(crate::qspi::BK1D1Pin)),
(("quadspi", "BK1_IO2"), quote!(crate::qspi::BK1D2Pin)),
(("quadspi", "BK1_IO3"), quote!(crate::qspi::BK1D3Pin)),
(("quadspi", "BK1_NCS"), quote!(crate::qspi::BK1NSSPin)),
(("quadspi", "BK2_IO0"), quote!(crate::qspi::BK2D0Pin)),
(("quadspi", "BK2_IO1"), quote!(crate::qspi::BK2D1Pin)),
(("quadspi", "BK2_IO2"), quote!(crate::qspi::BK2D2Pin)),
(("quadspi", "BK2_IO3"), quote!(crate::qspi::BK2D3Pin)),
(("quadspi", "BK2_NCS"), quote!(crate::qspi::BK2NSSPin)),
(("quadspi", "CLK"), quote!(crate::qspi::SckPin)),
(("quadspi", "BK1_NCS"), quote!(crate::qspi::NSSPin)),
].into();
for p in METADATA.peripherals {
@ -745,25 +872,8 @@ fn main() {
let af = pin.af.unwrap_or(0);
// MCO is special
if pin.signal.starts_with("MCO_") {
// Supported in H7 only for now
if regs.version.starts_with("h5")
|| regs.version.starts_with("h7")
|| regs.version.starts_with("f4")
{
peri = format_ident!("{}", pin.signal.replace('_', ""));
} else {
continue;
}
}
if pin.signal == "MCO" {
// Supported in H7 only for now
if regs.version.starts_with("l4") {
peri = format_ident!("MCO");
} else {
continue;
}
if pin.signal.starts_with("MCO") {
peri = format_ident!("{}", pin.signal.replace('_', ""));
}
g.extend(quote! {
@ -804,6 +914,20 @@ fn main() {
}
}
if regs.kind == "opamp" {
if !pin.signal.starts_with("VP") {
continue;
}
let peri = format_ident!("{}", p.name);
let pin_name = format_ident!("{}", pin.pin);
let ch: u8 = pin.signal.strip_prefix("VP").unwrap().parse().unwrap();
g.extend(quote! {
impl_opamp_pin!( #peri, #pin_name, #ch);
})
}
// DAC is special
if regs.kind == "dac" {
let peri = format_ident!("{}", p.name);
@ -888,6 +1012,97 @@ fn main() {
}
}
// ========
// Generate Div/Mul impls for RCC prescalers/dividers/multipliers.
for e in rcc_registers.ir.enums {
fn is_rcc_name(e: &str) -> bool {
match e {
"Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true,
"Timpre" | "Pllrclkpre" => false,
e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
_ => false,
}
}
#[derive(Copy, Clone, Debug)]
struct Frac {
num: u32,
denom: u32,
}
impl Frac {
fn simplify(self) -> Self {
let d = gcd(self.num, self.denom);
Self {
num: self.num / d,
denom: self.denom / d,
}
}
}
fn gcd(a: u32, b: u32) -> u32 {
if b == 0 {
return a;
}
gcd(b, a % b)
}
fn parse_num(n: &str) -> Result<Frac, ()> {
for prefix in ["DIV", "MUL"] {
if let Some(n) = n.strip_prefix(prefix) {
let exponent = n.find('_').map(|e| n.len() - 1 - e).unwrap_or(0) as u32;
let mantissa = n.replace('_', "").parse().map_err(|_| ())?;
let f = Frac {
num: mantissa,
denom: 10u32.pow(exponent),
};
return Ok(f.simplify());
}
}
Err(())
}
if is_rcc_name(e.name) {
let enum_name = format_ident!("{}", e.name);
let mut muls = Vec::new();
let mut divs = Vec::new();
for v in e.variants {
let Ok(val) = parse_num(v.name) else {
panic!("could not parse mul/div. enum={} variant={}", e.name, v.name)
};
let variant_name = format_ident!("{}", v.name);
let variant = quote!(crate::pac::rcc::vals::#enum_name::#variant_name);
let num = val.num;
let denom = val.denom;
muls.push(quote!(#variant => self * #num / #denom,));
divs.push(quote!(#variant => self * #denom / #num,));
}
g.extend(quote! {
impl core::ops::Div<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
type Output = crate::time::Hertz;
fn div(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
match rhs {
#(#divs)*
#[allow(unreachable_patterns)]
_ => unreachable!(),
}
}
}
impl core::ops::Mul<crate::pac::rcc::vals::#enum_name> for crate::time::Hertz {
type Output = crate::time::Hertz;
fn mul(self, rhs: crate::pac::rcc::vals::#enum_name) -> Self::Output {
match rhs {
#(#muls)*
#[allow(unreachable_patterns)]
_ => unreachable!(),
}
}
}
});
}
}
// ========
// Write foreach_foo! macrotables

3
embassy-stm32/src/adc/f1.rs
View File

@ -51,8 +51,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::enable();
T::reset();
T::enable_and_reset();
T::regs().cr2().modify(|reg| reg.set_adon(true));
// 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)

3
embassy-stm32/src/adc/f3.rs
View File

@ -64,8 +64,7 @@ impl<'d, T: Instance> Adc<'d, T> {
into_ref!(adc);
T::enable();
T::reset();
T::enable_and_reset();
// Enable the adc regulator
T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE));

4
embassy-stm32/src/adc/mod.rs
View File

@ -74,9 +74,9 @@ pub(crate) mod sealed {
}
}
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3)))]
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3))]
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}

3
embassy-stm32/src/adc/v1.rs
View File

@ -61,8 +61,7 @@ impl<'d, T: Instance> Adc<'d, T> {
delay: &mut impl DelayUs<u32>,
) -> Self {
into_ref!(adc);
T::enable();
T::reset();
T::enable_and_reset();
// Delay 1μs when using HSI14 as the ADC clock.
//

3
embassy-stm32/src/adc/v2.rs
View File

@ -95,8 +95,7 @@ where
{
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::enable();
T::reset();
T::enable_and_reset();
let presc = Prescaler::from_pclk2(T::frequency());
T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));

15
embassy-stm32/src/adc/v3.rs
View File

@ -9,19 +9,6 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
/// VREF voltage used for factory calibration of VREFINTCAL register.
pub const VREF_CALIB_MV: u32 = 3000;
/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
/// configuration.
fn enable() {
critical_section::with(|_| {
#[cfg(any(stm32h7, stm32wl))]
crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
#[cfg(stm32g0)]
crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
#[cfg(any(stm32l4, stm32l5, stm32wb))]
crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
});
}
pub struct VrefInt;
impl<T: Instance> AdcPin<T> for VrefInt {}
impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
@ -61,7 +48,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
enable();
T::enable_and_reset();
T::regs().cr().modify(|reg| {
#[cfg(not(adc_g0))]
reg.set_deeppwd(false);

3
embassy-stm32/src/adc/v4.rs
View File

@ -127,8 +127,7 @@ impl Prescaler {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u16>) -> Self {
embassy_hal_internal::into_ref!(adc);
T::enable();
T::reset();
T::enable_and_reset();
let prescaler = Prescaler::from_ker_ck(T::frequency());

3
embassy-stm32/src/can/bxcan.rs
View File

@ -136,8 +136,7 @@ impl<'d, T: Instance> Can<'d, T> {
rx.set_as_af(rx.af_num(), AFType::Input);
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
T::enable();
T::reset();
T::enable_and_reset();
{
use crate::pac::can::vals::{Errie, Fmpie, Tmeie};

4
embassy-stm32/src/crc/v1.rs
View File

@ -16,9 +16,7 @@ impl<'d> Crc<'d> {
// Note: enable and reset come from RccPeripheral.
// enable CRC clock in RCC.
CRC::enable();
// Reset CRC to default values.
CRC::reset();
CRC::enable_and_reset();
// Peripheral the peripheral
let mut instance = Self { _peri: peripheral };
instance.reset();

7
embassy-stm32/src/crc/v2v3.rs
View File

@ -69,16 +69,13 @@ impl<'d> Crc<'d> {
/// Instantiates the CRC32 peripheral and initializes it to default values.
pub fn new(peripheral: impl Peripheral<P = CRC> + 'd, config: Config) -> Self {
// Note: enable and reset come from RccPeripheral.
// enable CRC clock in RCC.
CRC::enable();
// Reset CRC to default values.
CRC::reset();
// reset to default values and enable CRC clock in RCC.
CRC::enable_and_reset();
into_ref!(peripheral);
let mut instance = Self {
_peripheral: peripheral,
_config: config,
};
CRC::reset();
instance.reconfigure();
instance.reset();
instance

54
embassy-stm32/src/dac/mod.rs
View File

@ -11,7 +11,7 @@ use crate::{peripherals, Peripheral};
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
/// Curstom Errors
/// Custom Errors
pub enum Error {
UnconfiguredChannel,
InvalidValue,
@ -255,8 +255,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
) -> Self {
pin.set_as_analog();
into_ref!(peri, dma);
T::enable();
T::reset();
T::enable_and_reset();
let mut dac = Self { _peri: peri, dma };
@ -366,8 +365,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
) -> Self {
pin.set_as_analog();
into_ref!(_peri, dma);
T::enable();
T::reset();
T::enable_and_reset();
let mut dac = Self {
phantom: PhantomData,
@ -483,8 +481,7 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
pin_ch1.set_as_analog();
pin_ch2.set_as_analog();
into_ref!(peri, dma_ch1, dma_ch2);
T::enable();
T::reset();
T::enable_and_reset();
let mut dac_ch1 = DacCh1 {
_peri: peri,
@ -563,35 +560,26 @@ pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
foreach_peripheral!(
(dac, $inst:ident) => {
// H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
#[cfg(rcc_h7)]
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
fn frequency() -> crate::time::Hertz {
critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
}
// H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
#[cfg(any(rcc_h7, rcc_h7rm0433))]
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
fn frequency() -> crate::time::Hertz {
critical_section::with(|_| unsafe { crate::rcc::get_freqs().pclk1 })
}
fn reset() {
critical_section::with(|_| {
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
})
}
fn enable_and_reset_with_cs(_cs: critical_section::CriticalSection) {
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
}
fn enable() {
critical_section::with(|_| {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
})
}
fn disable_with_cs(_cs: critical_section::CriticalSection) {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
}
}
fn disable() {
critical_section::with(|_| {
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
})
}
}
#[cfg(rcc_h7)]
impl crate::rcc::RccPeripheral for peripherals::$inst {}
#[cfg(any(rcc_h7, rcc_h7rm0433))]
impl crate::rcc::RccPeripheral for peripherals::$inst {}
impl crate::dac::sealed::Instance for peripherals::$inst {
fn regs() -> &'static crate::pac::dac::Dac {

3
embassy-stm32/src/dcmi.rs
View File

@ -330,8 +330,7 @@ where
use_embedded_synchronization: bool,
edm: u8,
) -> Self {
T::reset();
T::enable();
T::enable_and_reset();
peri.regs().cr().modify(|r| {
r.set_cm(true); // disable continuous mode (snapshot mode)

22
embassy-stm32/src/dma/bdma.rs
View File

@ -2,10 +2,9 @@
use core::future::Future;
use core::pin::Pin;
use core::sync::atomic::{fence, Ordering};
use core::sync::atomic::{fence, AtomicUsize, Ordering};
use core::task::{Context, Poll, Waker};
use atomic_polyfill::AtomicUsize;
use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -78,10 +77,10 @@ impl State {
static STATE: State = State::new();
/// safety: must be called only once
pub(crate) unsafe fn init(irq_priority: Priority) {
pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
crate::interrupt::typelevel::$irq::set_priority(irq_priority);
crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
crate::interrupt::typelevel::$irq::enable();
};
}
@ -127,7 +126,13 @@ pub(crate) unsafe fn on_irq_inner(dma: pac::bdma::Dma, channel_num: usize, index
} else if isr.tcif(channel_num) && cr.read().tcie() {
// Acknowledge transfer complete interrupt
dma.ifcr().write(|w| w.set_tcif(channel_num, true));
#[cfg(not(armv6m))]
STATE.complete_count[index].fetch_add(1, Ordering::Release);
#[cfg(armv6m)]
critical_section::with(|_| {
let x = STATE.complete_count[index].load(Ordering::Relaxed);
STATE.complete_count[index].store(x + 1, Ordering::Release);
})
} else {
return;
}
@ -391,7 +396,14 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
}
fn reset_complete_count(&mut self) -> usize {
STATE.complete_count[self.0.index()].swap(0, Ordering::AcqRel)
#[cfg(not(armv6m))]
return STATE.complete_count[self.0.index()].swap(0, Ordering::AcqRel);
#[cfg(armv6m)]
return critical_section::with(|_| {
let x = STATE.complete_count[self.0.index()].load(Ordering::Acquire);
STATE.complete_count[self.0.index()].store(0, Ordering::Release);
x
});
}
fn set_waker(&mut self, waker: &Waker) {

4
embassy-stm32/src/dma/dma.rs
View File

@ -154,10 +154,10 @@ impl State {
static STATE: State = State::new();
/// safety: must be called only once
pub(crate) unsafe fn init(irq_priority: Priority) {
pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
interrupt::typelevel::$irq::set_priority(irq_priority);
interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
interrupt::typelevel::$irq::enable();
};
}

2
embassy-stm32/src/dma/dmamux.rs
View File

@ -47,6 +47,6 @@ foreach_dma_channel! {
}
/// safety: must be called only once
pub(crate) unsafe fn init() {
pub(crate) unsafe fn init(_cs: critical_section::CriticalSection) {
crate::_generated::init_dmamux();
}

4
embassy-stm32/src/dma/gpdma.rs
View File

@ -53,10 +53,10 @@ impl State {
static STATE: State = State::new();
/// safety: must be called only once
pub(crate) unsafe fn init(irq_priority: Priority) {
pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
crate::interrupt::typelevel::$irq::set_priority(irq_priority);
crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
crate::interrupt::typelevel::$irq::enable();
};
}

9
embassy-stm32/src/dma/mod.rs
View File

@ -56,16 +56,17 @@ pub(crate) fn slice_ptr_parts_mut<T>(slice: *mut [T]) -> (usize, usize) {
// safety: must be called only once at startup
pub(crate) unsafe fn init(
cs: critical_section::CriticalSection,
#[cfg(bdma)] bdma_priority: Priority,
#[cfg(dma)] dma_priority: Priority,
#[cfg(gpdma)] gpdma_priority: Priority,
) {
#[cfg(bdma)]
bdma::init(bdma_priority);
bdma::init(cs, bdma_priority);
#[cfg(dma)]
dma::init(dma_priority);
dma::init(cs, dma_priority);
#[cfg(gpdma)]
gpdma::init(gpdma_priority);
gpdma::init(cs, gpdma_priority);
#[cfg(dmamux)]
dmamux::init();
dmamux::init(cs);
}

33
embassy-stm32/src/eth/generic_smi.rs
View File

@ -41,39 +41,40 @@ mod phy_consts {
}
use self::phy_consts::*;
/// Generic SMI Ethernet PHY
/// Generic SMI Ethernet PHY implementation
pub struct GenericSMI {
phy_addr: u8,
#[cfg(feature = "time")]
poll_interval: Duration,
#[cfg(not(feature = "time"))]
_private: (),
}
impl GenericSMI {
pub fn new() -> Self {
/// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
pub fn new(phy_addr: u8) -> Self {
Self {
phy_addr,
#[cfg(feature = "time")]
poll_interval: Duration::from_millis(500),
#[cfg(not(feature = "time"))]
_private: (),
}
}
}
unsafe impl PHY for GenericSMI {
/// Reset PHY and wait for it to come out of reset.
fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
sm.smi_write(PHY_REG_BCR, PHY_REG_BCR_RESET);
while sm.smi_read(PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
}
/// PHY initialisation.
fn phy_init<S: StationManagement>(&mut self, sm: &mut S) {
// Clear WU CSR
self.smi_write_ext(sm, PHY_REG_WUCSR, 0);
// Enable auto-negotiation
sm.smi_write(PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M);
sm.smi_write(
self.phy_addr,
PHY_REG_BCR,
PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
);
}
fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool {
@ -83,7 +84,7 @@ unsafe impl PHY for GenericSMI {
#[cfg(feature = "time")]
let _ = Timer::after(self.poll_interval).poll_unpin(cx);
let bsr = sm.smi_read(PHY_REG_BSR);
let bsr = sm.smi_read(self.phy_addr, PHY_REG_BSR);
// No link without autonegotiate
if bsr & PHY_REG_BSR_ANDONE == 0 {
@ -108,9 +109,9 @@ impl GenericSMI {
// Writes a value to an extended PHY register in MMD address space
fn smi_write_ext<S: StationManagement>(&mut self, sm: &mut S, reg_addr: u16, reg_data: u16) {
sm.smi_write(PHY_REG_CTL, 0x0003); // set address
sm.smi_write(PHY_REG_ADDAR, reg_addr);
sm.smi_write(PHY_REG_CTL, 0x4003); // set data
sm.smi_write(PHY_REG_ADDAR, reg_data);
sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
}
}

4
embassy-stm32/src/eth/mod.rs
View File

@ -134,9 +134,9 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> {
/// The methods cannot move out of self
pub unsafe trait StationManagement {
/// Read a register over SMI.
fn smi_read(&mut self, reg: u8) -> u16;
fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
/// Write a register over SMI.
fn smi_write(&mut self, reg: u8, val: u16);
fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
}
/// Traits for an Ethernet PHY

13
embassy-stm32/src/eth/v1/mod.rs
View File

@ -107,7 +107,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
phy: P,
mac_addr: [u8; 6],
phy_addr: u8,
) -> Self {
into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
@ -192,7 +191,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
// TODO MTU size setting not found for v1 ethernet, check if correct
// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
let hclk = unsafe { crate::rcc::get_freqs() }.ahb1;
let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
let hclk_mhz = hclk.0 / 1_000_000;
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
@ -227,7 +226,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
station_management: EthernetStationManagement {
peri: PhantomData,
clock_range: clock_range,
phy_addr: phy_addr,
},
mac_addr,
tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
@ -271,15 +269,14 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
pub struct EthernetStationManagement<T: Instance> {
peri: PhantomData<T>,
clock_range: Cr,
phy_addr: u8,
}
unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
fn smi_read(&mut self, reg: u8) -> u16 {
fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
let mac = ETH.ethernet_mac();
mac.macmiiar().modify(|w| {
w.set_pa(self.phy_addr);
w.set_pa(phy_addr);
w.set_mr(reg);
w.set_mw(Mw::READ); // read operation
w.set_cr(self.clock_range);
@ -289,12 +286,12 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
mac.macmiidr().read().md()
}
fn smi_write(&mut self, reg: u8, val: u16) {
fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
let mac = ETH.ethernet_mac();
mac.macmiidr().write(|w| w.set_md(val));
mac.macmiiar().modify(|w| {
w.set_pa(self.phy_addr);
w.set_pa(phy_addr);
w.set_mr(reg);
w.set_mw(Mw::WRITE); // write
w.set_cr(self.clock_range);

13
embassy-stm32/src/eth/v2/mod.rs
View File

@ -71,7 +71,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
phy: P,
mac_addr: [u8; 6],
phy_addr: u8,
) -> Self {
into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
@ -165,7 +164,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
});
// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
let hclk = unsafe { crate::rcc::get_freqs() }.ahb1;
let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
let hclk_mhz = hclk.0 / 1_000_000;
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
@ -202,7 +201,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
station_management: EthernetStationManagement {
peri: PhantomData,
clock_range: clock_range,
phy_addr: phy_addr,
},
mac_addr,
};
@ -242,15 +240,14 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
pub struct EthernetStationManagement<T: Instance> {
peri: PhantomData<T>,
clock_range: u8,
phy_addr: u8,
}
unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
fn smi_read(&mut self, reg: u8) -> u16 {
fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
let mac = ETH.ethernet_mac();
mac.macmdioar().modify(|w| {
w.set_pa(self.phy_addr);
w.set_pa(phy_addr);
w.set_rda(reg);
w.set_goc(0b11); // read
w.set_cr(self.clock_range);
@ -260,12 +257,12 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
mac.macmdiodr().read().md()
}
fn smi_write(&mut self, reg: u8, val: u16) {
fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
let mac = ETH.ethernet_mac();
mac.macmdiodr().write(|w| w.set_md(val));
mac.macmdioar().modify(|w| {
w.set_pa(self.phy_addr);
w.set_pa(phy_addr);
w.set_rda(reg);
w.set_goc(0b01); // write
w.set_cr(self.clock_range);

2
embassy-stm32/src/exti.rs
View File

@ -367,7 +367,7 @@ macro_rules! enable_irq {
}
/// safety: must be called only once
pub(crate) unsafe fn init() {
pub(crate) unsafe fn init(_cs: critical_section::CriticalSection) {
use crate::interrupt::typelevel::Interrupt;
foreach_exti_irq!(enable_irq);

6
embassy-stm32/src/flash/f0.rs
View File

@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
}
pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
}
}
pub(crate) unsafe fn enable_blocking_write() {

6
embassy-stm32/src/flash/f3.rs
View File

@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
}
pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_fkeyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
}
}
pub(crate) unsafe fn enable_blocking_write() {

6
embassy-stm32/src/flash/f4.rs
View File

@ -228,8 +228,10 @@ pub(crate) unsafe fn lock() {
}
pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_key(0x45670123));
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_key(0x45670123));
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF89AB));
}
}
pub(crate) unsafe fn enable_write() {

6
embassy-stm32/src/flash/f7.rs
View File

@ -19,8 +19,10 @@ pub(crate) unsafe fn lock() {
}
pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_key(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_key(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
}
}
pub(crate) unsafe fn enable_blocking_write() {

6
embassy-stm32/src/flash/g0.rs
View File

@ -24,8 +24,10 @@ pub(crate) unsafe fn unlock() {
while pac::FLASH.sr().read().bsy() {}
// Unlock flash
pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
}
}
pub(crate) unsafe fn enable_blocking_write() {

12
embassy-stm32/src/flash/h7.rs
View File

@ -26,11 +26,15 @@ pub(crate) unsafe fn lock() {
}
pub(crate) unsafe fn unlock() {
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
if pac::FLASH.bank(0).cr().read().lock() {
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
}
if is_dual_bank() {
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
if pac::FLASH.bank(1).cr().read().lock() {
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
}
}
}

18
embassy-stm32/src/flash/l.rs
View File

@ -28,17 +28,23 @@ pub(crate) unsafe fn lock() {
pub(crate) unsafe fn unlock() {
#[cfg(any(flash_wl, flash_wb, flash_l4))]
{
pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
if pac::FLASH.cr().read().lock() {
pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
}
}
#[cfg(any(flash_l0, flash_l1))]
{
pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
if pac::FLASH.pecr().read().pelock() {
pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
}
pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
if pac::FLASH.pecr().read().prglock() {
pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
}
}
}

3
embassy-stm32/src/fmc.rs
View File

@ -19,8 +19,7 @@ where
const REGISTERS: *const () = T::REGS.as_ptr() as *const _;
fn enable(&mut self) {
<T as crate::rcc::sealed::RccPeripheral>::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
T::enable_and_reset();
}
fn memory_controller_enable(&mut self) {

17
embassy-stm32/src/gpio.rs
View File

@ -1,6 +1,7 @@
#![macro_use]
use core::convert::Infallible;
use critical_section::CriticalSection;
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
use crate::pac::gpio::{self, vals};
@ -757,9 +758,9 @@ foreach_pin!(
};
);
pub(crate) unsafe fn init() {
pub(crate) unsafe fn init(_cs: CriticalSection) {
#[cfg(afio)]
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable_and_reset_with_cs(_cs);
crate::_generated::init_gpio();
}
@ -974,6 +975,18 @@ mod eh1 {
type Error = Infallible;
}
impl<'d, T: Pin> InputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {

3
embassy-stm32/src/hrtim/mod.rs
View File

@ -157,8 +157,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(tim);
T::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
T::enable_and_reset();
#[cfg(stm32f334)]
if unsafe { get_freqs() }.hrtim.is_some() {

7
embassy-stm32/src/i2c/mod.rs
View File

@ -7,14 +7,9 @@ use crate::interrupt;
mod _version;
pub use _version::*;
#[cfg(feature = "time")]
mod timeout;
#[cfg(feature = "time")]
pub use timeout::*;
use crate::peripherals;
#[derive(Debug)]
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
Bus,

209
embassy-stm32/src/i2c/timeout.rs
View File

@ -1,209 +0,0 @@
use embassy_time::{Duration, Instant};
use super::{Error, I2c, Instance};
/// An I2C wrapper, which provides `embassy-time` based timeouts for all `embedded-hal` trait methods.
///
/// This is useful for recovering from a shorted bus or a device stuck in a clock stretching state.
/// A regular [I2c] would freeze until condition is removed.
pub struct TimeoutI2c<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> {
i2c: &'a mut I2c<'d, T, TXDMA, RXDMA>,
timeout: Duration,
}
fn timeout_fn(timeout: Duration) -> impl Fn() -> Result<(), Error> {
let deadline = Instant::now() + timeout;
move || {
if Instant::now() > deadline {
Err(Error::Timeout)
} else {
Ok(())
}
}
}
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> TimeoutI2c<'a, 'd, T, TXDMA, RXDMA> {
pub fn new(i2c: &'a mut I2c<'d, T, TXDMA, RXDMA>, timeout: Duration) -> Self {
Self { i2c, timeout }
}
// =========================
// Async public API
#[cfg(i2c_v2)]
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_timeout(address, write, self.timeout).await
}
#[cfg(i2c_v2)]
pub async fn write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.i2c.write_timeout(address, write, timeout_fn(timeout)).await
}
#[cfg(i2c_v2)]
pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_vectored_timeout(address, write, self.timeout).await
}
#[cfg(i2c_v2)]
pub async fn write_vectored_timeout(&mut self, address: u8, write: &[&[u8]], timeout: Duration) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.i2c
.write_vectored_timeout(address, write, timeout_fn(timeout))
.await
}
#[cfg(i2c_v2)]
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
self.read_timeout(address, buffer, self.timeout).await
}
#[cfg(i2c_v2)]
pub async fn read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
self.i2c.read_timeout(address, buffer, timeout_fn(timeout)).await
}
#[cfg(i2c_v2)]
pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
{
self.write_read_timeout(address, write, read, self.timeout).await
}
#[cfg(i2c_v2)]
pub async fn write_read_timeout(
&mut self,
address: u8,
write: &[u8],
read: &mut [u8],
timeout: Duration,
) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
{
self.i2c
.write_read_timeout(address, write, read, timeout_fn(timeout))
.await
}
// =========================
// Blocking public API
/// Blocking read with a custom timeout
pub fn blocking_read_timeout(&mut self, addr: u8, read: &mut [u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_read_timeout(addr, read, timeout_fn(timeout))
}
/// Blocking read with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(addr, read, self.timeout)
}
/// Blocking write with a custom timeout
pub fn blocking_write_timeout(&mut self, addr: u8, write: &[u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_write_timeout(addr, write, timeout_fn(timeout))
}
/// Blocking write with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(addr, write, self.timeout)
}
/// Blocking write-read with a custom timeout
pub fn blocking_write_read_timeout(
&mut self,
addr: u8,
write: &[u8],
read: &mut [u8],
timeout: Duration,
) -> Result<(), Error> {
self.i2c
.blocking_write_read_timeout(addr, write, read, timeout_fn(timeout))
}
/// Blocking write-read with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(addr, write, read, self.timeout)
}
}
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::Read
for TimeoutI2c<'a, 'd, T, TXDMA, RXDMA>
{
type Error = Error;
fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(addr, read)
}
}
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::Write
for TimeoutI2c<'a, 'd, T, TXDMA, RXDMA>
{
type Error = Error;
fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(addr, write)
}
}
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::WriteRead
for TimeoutI2c<'a, 'd, T, TXDMA, RXDMA>
{
type Error = Error;
fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(addr, write, read)
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::ErrorType for TimeoutI2c<'a, 'd, T, TXDMA, RXDMA> {
type Error = Error;
}
impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::I2c for TimeoutI2c<'a, 'd, T, TXDMA, RXDMA> {
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
}
}

8
embassy-stm32/src/i2c/v1.rs
View File

@ -56,8 +56,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
) -> Self {
into_ref!(scl, sda, tx_dma, rx_dma);
T::enable();
T::reset();
T::enable_and_reset();
scl.set_as_af_pull(
scl.af_num(),
@ -518,7 +517,8 @@ impl Timings {
impl<'d, T: Instance> SetConfig for I2c<'d, T> {
type Config = Hertz;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
let timings = Timings::new(T::frequency(), *config);
T::regs().cr2().modify(|reg| {
reg.set_freq(timings.freq);
@ -531,5 +531,7 @@ impl<'d, T: Instance> SetConfig for I2c<'d, T> {
T::regs().trise().modify(|reg| {
reg.set_trise(timings.trise);
});
Ok(())
}
}

211
embassy-stm32/src/i2c/v2.rs
View File

@ -1,14 +1,21 @@
use core::cmp;
#[cfg(feature = "time")]
use core::future::poll_fn;
use core::marker::PhantomData;
#[cfg(feature = "time")]
use core::task::Poll;
use embassy_embedded_hal::SetConfig;
#[cfg(feature = "time")]
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
#[cfg(feature = "time")]
use embassy_time::{Duration, Instant};
use crate::dma::{NoDma, Transfer};
use crate::dma::NoDma;
#[cfg(feature = "time")]
use crate::dma::Transfer;
use crate::gpio::sealed::AFType;
use crate::gpio::Pull;
use crate::i2c::{Error, Instance, SclPin, SdaPin};
@ -43,6 +50,8 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
pub struct Config {
pub sda_pullup: bool,
pub scl_pullup: bool,
#[cfg(feature = "time")]
pub transaction_timeout: Duration,
}
impl Default for Config {
@ -50,6 +59,8 @@ impl Default for Config {
Self {
sda_pullup: false,
scl_pullup: false,
#[cfg(feature = "time")]
transaction_timeout: Duration::from_millis(100),
}
}
}
@ -68,9 +79,12 @@ impl State {
pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
_peri: PeripheralRef<'d, T>,
#[allow(dead_code)]
tx_dma: PeripheralRef<'d, TXDMA>,
#[allow(dead_code)]
rx_dma: PeripheralRef<'d, RXDMA>,
#[cfg(feature = "time")]
timeout: Duration,
}
impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
@ -86,8 +100,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
) -> Self {
into_ref!(peri, scl, sda, tx_dma, rx_dma);
T::enable();
T::reset();
T::enable_and_reset();
scl.set_as_af_pull(
scl.af_num(),
@ -132,6 +145,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
_peri: peri,
tx_dma,
rx_dma,
#[cfg(feature = "time")]
timeout: config.transaction_timeout,
}
}
@ -422,6 +437,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
result
}
#[cfg(feature = "time")]
async fn write_dma_internal(
&mut self,
address: u8,
@ -512,6 +528,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
Ok(())
}
#[cfg(feature = "time")]
async fn read_dma_internal(
&mut self,
address: u8,
@ -594,42 +611,41 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// =========================
// Async public API
#[cfg(feature = "time")]
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_timeout(address, write, || Ok(())).await
self.write_timeout(address, write, self.timeout).await
}
pub async fn write_timeout(
&mut self,
address: u8,
write: &[u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error>
#[cfg(feature = "time")]
pub async fn write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
if write.is_empty() {
self.write_internal(address, write, true, check_timeout)
self.write_internal(address, write, true, timeout_fn(timeout))
} else {
self.write_dma_internal(address, write, true, true, check_timeout).await
embassy_time::with_timeout(
timeout,
self.write_dma_internal(address, write, true, true, timeout_fn(timeout)),
)
.await
.unwrap_or(Err(Error::Timeout))
}
}
#[cfg(feature = "time")]
pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_vectored_timeout(address, write, || Ok(())).await
self.write_vectored_timeout(address, write, self.timeout).await
}
pub async fn write_vectored_timeout(
&mut self,
address: u8,
write: &[&[u8]],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error>
#[cfg(feature = "time")]
pub async fn write_vectored_timeout(&mut self, address: u8, write: &[&[u8]], timeout: Duration) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
@ -644,67 +660,88 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
let next = iter.next();
let is_last = next.is_none();
self.write_dma_internal(address, c, first, is_last, || check_timeout())
.await?;
embassy_time::with_timeout(
timeout,
self.write_dma_internal(address, c, first, is_last, timeout_fn(timeout)),
)
.await
.unwrap_or(Err(Error::Timeout))?;
first = false;
current = next;
}
Ok(())
}
#[cfg(feature = "time")]
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
self.read_timeout(address, buffer, || Ok(())).await
self.read_timeout(address, buffer, self.timeout).await
}
pub async fn read_timeout(
&mut self,
address: u8,
buffer: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error>
#[cfg(feature = "time")]
pub async fn read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
if buffer.is_empty() {
self.read_internal(address, buffer, false, check_timeout)
self.read_internal(address, buffer, false, timeout_fn(timeout))
} else {
self.read_dma_internal(address, buffer, false, check_timeout).await
embassy_time::with_timeout(
timeout,
self.read_dma_internal(address, buffer, false, timeout_fn(timeout)),
)
.await
.unwrap_or(Err(Error::Timeout))
}
}
#[cfg(feature = "time")]
pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
{
self.write_read_timeout(address, write, read, || Ok(())).await
self.write_read_timeout(address, write, read, self.timeout).await
}
#[cfg(feature = "time")]
pub async fn write_read_timeout(
&mut self,
address: u8,
write: &[u8],
read: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
timeout: Duration,
) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
{
let start_instant = Instant::now();
let check_timeout = timeout_fn(timeout);
if write.is_empty() {
self.write_internal(address, write, false, || check_timeout())?;
self.write_internal(address, write, false, &check_timeout)?;
} else {
self.write_dma_internal(address, write, true, true, || check_timeout())
.await?;
embassy_time::with_timeout(
timeout,
self.write_dma_internal(address, write, true, true, &check_timeout),
)
.await
.unwrap_or(Err(Error::Timeout))?;
}
let time_left_until_timeout = timeout - Instant::now().duration_since(start_instant);
if read.is_empty() {
self.read_internal(address, read, true, check_timeout)?;
self.read_internal(address, read, true, &check_timeout)?;
} else {
self.read_dma_internal(address, read, true, check_timeout).await?;
embassy_time::with_timeout(
time_left_until_timeout,
self.read_dma_internal(address, read, true, &check_timeout),
)
.await
.unwrap_or(Err(Error::Timeout))?;
}
Ok(())
@ -713,33 +750,73 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// =========================
// Blocking public API
#[cfg(feature = "time")]
pub fn blocking_read_timeout(&mut self, address: u8, read: &mut [u8], timeout: Duration) -> Result<(), Error> {
self.read_internal(address, read, false, timeout_fn(timeout))
// Automatic Stop
}
#[cfg(not(feature = "time"))]
pub fn blocking_read_timeout(
&mut self,
address: u8,
read: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.read_internal(address, read, false, &check_timeout)
self.read_internal(address, read, false, check_timeout)
// Automatic Stop
}
#[cfg(feature = "time")]
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(address, read, self.timeout)
}
#[cfg(not(feature = "time"))]
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(address, read, || Ok(()))
}
#[cfg(feature = "time")]
pub fn blocking_write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error> {
self.write_internal(address, write, true, timeout_fn(timeout))
}
#[cfg(not(feature = "time"))]
pub fn blocking_write_timeout(
&mut self,
address: u8,
write: &[u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.write_internal(address, write, true, &check_timeout)
self.write_internal(address, write, true, check_timeout)
}
#[cfg(feature = "time")]
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(address, write, self.timeout)
}
#[cfg(not(feature = "time"))]
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(address, write, || Ok(()))
}
#[cfg(feature = "time")]
pub fn blocking_write_read_timeout(
&mut self,
address: u8,
write: &[u8],
read: &mut [u8],
timeout: Duration,
) -> Result<(), Error> {
let check_timeout = timeout_fn(timeout);
self.write_internal(address, write, false, &check_timeout)?;
self.read_internal(address, read, true, &check_timeout)
// Automatic Stop
}
#[cfg(not(feature = "time"))]
pub fn blocking_write_read_timeout(
&mut self,
address: u8,
@ -752,11 +829,17 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// Automatic Stop
}
#[cfg(feature = "time")]
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(address, write, read, self.timeout)
}
#[cfg(not(feature = "time"))]
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(address, write, read, || Ok(()))
}
pub fn blocking_write_vectored_timeout(
fn blocking_write_vectored_with_timeout(
&mut self,
address: u8,
write: &[&[u8]],
@ -765,6 +848,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
if write.is_empty() {
return Err(Error::ZeroLengthTransfer);
}
let first_length = write[0].len();
let last_slice_index = write.len() - 1;
@ -833,6 +917,33 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
result
}
#[cfg(feature = "time")]
pub fn blocking_write_vectored_timeout(
&mut self,
address: u8,
write: &[&[u8]],
timeout: Duration,
) -> Result<(), Error> {
let check_timeout = timeout_fn(timeout);
self.blocking_write_vectored_with_timeout(address, write, check_timeout)
}
#[cfg(not(feature = "time"))]
pub fn blocking_write_vectored_timeout(
&mut self,
address: u8,
write: &[&[u8]],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.blocking_write_vectored_with_timeout(address, write, check_timeout)
}
#[cfg(feature = "time")]
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
self.blocking_write_vectored_timeout(address, write, self.timeout)
}
#[cfg(not(feature = "time"))]
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
self.blocking_write_vectored_timeout(address, write, || Ok(()))
}
@ -844,6 +955,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
}
}
#[cfg(feature = "time")]
mod eh02 {
use super::*;
@ -1043,7 +1155,7 @@ mod eh1 {
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
#[cfg(all(feature = "unstable-traits", feature = "nightly", feature = "time"))]
mod eha {
use super::super::{RxDma, TxDma};
use super::*;
@ -1075,7 +1187,8 @@ mod eha {
impl<'d, T: Instance> SetConfig for I2c<'d, T> {
type Config = Hertz;
fn set_config(&mut self, config: &Self::Config) {
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
let timings = Timings::new(T::frequency(), *config);
T::regs().timingr().write(|reg| {
reg.set_presc(timings.prescale);
@ -1084,5 +1197,19 @@ impl<'d, T: Instance> SetConfig for I2c<'d, T> {
reg.set_sdadel(timings.sdadel);
reg.set_scldel(timings.scldel);
});
Ok(())
}
}
#[cfg(feature = "time")]
fn timeout_fn(timeout: Duration) -> impl Fn() -> Result<(), Error> {
let deadline = Instant::now() + timeout;
move || {
if Instant::now() > deadline {
Err(Error::Timeout)
} else {
Ok(())
}
}
}

2
embassy-stm32/src/i2s.rs
View File

@ -170,7 +170,7 @@ impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> {
let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
#[cfg(all(rcc_f4, not(stm32f410)))]
let pclk = unsafe { get_freqs() }.plli2s.unwrap();
let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
#[cfg(stm32f410)]
let pclk = T::frequency();

3
embassy-stm32/src/ipcc.rs
View File

@ -93,8 +93,7 @@ pub struct Ipcc;
impl Ipcc {
pub fn enable(_config: Config) {
IPCC::enable();
IPCC::reset();
IPCC::enable_and_reset();
IPCC::set_cpu2(true);
_configure_pwr();

151
embassy-stm32/src/lib.rs
View File

@ -1,5 +1,5 @@
#![cfg_attr(not(test), no_std)]
#![cfg_attr(feature = "nightly", feature(async_fn_in_trait, impl_trait_projections))]
#![cfg_attr(feature = "nightly", feature(async_fn_in_trait))]
//! ## Feature flags
#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
@ -49,6 +49,8 @@ pub mod i2s;
pub mod ipcc;
#[cfg(feature = "low-power")]
pub mod low_power;
#[cfg(opamp)]
pub mod opamp;
#[cfg(quadspi)]
pub mod qspi;
#[cfg(rng)]
@ -153,79 +155,82 @@ impl Default for Config {
/// Initialize embassy.
pub fn init(config: Config) -> Peripherals {
let p = Peripherals::take();
critical_section::with(|cs| {
let p = Peripherals::take_with_cs(cs);
#[cfg(dbgmcu)]
if config.enable_debug_during_sleep {
crate::pac::DBGMCU.cr().modify(|cr| {
#[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5, dbgmcu_wba))]
{
cr.set_dbg_stop(true);
cr.set_dbg_standby(true);
}
#[cfg(any(
dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
))]
{
cr.set_dbg_sleep(true);
cr.set_dbg_stop(true);
cr.set_dbg_standby(true);
}
#[cfg(dbgmcu_h7)]
{
cr.set_d1dbgcken(true);
cr.set_d3dbgcken(true);
cr.set_dbgsleep_d1(true);
cr.set_dbgstby_d1(true);
cr.set_dbgstop_d1(true);
}
});
}
#[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
peripherals::SYSCFG::enable();
#[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
peripherals::PWR::enable();
#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
peripherals::FLASH::enable();
unsafe {
#[cfg(feature = "_split-pins-enabled")]
crate::pac::SYSCFG.pmcr().modify(|pmcr| {
#[cfg(feature = "split-pa0")]
pmcr.set_pa0so(true);
#[cfg(feature = "split-pa1")]
pmcr.set_pa1so(true);
#[cfg(feature = "split-pc2")]
pmcr.set_pc2so(true);
#[cfg(feature = "split-pc3")]
pmcr.set_pc3so(true);
});
gpio::init();
dma::init(
#[cfg(bdma)]
config.bdma_interrupt_priority,
#[cfg(dma)]
config.dma_interrupt_priority,
#[cfg(gpdma)]
config.gpdma_interrupt_priority,
);
#[cfg(feature = "exti")]
exti::init();
rcc::init(config.rcc);
// must be after rcc init
#[cfg(feature = "_time-driver")]
time_driver::init();
#[cfg(feature = "low-power")]
while !crate::rcc::low_power_ready() {
crate::rcc::clock_refcount_sub();
#[cfg(dbgmcu)]
if config.enable_debug_during_sleep {
crate::pac::DBGMCU.cr().modify(|cr| {
#[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5, dbgmcu_wba))]
{
cr.set_dbg_stop(true);
cr.set_dbg_standby(true);
}
#[cfg(any(
dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
))]
{
cr.set_dbg_sleep(true);
cr.set_dbg_stop(true);
cr.set_dbg_standby(true);
}
#[cfg(dbgmcu_h7)]
{
cr.set_d1dbgcken(true);
cr.set_d3dbgcken(true);
cr.set_dbgsleep_d1(true);
cr.set_dbgstby_d1(true);
cr.set_dbgstop_d1(true);
}
});
}
}
p
#[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
peripherals::SYSCFG::enable_and_reset_with_cs(cs);
#[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
peripherals::PWR::enable_and_reset_with_cs(cs);
#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
peripherals::FLASH::enable_and_reset_with_cs(cs);
unsafe {
#[cfg(feature = "_split-pins-enabled")]
crate::pac::SYSCFG.pmcr().modify(|pmcr| {
#[cfg(feature = "split-pa0")]
pmcr.set_pa0so(true);
#[cfg(feature = "split-pa1")]
pmcr.set_pa1so(true);
#[cfg(feature = "split-pc2")]
pmcr.set_pc2so(true);
#[cfg(feature = "split-pc3")]
pmcr.set_pc3so(true);
});
gpio::init(cs);
dma::init(
cs,
#[cfg(bdma)]
config.bdma_interrupt_priority,
#[cfg(dma)]
config.dma_interrupt_priority,
#[cfg(gpdma)]
config.gpdma_interrupt_priority,
);
#[cfg(feature = "exti")]
exti::init(cs);
rcc::init(config.rcc);
// must be after rcc init
#[cfg(feature = "_time-driver")]
time_driver::init(cs);
#[cfg(feature = "low-power")]
while !crate::rcc::low_power_ready() {
crate::rcc::clock_refcount_sub(cs);
}
}
p
})
}

26
embassy-stm32/src/low_power.rs
View File

@ -1,5 +1,6 @@
use core::arch::asm;
use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
use cortex_m::peripheral::SCB;
use embassy_executor::*;
@ -67,10 +68,8 @@ impl Executor {
}
unsafe fn on_wakeup_irq(&mut self) {
trace!("low power: on wakeup irq");
self.time_driver.resume_time();
trace!("low power: resume time");
trace!("low power: resume");
}
pub(self) fn stop_with_rtc(&mut self, rtc: &'static Rtc) {
@ -82,21 +81,18 @@ impl Executor {
}
fn configure_pwr(&mut self) {
trace!("low power: configure_pwr");
self.scb.clear_sleepdeep();
compiler_fence(Ordering::SeqCst);
if !low_power_ready() {
trace!("low power: configure_pwr: low power not ready");
return;
trace!("low power: not ready to stop");
} else if self.time_driver.pause_time().is_err() {
trace!("low power: failed to pause time");
} else {
trace!("low power: stop");
self.scb.set_sleepdeep();
}
if self.time_driver.pause_time().is_err() {
trace!("low power: configure_pwr: time driver failed to pause");
return;
}
trace!("low power: enter stop...");
self.scb.set_sleepdeep();
}
/// Run the executor.

159
embassy-stm32/src/opamp.rs Normal file
View File

@ -0,0 +1,159 @@
#![macro_use]
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::Peripheral;
#[derive(Clone, Copy)]
pub enum OpAmpGain {
Mul1,
Mul2,
Mul4,
Mul8,
Mul16,
}
pub struct OpAmpOutput<'d, 'p, T: Instance, P: NonInvertingPin<T>> {
_inner: &'d OpAmp<'d, T>,
_input: &'p mut P,
}
pub struct OpAmp<'d, T: Instance> {
_inner: PeripheralRef<'d, T>,
}
impl<'d, T: Instance> OpAmp<'d, T> {
pub fn new(opamp: impl Peripheral<P = T> + 'd) -> Self {
Self::new_inner(opamp)
}
fn new_inner(opamp: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(opamp);
#[cfg(opamp_f3)]
T::regs().opampcsr().modify(|w| {
w.set_opampen(true);
});
#[cfg(opamp_g4)]
T::regs().opamp_csr().modify(|w| {
w.set_opaen(true);
});
Self { _inner: opamp }
}
pub fn buffer_for<'a, 'b, P>(&'a mut self, pin: &'b mut P, gain: OpAmpGain) -> OpAmpOutput<'a, 'b, T, P>
where
P: NonInvertingPin<T>,
{
let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00),
OpAmpGain::Mul4 => (0b10, 0b01),
OpAmpGain::Mul8 => (0b10, 0b10),
OpAmpGain::Mul16 => (0b10, 0b11),
};
#[cfg(opamp_f3)]
T::regs().opampcsr().modify(|w| {
w.set_vp_sel(pin.channel());
w.set_vm_sel(vm_sel);
w.set_pga_gain(pga_gain);
});
#[cfg(opamp_g4)]
T::regs().opamp_csr().modify(|w| {
use crate::pac::opamp::vals::*;
w.set_vp_sel(OpampCsrVpSel::from_bits(pin.channel()));
w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
});
OpAmpOutput {
_inner: self,
_input: pin,
}
}
}
pub trait Instance: sealed::Instance + 'static {}
pub(crate) mod sealed {
pub trait Instance {
fn regs() -> crate::pac::opamp::Opamp;
}
pub trait NonInvertingPin<T: Instance> {
fn channel(&self) -> u8;
}
pub trait InvertingPin<T: Instance> {
fn channel(&self) -> u8;
}
}
pub trait NonInvertingPin<T: Instance>: sealed::NonInvertingPin<T> {}
pub trait InvertingPin<T: Instance>: sealed::InvertingPin<T> {}
#[cfg(opamp_f3)]
macro_rules! impl_opamp_output {
($inst:ident, $adc:ident, $ch:expr) => {
impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::sealed::AdcPin<crate::peripherals::$adc>
for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
{
fn channel(&self) -> u8 {
$ch
}
}
impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::AdcPin<crate::peripherals::$adc>
for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
{
}
};
}
#[cfg(opamp_f3)]
foreach_peripheral!(
(opamp, OPAMP1) => {
impl_opamp_output!(OPAMP1, ADC1, 3);
};
(opamp, OPAMP2) => {
impl_opamp_output!(OPAMP2, ADC2, 3);
};
(opamp, OPAMP3) => {
impl_opamp_output!(OPAMP3, ADC3, 1);
};
(opamp, OPAMP4) => {
impl_opamp_output!(OPAMP4, ADC4, 3);
};
);
foreach_peripheral! {
(opamp, $inst:ident) => {
impl sealed::Instance for crate::peripherals::$inst {
fn regs() -> crate::pac::opamp::Opamp {
crate::pac::$inst
}
}
impl Instance for crate::peripherals::$inst {
}
};
}
#[allow(unused_macros)]
macro_rules! impl_opamp_pin {
($inst:ident, $pin:ident, $ch:expr) => {
impl crate::opamp::NonInvertingPin<peripherals::$inst> for crate::peripherals::$pin {}
impl crate::opamp::sealed::NonInvertingPin<peripherals::$inst> for crate::peripherals::$pin {
fn channel(&self) -> u8 {
$ch
}
}
};
}

16
embassy-stm32/src/qspi/enums.rs
View File

@ -38,6 +38,22 @@ impl Into<u8> for QspiWidth {
}
}
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum FlashSelection {
Flash1,
Flash2,
}
impl Into<bool> for FlashSelection {
fn into(self) -> bool {
match self {
FlashSelection::Flash1 => false,
FlashSelection::Flash2 => true,
}
}
}
#[derive(Copy, Clone)]
pub enum MemorySize {
_1KiB,

121
embassy-stm32/src/qspi/mod.rs
View File

@ -7,7 +7,7 @@ use enums::*;
use crate::dma::Transfer;
use crate::gpio::sealed::AFType;
use crate::gpio::AnyPin;
use crate::gpio::{AnyPin, Pull};
use crate::pac::quadspi::Quadspi as Regs;
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
@ -83,30 +83,30 @@ pub struct Qspi<'d, T: Instance, Dma> {
}
impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
pub fn new(
pub fn new_bk1(
peri: impl Peripheral<P = T> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
config: Config,
) -> Self {
into_ref!(peri, d0, d1, d2, d3, sck, nss);
sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None);
sck.set_speed(crate::gpio::Speed::VeryHigh);
nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up);
nss.set_speed(crate::gpio::Speed::VeryHigh);
d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None);
d0.set_speed(crate::gpio::Speed::VeryHigh);
d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None);
d1.set_speed(crate::gpio::Speed::VeryHigh);
d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None);
d2.set_speed(crate::gpio::Speed::VeryHigh);
d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None);
d3.set_speed(crate::gpio::Speed::VeryHigh);
Self::new_inner(
@ -119,6 +119,47 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
Some(nss.map_into()),
dma,
config,
FlashSelection::Flash2,
)
}
pub fn new_bk2(
peri: impl Peripheral<P = T> + 'd,
d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
config: Config,
) -> Self {
into_ref!(peri, d0, d1, d2, d3, sck, nss);
sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None);
sck.set_speed(crate::gpio::Speed::VeryHigh);
nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up);
nss.set_speed(crate::gpio::Speed::VeryHigh);
d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None);
d0.set_speed(crate::gpio::Speed::VeryHigh);
d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None);
d1.set_speed(crate::gpio::Speed::VeryHigh);
d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None);
d2.set_speed(crate::gpio::Speed::VeryHigh);
d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None);
d3.set_speed(crate::gpio::Speed::VeryHigh);
Self::new_inner(
peri,
Some(d0.map_into()),
Some(d1.map_into()),
Some(d2.map_into()),
Some(d3.map_into()),
Some(sck.map_into()),
Some(nss.map_into()),
dma,
config,
FlashSelection::Flash2,
)
}
@ -132,22 +173,39 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
nss: Option<PeripheralRef<'d, AnyPin>>,
dma: impl Peripheral<P = Dma> + 'd,
config: Config,
fsel: FlashSelection,
) -> Self {
into_ref!(peri, dma);
T::enable();
T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into()));
T::enable_and_reset();
while T::REGS.sr().read().busy() {}
T::REGS.cr().write(|w| {
w.set_prescaler(config.prescaler);
#[cfg(stm32h7)]
{
use stm32_metapac::quadspi::regs::Cr;
// Apply precautionary steps according to the errata...
T::REGS.cr().write_value(Cr(0));
while T::REGS.sr().read().busy() {}
T::REGS.cr().write_value(Cr(0xFF000001));
T::REGS.ccr().write(|w| w.set_frcm(true));
T::REGS.ccr().write(|w| w.set_frcm(true));
T::REGS.cr().write_value(Cr(0));
while T::REGS.sr().read().busy() {}
}
T::REGS.cr().modify(|w| {
w.set_en(true);
//w.set_tcen(false);
w.set_sshift(false);
w.set_fthres(config.fifo_threshold.into());
w.set_prescaler(config.prescaler);
w.set_fsel(fsel.into());
});
T::REGS.dcr().write(|w| {
T::REGS.dcr().modify(|w| {
w.set_fsize(config.memory_size.into());
w.set_csht(config.cs_high_time.into());
w.set_ckmode(false);
w.set_ckmode(true);
});
Self {
@ -164,6 +222,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
}
pub fn command(&mut self, transaction: TransferConfig) {
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(false));
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
@ -172,6 +231,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
}
pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(false));
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
@ -195,7 +255,10 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
}
pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(false));
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
if let Some(len) = transaction.data_len {
@ -238,6 +301,8 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
)
};
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer.blocking_wait();
@ -264,6 +329,8 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
)
};
// STM32H7 does not have dmaen
#[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer.blocking_wait();
@ -313,11 +380,17 @@ pub(crate) mod sealed {
pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
pin_trait!(SckPin, Instance);
pin_trait!(D0Pin, Instance);
pin_trait!(D1Pin, Instance);
pin_trait!(D2Pin, Instance);
pin_trait!(D3Pin, Instance);
pin_trait!(NSSPin, Instance);
pin_trait!(BK1D0Pin, Instance);
pin_trait!(BK1D1Pin, Instance);
pin_trait!(BK1D2Pin, Instance);
pin_trait!(BK1D3Pin, Instance);
pin_trait!(BK1NSSPin, Instance);
pin_trait!(BK2D0Pin, Instance);
pin_trait!(BK2D1Pin, Instance);
pin_trait!(BK2D2Pin, Instance);
pin_trait!(BK2D3Pin, Instance);
pin_trait!(BK2NSSPin, Instance);
dma_trait!(QuadDma, Instance);

299
embassy-stm32/src/rcc/bd.rs
View File

@ -1,102 +1,161 @@
use core::sync::atomic::{compiler_fence, Ordering};
use crate::pac::common::{Reg, RW};
pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
use crate::time::Hertz;
#[cfg(any(stm32f0, stm32f1, stm32f3))]
pub const LSI_FREQ: Hertz = Hertz(40_000);
#[cfg(not(any(stm32f0, stm32f1, stm32f3)))]
pub const LSI_FREQ: Hertz = Hertz(32_000);
#[allow(dead_code)]
#[derive(Clone, Copy)]
pub enum LseMode {
Oscillator(LseDrive),
Bypass,
}
pub struct LseConfig {
pub frequency: Hertz,
pub mode: LseMode,
}
#[allow(dead_code)]
#[derive(Default, Clone, Copy)]
pub enum LseDrive {
#[cfg(any(rtc_v2f7, rtc_v2l4))]
Low = 0,
MediumLow = 0x01,
#[default]
MediumHigh = 0x02,
#[cfg(any(rtc_v2f7, rtc_v2l4))]
High = 0x03,
}
#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
// All families but these have the LSEDRV register
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
fn from(value: LseDrive) -> Self {
use crate::pac::rcc::vals::Lsedrv;
match value {
#[cfg(any(rtc_v2f7, rtc_v2l4))]
LseDrive::Low => Lsedrv::LOW,
LseDrive::MediumLow => Lsedrv::MEDIUMLOW,
LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH,
#[cfg(any(rtc_v2f7, rtc_v2l4))]
LseDrive::High => Lsedrv::HIGH,
}
}
}
pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
#[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
#[allow(dead_code)]
type Bdcr = crate::pac::rcc::regs::Bdcr;
#[cfg(any(rtc_v2l0, rtc_v2l1))]
#[allow(dead_code)]
type Bdcr = crate::pac::rcc::regs::Csr;
#[cfg(any(stm32c0))]
type Bdcr = crate::pac::rcc::regs::Csr1;
#[allow(dead_code)]
pub struct BackupDomain {}
#[cfg(any(stm32c0))]
fn unlock() {}
impl BackupDomain {
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
rtc_v3u5
))]
#[allow(dead_code, unused_variables)]
fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R {
#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1, rtc_v2l0))]
let cr = crate::pac::PWR.cr();
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
let cr = crate::pac::PWR.cr1();
#[cfg(not(any(stm32c0)))]
fn unlock() {
#[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
let cr = crate::pac::PWR.cr();
#[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
let cr = crate::pac::PWR.cr1();
#[cfg(any(stm32u5, stm32h5, stm32wba))]
let cr = crate::pac::PWR.dbpcr();
// TODO: Missing from PAC for l0 and f0?
#[cfg(not(any(rtc_v2f0, rtc_v3u5)))]
{
cr.modify(|w| w.set_dbp(true));
while !cr.read().dbp() {}
cr.modify(|w| w.set_dbp(true));
while !cr.read().dbp() {}
}
fn bdcr() -> Reg<Bdcr, RW> {
#[cfg(any(rtc_v2l0, rtc_v2l1))]
return crate::pac::RCC.csr();
#[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
return crate::pac::RCC.bdcr();
#[cfg(any(stm32c0))]
return crate::pac::RCC.csr1();
}
pub struct LsConfig {
pub rtc: RtcClockSource,
pub lsi: bool,
pub lse: Option<LseConfig>,
}
impl LsConfig {
pub const fn default_lse() -> Self {
Self {
rtc: RtcClockSource::LSE,
lse: Some(LseConfig {
frequency: Hertz(32_768),
mode: LseMode::Oscillator(LseDrive::MediumHigh),
}),
lsi: false,
}
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let cr = crate::pac::RCC.csr();
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr();
cr.modify(|w| f(w))
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
rtc_v3u5
))]
#[allow(dead_code)]
fn read() -> Bdcr {
#[cfg(any(rtc_v2l0, rtc_v2l1))]
let r = crate::pac::RCC.csr().read();
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let r = crate::pac::RCC.bdcr().read();
r
pub const fn default_lsi() -> Self {
Self {
rtc: RtcClockSource::LSI,
lsi: true,
lse: None,
}
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
rtc_v3u5
))]
#[allow(dead_code, unused_variables)]
pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) {
if lsi {
#[cfg(rtc_v3u5)]
pub const fn off() -> Self {
Self {
rtc: RtcClockSource::DISABLE,
lsi: false,
lse: None,
}
}
}
impl Default for LsConfig {
fn default() -> Self {
// on L5, just the fact that LSI is enabled makes things crash.
// TODO: investigate.
#[cfg(not(stm32l5))]
return Self::default_lsi();
#[cfg(stm32l5)]
return Self::off();
}
}
impl LsConfig {
pub(crate) fn init(&self) -> Option<Hertz> {
let rtc_clk = match self.rtc {
RtcClockSource::LSI => {
assert!(self.lsi);
Some(LSI_FREQ)
}
RtcClockSource::LSE => Some(self.lse.as_ref().unwrap().frequency),
RtcClockSource::DISABLE => None,
_ => todo!(),
};
let (lse_en, lse_byp, lse_drv) = match &self.lse {
Some(c) => match c.mode {
LseMode::Oscillator(lse_drv) => (true, false, Some(lse_drv)),
LseMode::Bypass => (true, true, None),
},
None => (false, false, None),
};
_ = lse_drv; // not all chips have it.
// Disable backup domain write protection
unlock();
if self.lsi {
#[cfg(any(stm32u5, stm32h5, stm32wba))]
let csr = crate::pac::RCC.bdcr();
#[cfg(not(rtc_v3u5))]
#[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
let csr = crate::pac::RCC.csr();
// Disable backup domain write protection
Self::modify(|_| {});
#[cfg(any(stm32c0))]
let csr = crate::pac::RCC.csr2();
#[cfg(not(any(rcc_wb, rcc_wba)))]
csr.modify(|w| w.set_lsion(true));
@ -111,66 +170,76 @@ impl BackupDomain {
while !csr.read().lsi1rdy() {}
}
if let Some(lse_drive) = lse {
Self::modify(|w| {
#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
w.set_lsedrv(lse_drive.into());
// backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
// once set, changing it requires a backup domain reset.
// first check if the configuration matches what we want.
// check if it's already enabled and in the source we want.
let reg = bdcr().read();
let mut ok = true;
ok &= reg.rtcsel() == self.rtc;
#[cfg(not(rcc_wba))]
{
ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
}
ok &= reg.lseon() == lse_en;
ok &= reg.lsebyp() == lse_byp;
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
if let Some(lse_drv) = lse_drv {
ok &= reg.lsedrv() == lse_drv.into();
}
// if configuration is OK, we're done.
if ok {
trace!("BDCR ok: {:08x}", bdcr().read().0);
return rtc_clk;
}
// If not OK, reset backup domain and configure it.
#[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32c0)))]
{
bdcr().modify(|w| w.set_bdrst(true));
bdcr().modify(|w| w.set_bdrst(false));
}
#[cfg(any(stm32h5))]
{
bdcr().modify(|w| w.set_vswrst(true));
bdcr().modify(|w| w.set_vswrst(false));
}
#[cfg(any(stm32c0))]
{
bdcr().modify(|w| w.set_rtcrst(true));
bdcr().modify(|w| w.set_rtcrst(false));
}
if lse_en {
bdcr().modify(|w| {
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
if let Some(lse_drv) = lse_drv {
w.set_lsedrv(lse_drv.into());
}
w.set_lsebyp(lse_byp);
w.set_lseon(true);
});
while !Self::read().lserdy() {}
while !bdcr().read().lserdy() {}
}
match clock_source {
RtcClockSource::LSI => assert!(lsi),
RtcClockSource::LSE => assert!(&lse.is_some()),
_ => {}
};
if clock_source == RtcClockSource::NOCLOCK {
// disable it
Self::modify(|w| {
#[cfg(not(rcc_wba))]
w.set_rtcen(false);
w.set_rtcsel(clock_source);
});
} else {
// check if it's already enabled and in the source we want.
let reg = Self::read();
let ok = reg.rtcsel() == clock_source;
#[cfg(not(rcc_wba))]
let ok = ok & reg.rtcen();
// if not, configure it.
if !ok {
if self.rtc != RtcClockSource::DISABLE {
bdcr().modify(|w| {
#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
#[cfg(not(any(rcc_l0, rcc_l1)))]
Self::modify(|w| w.set_bdrst(true));
Self::modify(|w| {
// Reset
#[cfg(not(any(rcc_l0, rcc_l1)))]
w.set_bdrst(false);
#[cfg(not(rcc_wba))]
w.set_rtcen(true);
w.set_rtcsel(clock_source);
// Restore bcdr
#[cfg(any(rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
w.set_lscosel(reg.lscosel());
#[cfg(any(rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
w.set_lscoen(reg.lscoen());
w.set_lseon(reg.lseon());
#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
w.set_lsedrv(reg.lsedrv());
w.set_lsebyp(reg.lsebyp());
});
}
#[cfg(not(rcc_wba))]
w.set_rtcen(true);
w.set_rtcsel(self.rtc);
});
}
trace!("BDCR configured: {:08x}", bdcr().read().0);
compiler_fence(Ordering::SeqCst);
rtc_clk
}
}

56
embassy-stm32/src/rcc/bus.rs
View File

@ -1,56 +0,0 @@
use core::ops::Div;
#[allow(unused_imports)]
use crate::pac::rcc;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
use crate::time::Hertz;
impl Div<AHBPrescaler> for Hertz {
type Output = Hertz;
fn div(self, rhs: AHBPrescaler) -> Self::Output {
let divisor = match rhs {
AHBPrescaler::DIV1 => 1,
AHBPrescaler::DIV2 => 2,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV3 => 3,
AHBPrescaler::DIV4 => 4,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV5 => 5,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV6 => 6,
AHBPrescaler::DIV8 => 8,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV10 => 10,
AHBPrescaler::DIV16 => 16,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV32 => 32,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV64 => 64,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV128 => 128,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV256 => 256,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV512 => 512,
_ => unreachable!(),
};
Hertz(self.0 / divisor)
}
}
impl Div<APBPrescaler> for Hertz {
type Output = Hertz;
fn div(self, rhs: APBPrescaler) -> Self::Output {
let divisor = match rhs {
APBPrescaler::DIV1 => 1,
APBPrescaler::DIV2 => 2,
APBPrescaler::DIV4 => 4,
APBPrescaler::DIV8 => 8,
APBPrescaler::DIV16 => 16,
_ => unreachable!(),
};
Hertz(self.0 / divisor)
}
}

82
embassy-stm32/src/rcc/c0.rs
View File

@ -1,6 +1,6 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{Hsidiv, Ppre, Sw};
use crate::pac::rcc::vals::Sw;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -8,9 +8,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(48_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
@ -19,47 +16,22 @@ pub enum ClockSrc {
LSI,
}
#[derive(Clone, Copy)]
pub enum HSIPrescaler {
NotDivided,
Div2,
Div4,
Div8,
Div16,
Div32,
Div64,
Div128,
}
impl Into<Hsidiv> for HSIPrescaler {
fn into(self) -> Hsidiv {
match self {
HSIPrescaler::NotDivided => Hsidiv::DIV1,
HSIPrescaler::Div2 => Hsidiv::DIV2,
HSIPrescaler::Div4 => Hsidiv::DIV4,
HSIPrescaler::Div8 => Hsidiv::DIV8,
HSIPrescaler::Div16 => Hsidiv::DIV16,
HSIPrescaler::Div32 => Hsidiv::DIV32,
HSIPrescaler::Div64 => Hsidiv::DIV64,
HSIPrescaler::Div128 => Hsidiv::DIV128,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb_pre: APBPrescaler,
pub ls: super::LsConfig,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::HSI(HSIPrescaler::NotDivided),
mux: ClockSrc::HSI(HSIPrescaler::DIV1),
ahb_pre: AHBPrescaler::DIV1,
apb_pre: APBPrescaler::DIV1,
ls: Default::default(),
}
}
}
@ -68,33 +40,34 @@ pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw) = match config.mux {
ClockSrc::HSI(div) => {
// Enable HSI
let div: Hsidiv = div.into();
RCC.cr().write(|w| {
w.set_hsidiv(div);
w.set_hsion(true)
});
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
(HSI_FREQ / div, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
(freq, Sw::HSE)
}
ClockSrc::LSI => {
// Enable LSI
RCC.csr2().write(|w| w.set_lsion(true));
while !RCC.csr2().read().lsirdy() {}
(LSI_FREQ.0, Sw::LSI)
(super::LSI_FREQ, Sw::LSI)
}
};
let rtc = config.ls.init();
// Determine the flash latency implied by the target clock speed
// RM0454 § 3.3.4:
let target_flash_latency = if sys_clk <= 24_000_000 {
let target_flash_latency = if sys_clk <= Hertz(24_000_000) {
Latency::WS0
} else {
Latency::WS1
@ -129,7 +102,7 @@ pub(crate) unsafe fn init(config: Config) {
}
// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
let (sw, hpre, ppre) = (sw.into(), config.ahb_pre.into(), config.apb_pre.into());
let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(hpre);
@ -150,34 +123,23 @@ pub(crate) unsafe fn init(config: Config) {
FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
}
let ahb_div = match config.ahb_pre {
AHBPrescaler::DIV1 => 1,
AHBPrescaler::DIV2 => 2,
AHBPrescaler::DIV4 => 4,
AHBPrescaler::DIV8 => 8,
AHBPrescaler::DIV16 => 16,
AHBPrescaler::DIV64 => 64,
AHBPrescaler::DIV128 => 128,
AHBPrescaler::DIV256 => 256,
AHBPrescaler::DIV512 => 512,
_ => unreachable!(),
};
let ahb_freq = sys_clk / ahb_div;
let ahb_freq = sys_clk / config.ahb_pre;
let (apb_freq, apb_tim_freq) = match config.apb_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
apb1: Hertz(apb_freq),
apb1_tim: Hertz(apb_tim_freq),
hsi: None,
lse: None,
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
rtc,
});
}

22
embassy-stm32/src/rcc/f0.rs
View File

@ -8,9 +8,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(40_000);
/// Configuration of the clocks
///
/// hse takes precedence over hsi48 if both are enabled
@ -27,6 +24,8 @@ pub struct Config {
pub sys_ck: Option<Hertz>,
pub hclk: Option<Hertz>,
pub pclk: Option<Hertz>,
pub ls: super::LsConfig,
}
pub(crate) unsafe fn init(config: Config) {
@ -128,7 +127,7 @@ pub(crate) unsafe fn init(config: Config) {
}
if config.usb_pll {
RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLLCLK));
RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
}
// TODO: Option to use CRS (Clock Recovery)
@ -141,7 +140,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cfgr().modify(|w| {
w.set_ppre(Ppre::from_bits(ppre_bits));
w.set_hpre(Hpre::from_bits(hpre_bits));
w.set_sw(Sw::PLL)
w.set_sw(Sw::PLL1_P)
});
} else {
RCC.cfgr().modify(|w| {
@ -159,12 +158,15 @@ pub(crate) unsafe fn init(config: Config) {
})
}
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(real_sysclk),
apb1: Hertz(pclk),
apb2: Hertz(pclk),
apb1_tim: Hertz(pclk * timer_mul),
apb2_tim: Hertz(pclk * timer_mul),
ahb1: Hertz(hclk),
pclk1: Hertz(pclk),
pclk2: Hertz(pclk),
pclk1_tim: Hertz(pclk * timer_mul),
pclk2_tim: Hertz(pclk * timer_mul),
hclk1: Hertz(hclk),
rtc,
});
}

30
embassy-stm32/src/rcc/f1.rs
View File

@ -9,9 +9,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(40_000);
/// Configuration of the clocks
///
#[non_exhaustive]
@ -25,6 +22,8 @@ pub struct Config {
pub pclk2: Option<Hertz>,
pub adcclk: Option<Hertz>,
pub pllxtpre: bool,
pub ls: super::LsConfig,
}
pub(crate) unsafe fn init(config: Config) {
@ -103,7 +102,6 @@ pub(crate) unsafe fn init(config: Config) {
assert!(pclk2 <= 72_000_000);
// Only needed for stm32f103?
FLASH.acr().write(|w| {
w.set_latency(if real_sysclk <= 24_000_000 {
Latency::WS0
@ -112,6 +110,8 @@ pub(crate) unsafe fn init(config: Config) {
} else {
Latency::WS2
});
// the prefetch buffer is enabled by default, let's keep it enabled
w.set_prftbe(true);
});
// the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
@ -169,7 +169,14 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(not(rcc_f100))]
w.set_usbpre(Usbpre::from_bits(usbpre as u8));
w.set_sw(if pllmul_bits.is_some() {
Sw::PLL
#[cfg(not(rcc_f1cl))]
{
Sw::PLL1_P
}
#[cfg(rcc_f1cl)]
{
Sw::PLL
}
} else if config.hse.is_some() {
Sw::HSE
} else {
@ -177,13 +184,16 @@ pub(crate) unsafe fn init(config: Config) {
});
});
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(real_sysclk),
apb1: Hertz(pclk1),
apb2: Hertz(pclk2),
apb1_tim: Hertz(pclk1 * timer_mul1),
apb2_tim: Hertz(pclk2 * timer_mul2),
ahb1: Hertz(hclk),
pclk1: Hertz(pclk1),
pclk2: Hertz(pclk2),
pclk1_tim: Hertz(pclk1 * timer_mul1),
pclk2_tim: Hertz(pclk2 * timer_mul2),
hclk1: Hertz(hclk),
adc: Some(Hertz(adcclk)),
rtc,
});
}

205
embassy-stm32/src/rcc/f2.rs
View File

@ -1,21 +1,16 @@
use core::convert::TryFrom;
use core::ops::{Div, Mul};
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{Pllp, Pllsrc, Sw};
use crate::pac::rcc::vals::Sw;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Pllm as PLLPreDiv, Plln as PLLMul, Pllp as PLLPDiv, Pllq as PLLQDiv, Pllsrc as PLLSrc,
Ppre as APBPrescaler,
};
use crate::pac::{FLASH, RCC};
use crate::rcc::bd::BackupDomain;
use crate::rcc::{set_freqs, Clocks};
use crate::rtc::RtcClockSource;
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
#[derive(Clone, Copy)]
pub struct HSEConfig {
pub frequency: Hertz,
@ -43,17 +38,17 @@ pub enum HSESrc {
pub struct PLLConfig {
pub pre_div: PLLPreDiv,
pub mul: PLLMul,
pub main_div: PLLMainDiv,
pub pll48_div: PLL48Div,
pub p_div: PLLPDiv,
pub q_div: PLLQDiv,
}
impl Default for PLLConfig {
fn default() -> Self {
PLLConfig {
pre_div: PLLPreDiv(16),
mul: PLLMul(192),
main_div: PLLMainDiv::Div2,
pll48_div: PLL48Div(4),
pre_div: PLLPreDiv::DIV16,
mul: PLLMul::MUL192,
p_div: PLLPDiv::DIV2,
q_div: PLLQDiv::DIV4,
}
}
}
@ -61,9 +56,9 @@ impl Default for PLLConfig {
impl PLLConfig {
pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
let in_freq = src_freq / self.pre_div;
let vco_freq = Hertz((src_freq.0 as u64 * self.mul.0 as u64 / self.pre_div.0 as u64) as u32);
let main_freq = vco_freq / self.main_div;
let pll48_freq = vco_freq / self.pll48_div;
let vco_freq = src_freq / self.pre_div * self.mul;
let main_freq = vco_freq / self.p_div;
let pll48_freq = vco_freq / self.q_div;
PLLClocks {
in_freq,
vco_freq,
@ -72,129 +67,6 @@ impl PLLConfig {
}
}
}
/// Clock source for both main PLL and PLLI2S
#[derive(Clone, Copy, PartialEq)]
pub enum PLLSrc {
HSE,
HSI,
}
impl Into<Pllsrc> for PLLSrc {
fn into(self) -> Pllsrc {
match self {
PLLSrc::HSE => Pllsrc::HSE,
PLLSrc::HSI => Pllsrc::HSI,
}
}
}
/// Division factor for both main PLL and PLLI2S
#[derive(Clone, Copy, PartialEq)]
#[repr(transparent)]
pub struct PLLPreDiv(u8);
impl TryFrom<u8> for PLLPreDiv {
type Error = &'static str;
fn try_from(value: u8) -> Result<Self, Self::Error> {
match value {
2..=63 => Ok(PLLPreDiv(value)),
_ => Err("PLLPreDiv must be within range 2..=63"),
}
}
}
impl Div<PLLPreDiv> for Hertz {
type Output = Hertz;
fn div(self, rhs: PLLPreDiv) -> Self::Output {
Hertz(self.0 / u32::from(rhs.0))
}
}
/// Multiplication factor for main PLL
#[derive(Clone, Copy, PartialEq)]
#[repr(transparent)]
pub struct PLLMul(u16);
impl Mul<PLLMul> for Hertz {
type Output = Hertz;
fn mul(self, rhs: PLLMul) -> Self::Output {
Hertz(self.0 * u32::from(rhs.0))
}
}
impl TryFrom<u16> for PLLMul {
type Error = &'static str;
fn try_from(value: u16) -> Result<Self, Self::Error> {
match value {
192..=432 => Ok(PLLMul(value)),
_ => Err("PLLMul must be within range 192..=432"),
}
}
}
/// PLL division factor for the main system clock
#[derive(Clone, Copy, PartialEq)]
pub enum PLLMainDiv {
Div2,
Div4,
Div6,
Div8,
}
impl Into<Pllp> for PLLMainDiv {
fn into(self) -> Pllp {
match self {
PLLMainDiv::Div2 => Pllp::DIV2,
PLLMainDiv::Div4 => Pllp::DIV4,
PLLMainDiv::Div6 => Pllp::DIV6,
PLLMainDiv::Div8 => Pllp::DIV8,
}
}
}
impl Div<PLLMainDiv> for Hertz {
type Output = Hertz;
fn div(self, rhs: PLLMainDiv) -> Self::Output {
let divisor = match rhs {
PLLMainDiv::Div2 => 2,
PLLMainDiv::Div4 => 4,
PLLMainDiv::Div6 => 6,
PLLMainDiv::Div8 => 8,
};
Hertz(self.0 / divisor)
}
}
/// PLL division factor for USB OTG FS / SDIO / RNG
#[derive(Clone, Copy, PartialEq)]
#[repr(transparent)]
pub struct PLL48Div(u8);
impl Div<PLL48Div> for Hertz {
type Output = Hertz;
fn div(self, rhs: PLL48Div) -> Self::Output {
Hertz(self.0 / u32::from(rhs.0))
}
}
impl TryFrom<u8> for PLL48Div {
type Error = &'static str;
fn try_from(value: u8) -> Result<Self, Self::Error> {
match value {
2..=15 => Ok(PLL48Div(value)),
_ => Err("PLL48Div must be within range 2..=15"),
}
}
}
#[derive(Clone, Copy, PartialEq)]
pub struct PLLClocks {
pub in_freq: Hertz,
@ -303,13 +175,11 @@ pub struct Config {
pub pll_mux: PLLSrc,
pub pll: PLLConfig,
pub mux: ClockSrc,
pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
pub voltage: VoltageScale,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub ls: super::LsConfig,
}
impl Default for Config {
@ -322,12 +192,10 @@ impl Default for Config {
pll: PLLConfig::default(),
voltage: VoltageScale::Range3,
mux: ClockSrc::HSI,
rtc: None,
lsi: false,
lse: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
ls: Default::default(),
}
}
}
@ -367,11 +235,11 @@ pub(crate) unsafe fn init(config: Config) {
assert!(pll_clocks.pll48_freq <= Hertz(48_000_000));
RCC.pllcfgr().write(|w| {
w.set_pllsrc(config.pll_mux.into());
w.set_pllm(config.pll.pre_div.0);
w.set_plln(config.pll.mul.0);
w.set_pllp(config.pll.main_div.into());
w.set_pllq(config.pll.pll48_div.0);
w.set_pllsrc(config.pll_mux);
w.set_pllm(config.pll.pre_div);
w.set_plln(config.pll.mul);
w.set_pllp(config.pll.p_div);
w.set_pllq(config.pll.q_div);
});
let (sys_clk, sw) = match config.mux {
@ -388,7 +256,7 @@ pub(crate) unsafe fn init(config: Config) {
ClockSrc::PLL => {
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
(pll_clocks.main_freq, Sw::PLL)
(pll_clocks.main_freq, Sw::PLL1_P)
}
};
// RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL
@ -424,9 +292,9 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cfgr().modify(|w| {
w.set_sw(sw.into());
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
@ -435,21 +303,18 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().modify(|w| w.set_hsion(false));
}
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = config.ls.init();
set_freqs(Clocks {
sys: sys_clk,
ahb1: ahb_freq,
ahb2: ahb_freq,
ahb3: ahb_freq,
apb1: apb1_freq,
apb1_tim: apb1_tim_freq,
apb2: apb2_freq,
apb2_tim: apb2_tim_freq,
pll48: Some(pll_clocks.pll48_freq),
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk3: ahb_freq,
pclk1: apb1_freq,
pclk1_tim: apb1_tim_freq,
pclk2: apb2_freq,
pclk2_tim: apb2_tim_freq,
pll1_q: Some(pll_clocks.pll48_freq),
rtc,
});
}

202
embassy-stm32/src/rcc/f3.rs
View File

@ -1,7 +1,8 @@
#[cfg(rcc_f3)]
use crate::pac::adccommon::vals::Ckmode;
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{Adcpres, Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
pub use crate::pac::rcc::vals::Adcpres;
use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -9,28 +10,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(40_000);
impl From<AdcClockSource> for Adcpres {
fn from(value: AdcClockSource) -> Self {
match value {
AdcClockSource::PllDiv1 => Adcpres::DIV1,
AdcClockSource::PllDiv2 => Adcpres::DIV2,
AdcClockSource::PllDiv4 => Adcpres::DIV4,
AdcClockSource::PllDiv6 => Adcpres::DIV6,
AdcClockSource::PllDiv8 => Adcpres::DIV8,
AdcClockSource::PllDiv12 => Adcpres::DIV12,
AdcClockSource::PllDiv16 => Adcpres::DIV16,
AdcClockSource::PllDiv32 => Adcpres::DIV32,
AdcClockSource::PllDiv64 => Adcpres::DIV64,
AdcClockSource::PllDiv128 => Adcpres::DIV128,
AdcClockSource::PllDiv256 => Adcpres::DIV256,
_ => unreachable!(),
}
}
}
#[cfg(rcc_f3)]
impl From<AdcClockSource> for Ckmode {
fn from(value: AdcClockSource) -> Self {
@ -45,32 +24,13 @@ impl From<AdcClockSource> for Ckmode {
#[derive(Clone, Copy)]
pub enum AdcClockSource {
PllDiv1 = 1,
PllDiv2 = 2,
PllDiv4 = 4,
PllDiv6 = 6,
PllDiv8 = 8,
PllDiv12 = 12,
PllDiv16 = 16,
PllDiv32 = 32,
PllDiv64 = 64,
PllDiv128 = 128,
PllDiv256 = 256,
Pll(Adcpres),
BusDiv1,
BusDiv2,
BusDiv4,
}
impl AdcClockSource {
pub fn is_bus(&self) -> bool {
match self {
Self::BusDiv1 => true,
Self::BusDiv2 => true,
Self::BusDiv4 => true,
_ => false,
}
}
pub fn bus_div(&self) -> u32 {
match self {
Self::BusDiv1 => 1,
@ -124,6 +84,7 @@ pub struct Config {
pub adc34: Option<AdcClockSource>,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
pub ls: super::LsConfig,
}
// Information required to setup the PLL clock
@ -137,67 +98,67 @@ struct PllConfig {
/// Initialize and Set the clock frequencies
pub(crate) unsafe fn init(config: Config) {
// Calculate the real System clock, and PLL configuration if applicable
let (Hertz(sysclk), pll_config) = get_sysclk(&config);
assert!(sysclk <= 72_000_000);
let (sysclk, pll_config) = get_sysclk(&config);
assert!(sysclk.0 <= 72_000_000);
// Calculate real AHB clock
let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
let (hpre_bits, hpre_div) = match sysclk / hclk {
let hclk = config.hclk.map(|h| h).unwrap_or(sysclk);
let hpre = match sysclk.0 / hclk.0 {
0 => unreachable!(),
1 => (Hpre::DIV1, 1),
2 => (Hpre::DIV2, 2),
3..=5 => (Hpre::DIV4, 4),
6..=11 => (Hpre::DIV8, 8),
12..=39 => (Hpre::DIV16, 16),
40..=95 => (Hpre::DIV64, 64),
96..=191 => (Hpre::DIV128, 128),
192..=383 => (Hpre::DIV256, 256),
_ => (Hpre::DIV512, 512),
1 => Hpre::DIV1,
2 => Hpre::DIV2,
3..=5 => Hpre::DIV4,
6..=11 => Hpre::DIV8,
12..=39 => Hpre::DIV16,
40..=95 => Hpre::DIV64,
96..=191 => Hpre::DIV128,
192..=383 => Hpre::DIV256,
_ => Hpre::DIV512,
};
let hclk = sysclk / hpre_div;
assert!(hclk <= 72_000_000);
let hclk = sysclk / hpre;
assert!(hclk <= Hertz(72_000_000));
// Calculate real APB1 clock
let pclk1 = config.pclk1.map(|p| p.0).unwrap_or(hclk);
let (ppre1_bits, ppre1) = match hclk / pclk1 {
let pclk1 = config.pclk1.unwrap_or(hclk);
let ppre1 = match hclk / pclk1 {
0 => unreachable!(),
1 => (Ppre::DIV1, 1),
2 => (Ppre::DIV2, 2),
3..=5 => (Ppre::DIV4, 4),
6..=11 => (Ppre::DIV8, 8),
_ => (Ppre::DIV16, 16),
1 => Ppre::DIV1,
2 => Ppre::DIV2,
3..=5 => Ppre::DIV4,
6..=11 => Ppre::DIV8,
_ => Ppre::DIV16,
};
let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
let timer_mul1 = if ppre1 == Ppre::DIV1 { 1u32 } else { 2 };
let pclk1 = hclk / ppre1;
assert!(pclk1 <= 36_000_000);
assert!(pclk1 <= Hertz(36_000_000));
// Calculate real APB2 clock
let pclk2 = config.pclk2.map(|p| p.0).unwrap_or(hclk);
let (ppre2_bits, ppre2) = match hclk / pclk2 {
let pclk2 = config.pclk2.unwrap_or(hclk);
let ppre2 = match hclk / pclk2 {
0 => unreachable!(),
1 => (Ppre::DIV1, 1),
2 => (Ppre::DIV2, 2),
3..=5 => (Ppre::DIV4, 4),
6..=11 => (Ppre::DIV8, 8),
_ => (Ppre::DIV16, 16),
1 => Ppre::DIV1,
2 => Ppre::DIV2,
3..=5 => Ppre::DIV4,
6..=11 => Ppre::DIV8,
_ => Ppre::DIV16,
};
let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
let timer_mul2 = if ppre2 == Ppre::DIV1 { 1u32 } else { 2 };
let pclk2 = hclk / ppre2;
assert!(pclk2 <= 72_000_000);
assert!(pclk2 <= Hertz(72_000_000));
// Set latency based on HCLK frquency
// RM0316: "The prefetch buffer must be kept on when using a prescaler
// different from 1 on the AHB clock.", "Half-cycle access cannot be
// used when there is a prescaler different from 1 on the AHB clock"
FLASH.acr().modify(|w| {
w.set_latency(if hclk <= 24_000_000 {
w.set_latency(if hclk <= Hertz(24_000_000) {
Latency::WS0
} else if hclk <= 48_000_000 {
} else if hclk <= Hertz(48_000_000) {
Latency::WS1
} else {
Latency::WS2
});
if hpre_div != 1 {
if hpre != Hpre::DIV1 {
w.set_hlfcya(false);
w.set_prftbe(true);
}
@ -240,9 +201,9 @@ pub(crate) unsafe fn init(config: Config) {
// Set prescalers
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
RCC.cfgr().modify(|w| {
w.set_ppre2(ppre2_bits);
w.set_ppre1(ppre1_bits);
w.set_hpre(hpre_bits);
w.set_ppre2(ppre2);
w.set_ppre1(ppre1);
w.set_hpre(hpre);
});
// Wait for the new prescalers to kick in
@ -253,52 +214,50 @@ pub(crate) unsafe fn init(config: Config) {
// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
RCC.cfgr().modify(|w| {
w.set_sw(match (pll_config, config.hse) {
(Some(_), _) => Sw::PLL,
(Some(_), _) => Sw::PLL1_P,
(None, Some(_)) => Sw::HSE,
(None, None) => Sw::HSI,
})
});
#[cfg(rcc_f3)]
let adc = config.adc.map(|adc| {
if !adc.is_bus() {
let adc = config.adc.map(|adc| match adc {
AdcClockSource::Pll(adcpres) => {
RCC.cfgr2().modify(|w| {
// Make sure that we're using the PLL
pll_config.unwrap();
w.set_adc12pres(adc.into());
w.set_adc12pres(adcpres);
Hertz(sysclk / adc as u32)
})
} else {
crate::pac::ADC_COMMON.ccr().modify(|w| {
assert!(!(adc.bus_div() == 1 && hpre_bits != Hpre::DIV1));
w.set_ckmode(adc.into());
Hertz(sysclk / adc.bus_div() as u32)
sysclk / adcpres
})
}
_ => crate::pac::ADC_COMMON.ccr().modify(|w| {
assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
w.set_ckmode(adc.into());
sysclk / adc.bus_div()
}),
});
#[cfg(all(rcc_f3, adc3_common))]
let adc34 = config.adc.map(|adc| {
if !adc.is_bus() {
let adc34 = config.adc34.map(|adc| match adc {
AdcClockSource::Pll(adcpres) => {
RCC.cfgr2().modify(|w| {
// Make sure that we're using the PLL
pll_config.unwrap();
w.set_adc12pres(adc.into());
w.set_adc34pres(adcpres);
Hertz(sysclk / adc as u32)
})
} else {
crate::pac::ADC3_COMMON.ccr().modify(|w| {
assert!(!(adc.bus_div() == 1 && hpre_bits != Hpre::DIV1));
w.set_ckmode(adc.into());
Hertz(sysclk / adc.bus_div() as u32)
sysclk / adcpres
})
}
_ => crate::pac::ADC_COMMON.ccr().modify(|w| {
assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
w.set_ckmode(adc.into());
sysclk / adc.bus_div()
}),
});
#[cfg(stm32f334)]
@ -310,21 +269,23 @@ pub(crate) unsafe fn init(config: Config) {
// Make sure that we're using the PLL
pll_config.unwrap();
assert!((pclk2 == sysclk) || (pclk2 * 2 == sysclk));
assert!((pclk2 == sysclk) || (pclk2 * 2u32 == sysclk));
RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL));
RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL1_P));
Some(Hertz(sysclk * 2))
Some(sysclk * 2u32)
}
};
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sysclk),
apb1: Hertz(pclk1),
apb2: Hertz(pclk2),
apb1_tim: Hertz(pclk1 * timer_mul1),
apb2_tim: Hertz(pclk2 * timer_mul2),
ahb1: Hertz(hclk),
sys: sysclk,
pclk1: pclk1,
pclk2: pclk2,
pclk1_tim: pclk1 * timer_mul1,
pclk2_tim: pclk2 * timer_mul2,
hclk1: hclk,
#[cfg(rcc_f3)]
adc: adc,
#[cfg(all(rcc_f3, adc3_common))]
@ -333,6 +294,7 @@ pub(crate) unsafe fn init(config: Config) {
adc34: None,
#[cfg(stm32f334)]
hrtim: hrtim,
rtc,
});
}
@ -421,16 +383,16 @@ fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
#[inline]
#[allow(unused_variables)]
fn get_usb_pre(config: &Config, sysclk: u32, pclk1: u32, pll_config: &Option<PllConfig>) -> Usbpre {
fn get_usb_pre(config: &Config, sysclk: Hertz, pclk1: Hertz, pll_config: &Option<PllConfig>) -> Usbpre {
cfg_if::cfg_if! {
// Some chips do not have USB
if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
panic!("USB clock not supported by the chip");
} else {
let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= 10_000_000);
let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= Hertz(10_000_000));
match (usb_ok, sysclk) {
(true, 72_000_000) => Usbpre::DIV1_5,
(true, 48_000_000) => Usbpre::DIV1,
(true, Hertz(72_000_000)) => Usbpre::DIV1_5,
(true, Hertz(48_000_000)) => Usbpre::DIV1,
_ => panic!(
"USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
),

579
embassy-stm32/src/rcc/f4.rs
View File

@ -1,579 +0,0 @@
use core::marker::PhantomData;
use embassy_hal_internal::into_ref;
use stm32_metapac::rcc::vals::{Mco1, Mco2, Mcopre};
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// Clocks configuration
#[non_exhaustive]
#[derive(Default)]
pub struct Config {
pub hse: Option<Hertz>,
pub bypass_hse: bool,
pub hclk: Option<Hertz>,
pub sys_ck: Option<Hertz>,
pub pclk1: Option<Hertz>,
pub pclk2: Option<Hertz>,
#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
pub plli2s: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai: Option<Hertz>,
pub pll48: bool,
pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
}
#[cfg(stm32f410)]
fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
None
}
// Not currently implemented, but will be in the future
#[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
None
}
#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
fn calculate_sai_i2s_pll_values(vco_in: u32, max_div: u32, target: Option<u32>) -> Option<(u32, u32, u32)> {
let min_div = 2;
let target = match target {
Some(target) => target,
None => return None,
};
// We loop through the possible divider values to find the best configuration. Looping
// through all possible "N" values would result in more iterations.
let (n, outdiv, output, _error) = (min_div..=max_div)
.filter_map(|outdiv| {
let target_vco_out = match target.checked_mul(outdiv) {
Some(x) => x,
None => return None,
};
let n = (target_vco_out + (vco_in >> 1)) / vco_in;
let vco_out = vco_in * n;
if !(100_000_000..=432_000_000).contains(&vco_out) {
return None;
}
let output = vco_out / outdiv;
let error = (output as i32 - target as i32).unsigned_abs();
Some((n, outdiv, output, error))
})
.min_by_key(|(_, _, _, error)| *error)?;
Some((n, outdiv, output))
}
#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 7, plli2s)?;
RCC.plli2scfgr().modify(|w| {
w.set_plli2sn(n as u16);
w.set_plli2sr(outdiv as u8);
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
w.set_plli2sq(outdiv as u8); //set sai divider same as i2s
});
Some(output)
}
#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
fn setup_sai_pll(_vco_in: u32, _pllsai: Option<u32>) -> Option<u32> {
None
}
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
fn setup_sai_pll(vco_in: u32, pllsai: Option<u32>) -> Option<u32> {
let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 15, pllsai)?;
RCC.pllsaicfgr().modify(|w| {
w.set_pllsain(n as u16);
w.set_pllsaiq(outdiv as u8);
});
Some(output)
}
fn setup_pll(
pllsrcclk: u32,
use_hse: bool,
pllsysclk: Option<u32>,
plli2s: Option<u32>,
pllsai: Option<u32>,
pll48clk: bool,
) -> PllResults {
use crate::pac::rcc::vals::{Pllp, Pllsrc};
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
return PllResults {
use_pll: false,
pllsysclk: None,
pll48clk: None,
plli2sclk: None,
pllsaiclk: None,
};
}
// Input divisor from PLL source clock, must result to frequency in
// the range from 1 to 2 MHz
let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
let pllm_max = pllsrcclk / 1_000_000;
// Sysclk output divisor must be one of 2, 4, 6 or 8
let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
// Find the lowest pllm value that minimize the difference between
// target frequency and the real vco_out frequency.
let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
let vco_in = pllsrcclk / pllm;
let plln = target_freq / vco_in;
target_freq - vco_in * plln
}));
let vco_in = pllsrcclk / pllm;
assert!((1_000_000..=2_000_000).contains(&vco_in));
// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
// and <= 432MHz, min 50, max 432
let plln = if pll48clk {
// try the different valid pllq according to the valid
// main scaller values, and take the best
let pllq = unwrap!((4..=9).min_by_key(|pllq| {
let plln = 48_000_000 * pllq / vco_in;
let pll48_diff = 48_000_000 - vco_in * plln / pllq;
let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
(pll48_diff, sysclk_diff)
}));
48_000_000 * pllq / vco_in
} else {
sysclk * sysclk_div / vco_in
};
let pllp = (sysclk_div / 2) - 1;
let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
let real_pll48clk = vco_in * plln / pllq;
RCC.pllcfgr().modify(|w| {
w.set_pllm(pllm as u8);
w.set_plln(plln as u16);
w.set_pllp(Pllp::from_bits(pllp as u8));
w.set_pllq(pllq as u8);
w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
w.set_pllr(0);
});
let real_pllsysclk = vco_in * plln / sysclk_div;
PllResults {
use_pll: true,
pllsysclk: Some(real_pllsysclk),
pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
plli2sclk: setup_i2s_pll(vco_in, plli2s),
pllsaiclk: setup_sai_pll(vco_in, pllsai),
}
}
pub enum McoClock {
DIV1,
DIV2,
DIV3,
DIV4,
DIV5,
}
impl McoClock {
fn into_raw(&self) -> Mcopre {
match self {
McoClock::DIV1 => Mcopre::DIV1,
McoClock::DIV2 => Mcopre::DIV2,
McoClock::DIV3 => Mcopre::DIV3,
McoClock::DIV4 => Mcopre::DIV4,
McoClock::DIV5 => Mcopre::DIV5,
}
}
}
#[derive(Copy, Clone)]
pub enum Mco1Source {
Hsi,
Lse,
Hse,
Pll,
}
impl Default for Mco1Source {
fn default() -> Self {
Self::Hsi
}
}
pub trait McoSource {
type Raw;
fn into_raw(&self) -> Self::Raw;
}
impl McoSource for Mco1Source {
type Raw = Mco1;
fn into_raw(&self) -> Self::Raw {
match self {
Mco1Source::Hsi => Mco1::HSI,
Mco1Source::Lse => Mco1::LSE,
Mco1Source::Hse => Mco1::HSE,
Mco1Source::Pll => Mco1::PLL,
}
}
}
#[derive(Copy, Clone)]
pub enum Mco2Source {
SysClk,
Plli2s,
Hse,
Pll,
}
impl Default for Mco2Source {
fn default() -> Self {
Self::SysClk
}
}
impl McoSource for Mco2Source {
type Raw = Mco2;
fn into_raw(&self) -> Self::Raw {
match self {
Mco2Source::SysClk => Mco2::SYSCLK,
Mco2Source::Plli2s => Mco2::PLLI2S,
Mco2Source::Hse => Mco2::HSE,
Mco2Source::Pll => Mco2::PLL,
}
}
}
pub(crate) mod sealed {
use stm32_metapac::rcc::vals::Mcopre;
pub trait McoInstance {
type Source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre);
}
}
pub trait McoInstance: sealed::McoInstance + 'static {}
pin_trait!(McoPin, McoInstance);
impl sealed::McoInstance for peripherals::MCO1 {
type Source = Mco1;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
RCC.cfgr().modify(|w| {
w.set_mco1(source);
w.set_mco1pre(prescaler);
});
match source {
Mco1::PLL => {
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
}
Mco1::HSI => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
_ => {}
}
}
}
impl McoInstance for peripherals::MCO1 {}
impl sealed::McoInstance for peripherals::MCO2 {
type Source = Mco2;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
RCC.cfgr().modify(|w| {
w.set_mco2(source);
w.set_mco2pre(prescaler);
});
match source {
Mco2::PLL => {
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
}
#[cfg(not(stm32f410))]
Mco2::PLLI2S => {
RCC.cr().modify(|w| w.set_plli2son(true));
while !RCC.cr().read().plli2srdy() {}
}
_ => {}
}
}
}
impl McoInstance for peripherals::MCO2 {}
pub struct Mco<'d, T: McoInstance> {
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: McoInstance> Mco<'d, T> {
pub fn new(
_peri: impl Peripheral<P = T> + 'd,
pin: impl Peripheral<P = impl McoPin<T>> + 'd,
source: impl McoSource<Raw = T::Source>,
prescaler: McoClock,
) -> Self {
into_ref!(pin);
critical_section::with(|_| unsafe {
T::apply_clock_settings(source.into_raw(), prescaler.into_raw());
pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
pin.set_speed(Speed::VeryHigh);
});
Self { phantom: PhantomData }
}
}
fn flash_setup(sysclk: u32) {
use crate::pac::flash::vals::Latency;
// Be conservative with voltage ranges
const FLASH_LATENCY_STEP: u32 = 30_000_000;
critical_section::with(|_| {
FLASH
.acr()
.modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
});
}
pub(crate) unsafe fn init(config: Config) {
let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let sysclk_on_pll = sysclk != pllsrcclk;
let plls = setup_pll(
pllsrcclk,
config.hse.is_some(),
if sysclk_on_pll { Some(sysclk) } else { None },
#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
config.plli2s.map(|i2s| i2s.0),
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
None,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
config.pllsai.map(|sai| sai.0),
#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
None,
config.pll48,
);
if config.pll48 {
let freq = unwrap!(plls.pll48clk);
assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
}
let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
// AHB prescaler
let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
0 => unreachable!(),
1 => (Hpre::DIV1, 1),
2 => (Hpre::DIV2, 2),
3..=5 => (Hpre::DIV4, 4),
6..=11 => (Hpre::DIV8, 8),
12..=39 => (Hpre::DIV16, 16),
40..=95 => (Hpre::DIV64, 64),
96..=191 => (Hpre::DIV128, 128),
192..=383 => (Hpre::DIV256, 256),
_ => (Hpre::DIV512, 512),
};
// Calculate real AHB clock
let hclk = sysclk / hpre_div;
let pclk1 = config
.pclk1
.map(|p| p.0)
.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
0 => unreachable!(),
1 => (0b000, 1),
2 => (0b100, 2),
3..=5 => (0b101, 4),
6..=11 => (0b110, 8),
_ => (0b111, 16),
};
let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
// Calculate real APB1 clock
let pclk1 = hclk / ppre1;
assert!(pclk1 <= max::PCLK1_MAX);
let pclk2 = config
.pclk2
.map(|p| p.0)
.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
0 => unreachable!(),
1 => (0b000, 1),
2 => (0b100, 2),
3..=5 => (0b101, 4),
6..=11 => (0b110, 8),
_ => (0b111, 16),
};
let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
// Calculate real APB2 clock
let pclk2 = hclk / ppre2;
assert!(pclk2 <= max::PCLK2_MAX);
flash_setup(sysclk);
if config.hse.is_some() {
RCC.cr().modify(|w| {
w.set_hsebyp(config.bypass_hse);
w.set_hseon(true);
});
while !RCC.cr().read().hserdy() {}
}
if plls.use_pll {
RCC.cr().modify(|w| w.set_pllon(true));
if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
PWR.cr1().modify(|w| w.set_oden(true));
while !PWR.csr1().read().odrdy() {}
PWR.cr1().modify(|w| w.set_odswen(true));
while !PWR.csr1().read().odswrdy() {}
}
while !RCC.cr().read().pllrdy() {}
}
#[cfg(not(stm32f410))]
if plls.plli2sclk.is_some() {
RCC.cr().modify(|w| w.set_plli2son(true));
while !RCC.cr().read().plli2srdy() {}
}
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
if plls.pllsaiclk.is_some() {
RCC.cr().modify(|w| w.set_pllsaion(true));
while !RCC.cr().read().pllsairdy() {}
}
RCC.cfgr().modify(|w| {
w.set_ppre2(Ppre::from_bits(ppre2_bits));
w.set_ppre1(Ppre::from_bits(ppre1_bits));
w.set_hpre(hpre_bits);
});
// Wait for the new prescalers to kick in
// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
cortex_m::asm::delay(16);
RCC.cfgr().modify(|w| {
w.set_sw(if sysclk_on_pll {
Sw::PLL
} else if config.hse.is_some() {
Sw::HSE
} else {
Sw::HSI
})
});
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ),
Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
_ => None,
};
set_freqs(Clocks {
sys: Hertz(sysclk),
apb1: Hertz(pclk1),
apb2: Hertz(pclk2),
apb1_tim: Hertz(pclk1 * timer_mul1),
apb2_tim: Hertz(pclk2 * timer_mul2),
ahb1: Hertz(hclk),
ahb2: Hertz(hclk),
ahb3: Hertz(hclk),
pll48: plls.pll48clk.map(Hertz),
#[cfg(not(stm32f410))]
plli2s: plls.plli2sclk.map(Hertz),
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pllsai: plls.pllsaiclk.map(Hertz),
rtc: rtc,
rtc_hse: None,
});
}
struct PllResults {
use_pll: bool,
pllsysclk: Option<u32>,
pll48clk: Option<u32>,
#[allow(dead_code)]
plli2sclk: Option<u32>,
#[allow(dead_code)]
pllsaiclk: Option<u32>,
}
mod max {
#[cfg(stm32f401)]
pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;
pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
pub(crate) const PLL_48_CLK: u32 = 48_000_000;
pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
}

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embassy-stm32/src/rcc/f4f7.rs Normal file
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@ -0,0 +1,385 @@
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
// TODO: on some F4s, add support for plli2s_src
//
// plli2s plli2s_m plli2s_src pllsai pllsai_m
// f401 y shared
// f410
// f411 y individual
// f412 y individual y
// f4[12]3 y individual y
// f446 y individual y individual
// f4[67]9 y shared y shared
// f4[23][79] y shared y shared
// f4[01][57] y shared
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
Oscillator,
/// external analog clock (low swing) (HSEBYP=1)
Bypass,
}
#[derive(Clone, Copy, Eq, PartialEq)]
pub struct Hse {
/// HSE frequency.
pub freq: Hertz,
/// HSE mode.
pub mode: HseMode,
}
#[derive(Clone, Copy)]
pub struct Pll {
/// PLL pre-divider (DIVM).
pub prediv: PllPreDiv,
/// PLL multiplication factor.
pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled.
pub divp: Option<Pllp>,
/// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<Pllq>,
/// PLL R division factor. If None, PLL R output is disabled.
pub divr: Option<Pllr>,
}
/// Configuration of the core clocks
#[non_exhaustive]
pub struct Config {
pub hsi: bool,
pub hse: Option<Hse>,
pub sys: Sysclk,
pub pll_src: PllSource,
pub pll: Option<Pll>,
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
pub plli2s: Option<Pll>,
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
pub pllsai: Option<Pll>,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub ls: super::LsConfig,
}
impl Default for Config {
fn default() -> Self {
Self {
hsi: true,
hse: None,
sys: Sysclk::HSI,
pll_src: PllSource::HSI,
pll: None,
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
plli2s: None,
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
pllsai: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
ls: Default::default(),
}
}
}
pub(crate) unsafe fn init(config: Config) {
// always enable overdrive for now. Make it configurable in the future.
#[cfg(not(any(
stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f405, stm32f407, stm32f415, stm32f417
)))]
{
use crate::pac::PWR;
PWR.cr1().modify(|w| w.set_oden(true));
while !PWR.csr1().read().odrdy() {}
PWR.cr1().modify(|w| w.set_odswen(true));
while !PWR.csr1().read().odswrdy() {}
}
// Configure HSI
let hsi = match config.hsi {
false => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
true => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
Some(HSI_FREQ)
}
};
// Configure HSE
let hse = match config.hse {
None => {
RCC.cr().modify(|w| w.set_hseon(false));
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
RCC.cr().modify(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
Some(hse.freq)
}
};
// Configure PLLs.
let pll_input = PllInput {
hse,
hsi,
source: config.pll_src,
};
let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
// Configure sysclk
let sys = match config.sys {
Sysclk::HSI => unwrap!(hsi),
Sysclk::HSE => unwrap!(hse),
Sysclk::PLL1_P => unwrap!(pll.p),
_ => unreachable!(),
};
let hclk = sys / config.ahb_pre;
let (pclk1, pclk1_tim) = calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = calc_pclk(hclk, config.apb2_pre);
assert!(max::SYSCLK.contains(&sys));
assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
assert!(max::PCLK2.contains(&pclk2));
let rtc = config.ls.init();
flash_setup(hclk);
RCC.cfgr().modify(|w| {
w.set_sw(config.sys);
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
while RCC.cfgr().read().sws() != config.sys {}
set_freqs(Clocks {
sys,
hclk1: hclk,
hclk2: hclk,
hclk3: hclk,
pclk1,
pclk2,
pclk1_tim,
pclk2_tim,
rtc,
pll1_q: pll.q,
#[cfg(all(rcc_f4, not(stm32f410)))]
plli2s1_q: _plli2s.q,
#[cfg(all(rcc_f4, not(stm32f410)))]
plli2s1_r: _plli2s.r,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pllsai1_q: _pllsai.q,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pllsai1_r: _pllsai.r,
});
}
struct PllInput {
source: PllSource,
hsi: Option<Hertz>,
hse: Option<Hertz>,
}
#[derive(Default)]
#[allow(unused)]
struct PllOutput {
p: Option<Hertz>,
q: Option<Hertz>,
r: Option<Hertz>,
}
#[derive(PartialEq, Eq, Clone, Copy)]
enum PllInstance {
Pll,
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
Plli2s,
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
Pllsai,
}
fn pll_enable(instance: PllInstance, enabled: bool) {
match instance {
PllInstance::Pll => {
RCC.cr().modify(|w| w.set_pllon(enabled));
while RCC.cr().read().pllrdy() != enabled {}
}
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
PllInstance::Plli2s => {
RCC.cr().modify(|w| w.set_plli2son(enabled));
while RCC.cr().read().plli2srdy() != enabled {}
}
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
PllInstance::Pllsai => {
RCC.cr().modify(|w| w.set_pllsaion(enabled));
while RCC.cr().read().pllsairdy() != enabled {}
}
}
}
fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
// Disable PLL
pll_enable(instance, false);
let Some(pll) = config else { return PllOutput::default() };
let pll_src = match input.source {
PllSource::HSE => input.hse,
PllSource::HSI => input.hsi,
};
let pll_src = pll_src.unwrap();
let in_freq = pll_src / pll.prediv;
assert!(max::PLL_IN.contains(&in_freq));
let vco_freq = in_freq * pll.mul;
assert!(max::PLL_VCO.contains(&vco_freq));
let p = pll.divp.map(|div| vco_freq / div);
let q = pll.divq.map(|div| vco_freq / div);
let r = pll.divr.map(|div| vco_freq / div);
macro_rules! write_fields {
($w:ident) => {
$w.set_plln(pll.mul);
if let Some(divp) = pll.divp {
$w.set_pllp(divp);
}
if let Some(divq) = pll.divq {
$w.set_pllq(divq);
}
if let Some(divr) = pll.divr {
$w.set_pllr(divr);
}
};
}
match instance {
PllInstance::Pll => RCC.pllcfgr().write(|w| {
w.set_pllm(pll.prediv);
w.set_pllsrc(input.source);
write_fields!(w);
}),
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
write_fields!(w);
}),
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
write_fields!(w);
}),
}
// Enable PLL
pll_enable(instance, true);
PllOutput { p, q, r }
}
fn flash_setup(clk: Hertz) {
use crate::pac::flash::vals::Latency;
// Be conservative with voltage ranges
const FLASH_LATENCY_STEP: u32 = 30_000_000;
let latency = (clk.0 - 1) / FLASH_LATENCY_STEP;
debug!("flash: latency={}", latency);
let latency = Latency::from_bits(latency as u8);
FLASH.acr().write(|w| {
w.set_latency(latency);
});
while FLASH.acr().read().latency() != latency {}
}
fn calc_pclk<D>(hclk: Hertz, ppre: D) -> (Hertz, Hertz)
where
Hertz: core::ops::Div<D, Output = Hertz>,
{
let pclk = hclk / ppre;
let pclk_tim = if hclk == pclk { pclk } else { pclk * 2u32 };
(pclk, pclk_tim)
}
#[cfg(stm32f7)]
mod max {
use core::ops::RangeInclusive;
use crate::time::Hertz;
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 4);
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 2);
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
}
#[cfg(stm32f4)]
mod max {
use core::ops::RangeInclusive;
use crate::time::Hertz;
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
#[cfg(stm32f401)]
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(84_000_000);
#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(168_000_000);
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(100_000_000);
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(180_000_000);
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(PCLK2.end().0 / 2);
#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0);
#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0 / 2);
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
}

323
embassy-stm32/src/rcc/f7.rs
View File

@ -1,323 +0,0 @@
use crate::pac::pwr::vals::Vos;
use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// Clocks configuration
#[non_exhaustive]
#[derive(Default)]
pub struct Config {
pub hse: Option<Hertz>,
pub bypass_hse: bool,
pub hclk: Option<Hertz>,
pub sys_ck: Option<Hertz>,
pub pclk1: Option<Hertz>,
pub pclk2: Option<Hertz>,
pub pll48: bool,
pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
}
fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
use crate::pac::rcc::vals::{Pllp, Pllsrc};
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
if pllsysclk.is_none() && !pll48clk {
RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
return PllResults {
use_pll: false,
pllsysclk: None,
pll48clk: None,
};
}
// Input divisor from PLL source clock, must result to frequency in
// the range from 1 to 2 MHz
let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
let pllm_max = pllsrcclk / 1_000_000;
// Sysclk output divisor must be one of 2, 4, 6 or 8
let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
// Find the lowest pllm value that minimize the difference between
// target frequency and the real vco_out frequency.
let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
let vco_in = pllsrcclk / pllm;
let plln = target_freq / vco_in;
target_freq - vco_in * plln
}));
let vco_in = pllsrcclk / pllm;
assert!((1_000_000..=2_000_000).contains(&vco_in));
// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
// and <= 432MHz, min 50, max 432
let plln = if pll48clk {
// try the different valid pllq according to the valid
// main scaller values, and take the best
let pllq = unwrap!((4..=9).min_by_key(|pllq| {
let plln = 48_000_000 * pllq / vco_in;
let pll48_diff = 48_000_000 - vco_in * plln / pllq;
let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
(pll48_diff, sysclk_diff)
}));
48_000_000 * pllq / vco_in
} else {
sysclk * sysclk_div / vco_in
};
let pllp = (sysclk_div / 2) - 1;
let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
let real_pll48clk = vco_in * plln / pllq;
RCC.pllcfgr().modify(|w| {
w.set_pllm(pllm as u8);
w.set_plln(plln as u16);
w.set_pllp(Pllp::from_bits(pllp as u8));
w.set_pllq(pllq as u8);
w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
});
let real_pllsysclk = vco_in * plln / sysclk_div;
PllResults {
use_pll: true,
pllsysclk: Some(real_pllsysclk),
pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
}
}
fn flash_setup(sysclk: u32) {
use crate::pac::flash::vals::Latency;
// Be conservative with voltage ranges
const FLASH_LATENCY_STEP: u32 = 30_000_000;
critical_section::with(|_| {
FLASH
.acr()
.modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
});
}
pub(crate) unsafe fn init(config: Config) {
if let Some(hse) = config.hse {
if config.bypass_hse {
assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
} else {
assert!((max::HSE_OSC_MIN..=max::HSE_OSC_MAX).contains(&hse.0));
}
}
let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let sysclk_on_pll = sysclk != pllsrcclk;
assert!((max::SYSCLK_MIN..=max::SYSCLK_MAX).contains(&sysclk));
let plls = setup_pll(
pllsrcclk,
config.hse.is_some(),
if sysclk_on_pll { Some(sysclk) } else { None },
config.pll48,
);
if config.pll48 {
let freq = unwrap!(plls.pll48clk);
assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
}
let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
// AHB prescaler
let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
0 => unreachable!(),
1 => (Hpre::DIV1, 1),
2 => (Hpre::DIV2, 2),
3..=5 => (Hpre::DIV4, 4),
6..=11 => (Hpre::DIV8, 8),
12..=39 => (Hpre::DIV16, 16),
40..=95 => (Hpre::DIV64, 64),
96..=191 => (Hpre::DIV128, 128),
192..=383 => (Hpre::DIV256, 256),
_ => (Hpre::DIV512, 512),
};
// Calculate real AHB clock
let hclk = sysclk / hpre_div;
assert!(hclk <= max::HCLK_MAX);
let pclk1 = config
.pclk1
.map(|p| p.0)
.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
0 => unreachable!(),
1 => (0b000, 1),
2 => (0b100, 2),
3..=5 => (0b101, 4),
6..=11 => (0b110, 8),
_ => (0b111, 16),
};
let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
// Calculate real APB1 clock
let pclk1 = hclk / ppre1;
assert!((max::PCLK1_MIN..=max::PCLK1_MAX).contains(&pclk1));
let pclk2 = config
.pclk2
.map(|p| p.0)
.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
0 => unreachable!(),
1 => (0b000, 1),
2 => (0b100, 2),
3..=5 => (0b101, 4),
6..=11 => (0b110, 8),
_ => (0b111, 16),
};
let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
// Calculate real APB2 clock
let pclk2 = hclk / ppre2;
assert!((max::PCLK2_MIN..=max::PCLK2_MAX).contains(&pclk2));
flash_setup(sysclk);
if config.hse.is_some() {
RCC.cr().modify(|w| {
w.set_hsebyp(config.bypass_hse);
w.set_hseon(true);
});
while !RCC.cr().read().hserdy() {}
}
if plls.use_pll {
RCC.cr().modify(|w| w.set_pllon(false));
// setup VOSScale
let vos_scale = if sysclk <= 144_000_000 {
3
} else if sysclk <= 168_000_000 {
2
} else {
1
};
PWR.cr1().modify(|w| {
w.set_vos(match vos_scale {
3 => Vos::SCALE3,
2 => Vos::SCALE2,
1 => Vos::SCALE1,
_ => panic!("Invalid VOS Scale."),
})
});
RCC.cr().modify(|w| w.set_pllon(true));
if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
PWR.cr1().modify(|w| w.set_oden(true));
while !PWR.csr1().read().odrdy() {}
PWR.cr1().modify(|w| w.set_odswen(true));
while !PWR.csr1().read().odswrdy() {}
}
while !RCC.cr().read().pllrdy() {}
}
RCC.cfgr().modify(|w| {
w.set_ppre2(Ppre::from_bits(ppre2_bits));
w.set_ppre1(Ppre::from_bits(ppre1_bits));
w.set_hpre(hpre_bits);
});
// Wait for the new prescalers to kick in
// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
cortex_m::asm::delay(16);
RCC.cfgr().modify(|w| {
w.set_sw(if sysclk_on_pll {
Sw::PLL
} else if config.hse.is_some() {
Sw::HSE
} else {
Sw::HSI
})
});
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ),
Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
_ => None,
};
set_freqs(Clocks {
sys: Hertz(sysclk),
apb1: Hertz(pclk1),
apb2: Hertz(pclk2),
apb1_tim: Hertz(pclk1 * timer_mul1),
apb2_tim: Hertz(pclk2 * timer_mul2),
ahb1: Hertz(hclk),
ahb2: Hertz(hclk),
ahb3: Hertz(hclk),
pll48: plls.pll48clk.map(Hertz),
rtc,
});
}
struct PllResults {
use_pll: bool,
pllsysclk: Option<u32>,
pll48clk: Option<u32>,
}
mod max {
pub(crate) const HSE_OSC_MIN: u32 = 4_000_000;
pub(crate) const HSE_OSC_MAX: u32 = 26_000_000;
pub(crate) const HSE_BYPASS_MIN: u32 = 1_000_000;
pub(crate) const HSE_BYPASS_MAX: u32 = 50_000_000;
pub(crate) const HCLK_MAX: u32 = 216_000_000;
pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 180_000_000;
pub(crate) const SYSCLK_MIN: u32 = 12_500_000;
pub(crate) const SYSCLK_MAX: u32 = 216_000_000;
pub(crate) const PCLK1_MIN: u32 = SYSCLK_MIN;
pub(crate) const PCLK1_MAX: u32 = SYSCLK_MAX / 4;
pub(crate) const PCLK2_MIN: u32 = SYSCLK_MIN;
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
// USB specification allows +-0.25%
pub(crate) const PLL_48_CLK: u32 = 48_000_000;
pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
}

211
embassy-stm32/src/rcc/g0.rs
View File

@ -1,6 +1,8 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{self, Hsidiv, Ppre, Sw};
use crate::pac::rcc::vals::{self, Sw};
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Hsidiv as HSI16Prescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -8,9 +10,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
@ -20,33 +19,6 @@ pub enum ClockSrc {
LSI,
}
#[derive(Clone, Copy)]
pub enum HSI16Prescaler {
NotDivided,
Div2,
Div4,
Div8,
Div16,
Div32,
Div64,
Div128,
}
impl Into<Hsidiv> for HSI16Prescaler {
fn into(self) -> Hsidiv {
match self {
HSI16Prescaler::NotDivided => Hsidiv::DIV1,
HSI16Prescaler::Div2 => Hsidiv::DIV2,
HSI16Prescaler::Div4 => Hsidiv::DIV4,
HSI16Prescaler::Div8 => Hsidiv::DIV8,
HSI16Prescaler::Div16 => Hsidiv::DIV16,
HSI16Prescaler::Div32 => Hsidiv::DIV32,
HSI16Prescaler::Div64 => Hsidiv::DIV64,
HSI16Prescaler::Div128 => Hsidiv::DIV128,
}
}
}
/// The PLL configuration.
///
/// * `VCOCLK = source / m * n`
@ -60,15 +32,15 @@ pub struct PllConfig {
/// The initial divisor of that clock signal
pub m: Pllm,
/// The PLL VCO multiplier, which must be in the range `8..=86`.
pub n: u8,
pub n: Plln,
/// The final divisor for `PLLRCLK` output which drives the system clock
pub r: Pllr,
/// The divisor for the `PLLQCLK` output, if desired
pub q: Option<Pllr>,
pub q: Option<Pllq>,
/// The divisor for the `PLLPCLK` output, if desired
pub p: Option<Pllr>,
pub p: Option<Pllp>,
}
impl Default for PllConfig {
@ -77,9 +49,9 @@ impl Default for PllConfig {
// HSI16 / 1 * 8 / 2 = 64 MHz
PllConfig {
source: PllSrc::HSI16,
m: Pllm::Div1,
n: 8,
r: Pllr::Div2,
m: Pllm::DIV1,
n: Plln::MUL8,
r: Pllr::DIV2,
q: None,
p: None,
}
@ -92,131 +64,51 @@ pub enum PllSrc {
HSE(Hertz),
}
#[derive(Clone, Copy)]
pub enum Pllm {
Div1,
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
}
impl From<Pllm> for u8 {
fn from(v: Pllm) -> Self {
match v {
Pllm::Div1 => 0b000,
Pllm::Div2 => 0b001,
Pllm::Div3 => 0b010,
Pllm::Div4 => 0b011,
Pllm::Div5 => 0b100,
Pllm::Div6 => 0b101,
Pllm::Div7 => 0b110,
Pllm::Div8 => 0b111,
}
}
}
impl From<Pllm> for u32 {
fn from(v: Pllm) -> Self {
match v {
Pllm::Div1 => 1,
Pllm::Div2 => 2,
Pllm::Div3 => 3,
Pllm::Div4 => 4,
Pllm::Div5 => 5,
Pllm::Div6 => 6,
Pllm::Div7 => 7,
Pllm::Div8 => 8,
}
}
}
#[derive(Clone, Copy)]
pub enum Pllr {
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
}
impl From<Pllr> for u8 {
fn from(v: Pllr) -> Self {
match v {
Pllr::Div2 => 0b000,
Pllr::Div3 => 0b001,
Pllr::Div4 => 0b010,
Pllr::Div5 => 0b011,
Pllr::Div6 => 0b101,
Pllr::Div7 => 0b110,
Pllr::Div8 => 0b111,
}
}
}
impl From<Pllr> for u32 {
fn from(v: Pllr) -> Self {
match v {
Pllr::Div2 => 2,
Pllr::Div3 => 3,
Pllr::Div4 => 4,
Pllr::Div5 => 5,
Pllr::Div6 => 6,
Pllr::Div7 => 7,
Pllr::Div8 => 8,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb_pre: APBPrescaler,
pub low_power_run: bool,
pub ls: super::LsConfig,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided),
mux: ClockSrc::HSI16(HSI16Prescaler::DIV1),
ahb_pre: AHBPrescaler::DIV1,
apb_pre: APBPrescaler::DIV1,
low_power_run: false,
ls: Default::default(),
}
}
}
impl PllConfig {
pub(crate) fn init(self) -> u32 {
assert!(self.n >= 8 && self.n <= 86);
pub(crate) fn init(self) -> Hertz {
let (src, input_freq) = match self.source {
PllSrc::HSI16 => (vals::Pllsrc::HSI16, HSI_FREQ.0),
PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq.0),
PllSrc::HSI16 => (vals::Pllsrc::HSI, HSI_FREQ),
PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
};
let m_freq = input_freq / u32::from(self.m);
let m_freq = input_freq / self.m;
// RM0454 § 5.4.4:
// > Caution: The software must set these bits so that the PLL input frequency after the
// > /M divider is between 2.66 and 16 MHz.
debug_assert!(m_freq >= 2_660_000 && m_freq <= 16_000_000);
debug_assert!(m_freq.0 >= 2_660_000 && m_freq.0 <= 16_000_000);
let n_freq = m_freq * self.n as u32;
// RM0454 § 5.4.4:
// > Caution: The software must set these bits so that the VCO output frequency is between
// > 64 and 344 MHz.
debug_assert!(n_freq >= 64_000_000 && n_freq <= 344_000_000);
debug_assert!(n_freq.0 >= 64_000_000 && n_freq.0 <= 344_000_000);
let r_freq = n_freq / u32::from(self.r);
let r_freq = n_freq / self.r;
// RM0454 § 5.4.4:
// > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
debug_assert!(r_freq <= 64_000_000);
debug_assert!(r_freq.0 <= 64_000_000);
// RM0454 § 5.2.3:
// > To modify the PLL configuration, proceed as follows:
@ -239,25 +131,16 @@ impl PllConfig {
}
}
// Configure PLLSYSCFGR
RCC.pllsyscfgr().modify(|w| {
w.set_pllr(u8::from(self.r));
// Configure PLLCFGR
RCC.pllcfgr().modify(|w| {
w.set_pllr(self.r);
w.set_pllren(false);
if let Some(q) = self.q {
w.set_pllq(u8::from(q));
}
w.set_pllq(self.q.unwrap_or(Pllq::DIV2));
w.set_pllqen(false);
if let Some(p) = self.p {
w.set_pllp(u8::from(p));
}
w.set_pllp(self.p.unwrap_or(Pllp::DIV2));
w.set_pllpen(false);
w.set_plln(self.n);
w.set_pllm(self.m as u8);
w.set_pllm(self.m);
w.set_pllsrc(src)
});
@ -269,7 +152,7 @@ impl PllConfig {
// > 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
// > configuration register (RCC_PLLCFGR).
RCC.pllsyscfgr().modify(|w| {
RCC.pllcfgr().modify(|w| {
// We'll use R for system clock, so enable that unconditionally
w.set_pllren(true);
@ -286,39 +169,38 @@ pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw) = match config.mux {
ClockSrc::HSI16(div) => {
// Enable HSI16
let div: Hsidiv = div.into();
RCC.cr().write(|w| {
w.set_hsidiv(div);
w.set_hsion(true)
});
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0 >> div.to_bits(), Sw::HSI)
(HSI_FREQ / div, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
(freq, Sw::HSE)
}
ClockSrc::PLL(pll) => {
let freq = pll.init();
(freq, Sw::PLLRCLK)
(freq, Sw::PLL1_R)
}
ClockSrc::LSI => {
// Enable LSI
RCC.csr().write(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
(LSI_FREQ.0, Sw::LSI)
(super::LSI_FREQ, Sw::LSI)
}
};
// Determine the flash latency implied by the target clock speed
// RM0454 § 3.3.4:
let target_flash_latency = if sys_clk <= 24_000_000 {
let target_flash_latency = if sys_clk.0 <= 24_000_000 {
Latency::WS0
} else if sys_clk <= 48_000_000 {
} else if sys_clk.0 <= 48_000_000 {
Latency::WS1
} else {
Latency::WS2
@ -353,7 +235,7 @@ pub(crate) unsafe fn init(config: Config) {
}
// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
let (sw, hpre, ppre) = (sw.into(), config.ahb_pre.into(), config.apb_pre.into());
let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(hpre);
@ -374,27 +256,28 @@ pub(crate) unsafe fn init(config: Config) {
FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
}
let ahb_freq = Hertz(sys_clk) / config.ahb_pre;
let ahb_freq = sys_clk / config.ahb_pre;
let (apb_freq, apb_tim_freq) = match config.apb_pre {
APBPrescaler::DIV1 => (ahb_freq.0, ahb_freq.0),
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq.0 / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
if config.low_power_run {
assert!(sys_clk <= 2_000_000);
assert!(sys_clk.0 <= 2_000_000);
PWR.cr1().modify(|w| w.set_lpr(true));
}
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: ahb_freq,
apb1: Hertz(apb_freq),
apb1_tim: Hertz(apb_tim_freq),
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
rtc,
});
}

340
embassy-stm32/src/rcc/g4.rs
View File

@ -2,7 +2,10 @@ use stm32_metapac::flash::vals::Latency;
use stm32_metapac::rcc::vals::{Adcsel, Pllsrc, Sw};
use stm32_metapac::FLASH;
pub use super::bus::{AHBPrescaler, APBPrescaler};
pub use crate::pac::rcc::vals::{
Adcsel as AdcClockSource, Hpre as AHBPrescaler, Pllm as PllM, Plln as PllN, Pllp as PllP, Pllq as PllQ,
Pllr as PllR, Ppre as APBPrescaler,
};
use crate::pac::{PWR, RCC};
use crate::rcc::sealed::RccPeripheral;
use crate::rcc::{set_freqs, Clocks};
@ -11,32 +14,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
#[derive(Clone, Copy)]
pub enum AdcClockSource {
NoClk,
SysClk,
PllP,
}
impl AdcClockSource {
pub fn adcsel(&self) -> Adcsel {
match self {
AdcClockSource::NoClk => Adcsel::NOCLK,
AdcClockSource::SysClk => Adcsel::SYSCLK,
AdcClockSource::PllP => Adcsel::PLLP,
}
}
}
impl Default for AdcClockSource {
fn default() -> Self {
Self::NoClk
}
}
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
@ -56,182 +33,7 @@ impl Into<Pllsrc> for PllSrc {
fn into(self) -> Pllsrc {
match self {
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI16 => Pllsrc::HSI16,
}
}
}
seq_macro::seq!(P in 2..=31 {
/// Output divider for the PLL P output.
#[derive(Clone, Copy)]
pub enum PllP {
// Note: If PLL P is set to 0 the PLLP bit controls the output division. There does not seem to
// a good reason to do this so the API does not support it.
// Div1 is invalid
#(
Div~P,
)*
}
impl From<PllP> for u8 {
/// Returns the register value for the P output divider.
fn from(val: PllP) -> u8 {
match val {
#(
PllP::Div~P => P,
)*
}
}
}
});
impl PllP {
/// Returns the numeric value of the P output divider.
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
val as u32
}
}
/// Output divider for the PLL Q output.
#[derive(Clone, Copy)]
pub enum PllQ {
Div2,
Div4,
Div6,
Div8,
}
impl PllQ {
/// Returns the numeric value of the Q output divider.
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
(val as u32 + 1) * 2
}
}
impl From<PllQ> for u8 {
/// Returns the register value for the Q output divider.
fn from(val: PllQ) -> u8 {
match val {
PllQ::Div2 => 0b00,
PllQ::Div4 => 0b01,
PllQ::Div6 => 0b10,
PllQ::Div8 => 0b11,
}
}
}
/// Output divider for the PLL R output.
#[derive(Clone, Copy)]
pub enum PllR {
Div2,
Div4,
Div6,
Div8,
}
impl PllR {
/// Returns the numeric value of the R output divider.
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
(val as u32 + 1) * 2
}
}
impl From<PllR> for u8 {
/// Returns the register value for the R output divider.
fn from(val: PllR) -> u8 {
match val {
PllR::Div2 => 0b00,
PllR::Div4 => 0b01,
PllR::Div6 => 0b10,
PllR::Div8 => 0b11,
}
}
}
seq_macro::seq!(N in 8..=127 {
/// Multiplication factor for the PLL VCO input clock.
#[derive(Clone, Copy)]
pub enum PllN {
#(
Mul~N,
)*
}
impl From<PllN> for u8 {
/// Returns the register value for the N multiplication factor.
fn from(val: PllN) -> u8 {
match val {
#(
PllN::Mul~N => N,
)*
}
}
}
impl PllN {
/// Returns the numeric value of the N multiplication factor.
pub fn to_mul(self) -> u32 {
match self {
#(
PllN::Mul~N => N,
)*
}
}
}
});
/// PLL Pre-division. This must be set such that the PLL input is between 2.66 MHz and 16 MHz.
#[derive(Copy, Clone)]
pub enum PllM {
Div1,
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
Div9,
Div10,
Div11,
Div12,
Div13,
Div14,
Div15,
Div16,
}
impl PllM {
/// Returns the numeric value of the M pre-division.
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
val as u32 + 1
}
}
impl From<PllM> for u8 {
/// Returns the register value for the M pre-division.
fn from(val: PllM) -> u8 {
match val {
PllM::Div1 => 0b0000,
PllM::Div2 => 0b0001,
PllM::Div3 => 0b0010,
PllM::Div4 => 0b0011,
PllM::Div5 => 0b0100,
PllM::Div6 => 0b0101,
PllM::Div7 => 0b0110,
PllM::Div8 => 0b0111,
PllM::Div9 => 0b1000,
PllM::Div10 => 0b1001,
PllM::Div11 => 0b1010,
PllM::Div12 => 0b1011,
PllM::Div13 => 0b1100,
PllM::Div14 => 0b1101,
PllM::Div15 => 0b1110,
PllM::Div16 => 0b1111,
PllSrc::HSI16 => Pllsrc::HSI,
}
}
}
@ -261,32 +63,6 @@ pub struct Pll {
pub div_r: Option<PllR>,
}
fn ahb_div(ahb: AHBPrescaler) -> u32 {
match ahb {
AHBPrescaler::DIV1 => 1,
AHBPrescaler::DIV2 => 2,
AHBPrescaler::DIV4 => 4,
AHBPrescaler::DIV8 => 8,
AHBPrescaler::DIV16 => 16,
AHBPrescaler::DIV64 => 64,
AHBPrescaler::DIV128 => 128,
AHBPrescaler::DIV256 => 256,
AHBPrescaler::DIV512 => 512,
_ => unreachable!(),
}
}
fn apb_div(apb: APBPrescaler) -> u32 {
match apb {
APBPrescaler::DIV1 => 1,
APBPrescaler::DIV2 => 2,
APBPrescaler::DIV4 => 4,
APBPrescaler::DIV8 => 8,
APBPrescaler::DIV16 => 16,
_ => unreachable!(),
}
}
/// Sets the source for the 48MHz clock to the USB and RNG peripherals.
pub enum Clock48MhzSrc {
/// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
@ -322,6 +98,8 @@ pub struct Config {
pub clock_48mhz_src: Option<Clock48MhzSrc>,
pub adc12_clock_source: AdcClockSource,
pub adc345_clock_source: AdcClockSource,
pub ls: super::LsConfig,
}
/// Configuration for the Clock Recovery System (CRS) used to trim the HSI48 oscillator.
@ -340,9 +118,10 @@ impl Default for Config {
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
pll: None,
clock_48mhz_src: None,
adc12_clock_source: Default::default(),
adc345_clock_source: Default::default(),
clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(None)),
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
ls: Default::default(),
}
}
}
@ -360,12 +139,12 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
HSI_FREQ
}
PllSrc::HSE(freq) => {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
freq
}
};
@ -373,36 +152,36 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let internal_freq = src_freq / pll_config.prediv_m.to_div() * pll_config.mul_n.to_mul();
let internal_freq = src_freq / pll_config.prediv_m * pll_config.mul_n;
RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul_n.into());
w.set_pllm(pll_config.prediv_m.into());
w.set_plln(pll_config.mul_n);
w.set_pllm(pll_config.prediv_m);
w.set_pllsrc(pll_config.source.into());
});
let pll_p_freq = pll_config.div_p.map(|div_p| {
RCC.pllcfgr().modify(|w| {
w.set_pllpdiv(div_p.into());
w.set_pllp(div_p);
w.set_pllpen(true);
});
Hertz(internal_freq / div_p.to_div())
internal_freq / div_p
});
let pll_q_freq = pll_config.div_q.map(|div_q| {
RCC.pllcfgr().modify(|w| {
w.set_pllq(div_q.into());
w.set_pllq(div_q);
w.set_pllqen(true);
});
Hertz(internal_freq / div_q.to_div())
internal_freq / div_q
});
let pll_r_freq = pll_config.div_r.map(|div_r| {
RCC.pllcfgr().modify(|w| {
w.set_pllr(div_r.into());
w.set_pllr(div_r);
w.set_pllren(true);
});
Hertz(internal_freq / div_r.to_div())
internal_freq / div_r
});
// Enable the PLL
@ -422,14 +201,14 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0, Sw::HSI16)
(HSI_FREQ, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
(freq, Sw::HSE)
}
ClockSrc::PLL => {
assert!(pll_freq.is_some());
@ -470,35 +249,32 @@ pub(crate) unsafe fn init(config: Config) {
}
}
(freq, Sw::PLLRCLK)
(Hertz(freq), Sw::PLL1_R)
}
};
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => sys_clk / ahb_div(pre),
};
let ahb_freq = sys_clk / config.ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / apb_div(pre);
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / apb_div(pre);
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
@ -510,7 +286,7 @@ pub(crate) unsafe fn init(config: Config) {
let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
crate::pac::rcc::vals::Clk48sel::PLLQCLK
crate::pac::rcc::vals::Clk48sel::PLL1_Q
}
Clock48MhzSrc::Hsi48(crs_config) => {
// Enable HSI48
@ -520,7 +296,7 @@ pub(crate) unsafe fn init(config: Config) {
// Enable and setup CRS if needed
if let Some(crs_config) = crs_config {
crate::peripherals::CRS::enable();
crate::peripherals::CRS::enable_and_reset();
let sync_src = match crs_config.sync_src {
CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO,
@ -546,43 +322,41 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr().modify(|w| w.set_clk48sel(source));
}
RCC.ccipr()
.modify(|w| w.set_adc12sel(config.adc12_clock_source.adcsel()));
RCC.ccipr()
.modify(|w| w.set_adc345sel(config.adc345_clock_source.adcsel()));
RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
let adc12_ck = match config.adc12_clock_source {
AdcClockSource::NoClk => None,
AdcClockSource::PllP => match &pll_freq {
Some(pll) => pll.pll_p,
None => None,
},
AdcClockSource::SysClk => Some(Hertz(sys_clk)),
AdcClockSource::DISABLE => None,
AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(),
};
let adc345_ck = match config.adc345_clock_source {
AdcClockSource::NoClk => None,
AdcClockSource::PllP => match &pll_freq {
Some(pll) => pll.pll_p,
None => None,
},
AdcClockSource::SysClk => Some(Hertz(sys_clk)),
AdcClockSource::DISABLE => None,
AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(),
};
if config.low_power_run {
assert!(sys_clk <= 2_000_000);
assert!(sys_clk <= Hertz(2_000_000));
PWR.cr1().modify(|w| w.set_lpr(true));
}
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2: Hertz(apb2_freq),
apb2_tim: Hertz(apb2_tim_freq),
sys: sys_clk,
hclk1: ahb_freq,
hclk2: ahb_freq,
pclk1: apb1_freq,
pclk1_tim: apb1_tim_freq,
pclk2: apb2_freq,
pclk2_tim: apb2_tim_freq,
adc: adc12_ck,
adc34: adc345_ck,
pll1_p: None,
rtc,
});
}

159
embassy-stm32/src/rcc/h.rs
View File

@ -6,8 +6,8 @@ use crate::pac::pwr::vals::Vos;
pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
#[cfg(stm32h7)]
pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
pub use crate::pac::rcc::vals::Ckpersel as PerClockSource;
use crate::pac::rcc::vals::{Ckpersel, Hsidiv, Pllrge, Pllsrc, Pllvcosel, Sw, Timpre};
pub use crate::pac::rcc::vals::{Ckpersel as PerClockSource, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -21,18 +21,15 @@ pub const CSI_FREQ: Hertz = Hertz(4_000_000);
/// HSI48 speed
pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
const VCO_RANGE: RangeInclusive<u32> = 150_000_000..=420_000_000;
const VCO_RANGE: RangeInclusive<Hertz> = Hertz(150_000_000)..=Hertz(420_000_000);
#[cfg(any(stm32h5, pwr_h7rm0455))]
const VCO_WIDE_RANGE: RangeInclusive<u32> = 128_000_000..=560_000_000;
const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(128_000_000)..=Hertz(560_000_000);
#[cfg(pwr_h7rm0468)]
const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=836_000_000;
const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(836_000_000);
#[cfg(any(pwr_h7rm0399, pwr_h7rm0433))]
const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=960_000_000;
const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(960_000_000);
pub use super::bus::{AHBPrescaler, APBPrescaler};
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum VoltageScale {
@ -46,9 +43,9 @@ pub enum VoltageScale {
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
Oscillator,
/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
Bypass,
/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
#[cfg(any(rcc_h5, rcc_h50))]
BypassDigital,
}
@ -98,19 +95,19 @@ pub struct Pll {
#[cfg(stm32h5)]
pub source: PllSource,
/// PLL pre-divider (DIVM). Must be between 1 and 63.
pub prediv: u8,
/// PLL pre-divider (DIVM).
pub prediv: PllPreDiv,
/// PLL multiplication factor. Must be between 4 and 512.
pub mul: u16,
/// PLL multiplication factor.
pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
/// PLL P division factor. If None, PLL P output is disabled.
/// On PLL1, it must be even (in particular, it cannot be 1.)
pub divp: Option<u16>,
/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
pub divq: Option<u16>,
/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
pub divr: Option<u16>,
pub divp: Option<PllDiv>,
/// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<PllDiv>,
/// PLL R division factor. If None, PLL R output is disabled.
pub divr: Option<PllDiv>,
}
fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz {
@ -181,6 +178,7 @@ pub struct Config {
pub adc_clock_source: AdcClockSource,
pub timer_prescaler: TimerPrescaler,
pub voltage_scale: VoltageScale,
pub ls: super::LsConfig,
}
impl Default for Config {
@ -210,6 +208,7 @@ impl Default for Config {
adc_clock_source: AdcClockSource::from_bits(0), // PLL2_P on H7, HCLK on H5
timer_prescaler: TimerPrescaler::DefaultX2,
voltage_scale: VoltageScale::Scale0,
ls: Default::default(),
}
}
}
@ -372,14 +371,14 @@ pub(crate) unsafe fn init(config: Config) {
let pll1 = init_pll(0, config.pll1, &pll_input);
let pll2 = init_pll(1, config.pll2, &pll_input);
#[cfg(any(rcc_h5, stm32h7))]
let _pll3 = init_pll(2, config.pll3, &pll_input);
let pll3 = init_pll(2, config.pll3, &pll_input);
// Configure sysclk
let (sys, sw) = match config.sys {
Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
Sysclk::HSE => (unwrap!(hse), Sw::HSE),
Sysclk::CSI => (unwrap!(csi), Sw::CSI),
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1_P),
};
// Check limits.
@ -431,23 +430,25 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h7)]
let adc = match config.adc_clock_source {
AdcClockSource::PLL2_P => pll2.p,
AdcClockSource::PLL3_R => _pll3.r,
AdcClockSource::PLL3_R => pll3.r,
AdcClockSource::PER => _per_ck,
_ => unreachable!(),
};
#[cfg(stm32h5)]
let adc = match config.adc_clock_source {
AdcClockSource::HCLK => Some(hclk),
AdcClockSource::SYSCLK => Some(sys),
AdcClockSource::HCLK1 => Some(hclk),
AdcClockSource::SYS => Some(sys),
AdcClockSource::PLL2_R => pll2.r,
AdcClockSource::HSE => hse,
AdcClockSource::HSI_KER => hsi,
AdcClockSource::CSI_KER => csi,
AdcClockSource::HSI => hsi,
AdcClockSource::CSI => csi,
_ => unreachable!(),
};
flash_setup(hclk, config.voltage_scale);
let rtc = config.ls.init();
#[cfg(stm32h7)]
{
RCC.d1cfgr().modify(|w| {
@ -514,18 +515,65 @@ pub(crate) unsafe fn init(config: Config) {
set_freqs(Clocks {
sys,
ahb1: hclk,
ahb2: hclk,
ahb3: hclk,
ahb4: hclk,
apb1,
apb2,
apb3,
hclk1: hclk,
hclk2: hclk,
hclk3: hclk,
hclk4: hclk,
pclk1: apb1,
pclk2: apb2,
pclk3: apb3,
#[cfg(stm32h7)]
apb4,
apb1_tim,
apb2_tim,
adc: adc,
pclk4: apb4,
#[cfg(stm32h5)]
pclk4: Hertz(1),
pclk1_tim: apb1_tim,
pclk2_tim: apb2_tim,
adc,
rtc,
#[cfg(any(stm32h5, stm32h7))]
hsi: None,
#[cfg(stm32h5)]
hsi48: None,
#[cfg(stm32h5)]
lsi: None,
#[cfg(any(stm32h5, stm32h7))]
csi: None,
#[cfg(any(stm32h5, stm32h7))]
lse: None,
#[cfg(any(stm32h5, stm32h7))]
hse: None,
#[cfg(any(stm32h5, stm32h7))]
pll1_q: pll1.q,
#[cfg(any(stm32h5, stm32h7))]
pll2_p: pll2.p,
#[cfg(any(stm32h5, stm32h7))]
pll2_q: pll2.q,
#[cfg(any(stm32h5, stm32h7))]
pll2_r: pll2.r,
#[cfg(any(rcc_h5, stm32h7))]
pll3_p: pll3.p,
#[cfg(any(rcc_h5, stm32h7))]
pll3_q: pll3.q,
#[cfg(any(rcc_h5, stm32h7))]
pll3_r: pll3.r,
#[cfg(rcc_h50)]
pll3_p: None,
#[cfg(rcc_h50)]
pll3_q: None,
#[cfg(rcc_h50)]
pll3_r: None,
#[cfg(stm32h5)]
audioclk: None,
#[cfg(any(stm32h5, stm32h7))]
per: None,
#[cfg(stm32h7)]
rcc_pclk_d3: None,
});
}
@ -553,9 +601,9 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
// "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
#[cfg(stm32h7)]
RCC.pllckselr().write(|w| w.set_divm(num, 0));
RCC.pllckselr().write(|w| w.set_divm(num, PllPreDiv::from_bits(0)));
#[cfg(stm32h5)]
RCC.pllcfgr(num).write(|w| w.set_divm(0));
RCC.pllcfgr(num).write(|w| w.set_divm(PllPreDiv::from_bits(0)));
return PllOutput {
p: None,
@ -564,9 +612,6 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
};
};
assert!(1 <= config.prediv && config.prediv <= 63);
assert!(4 <= config.mul && config.mul <= 512);
#[cfg(stm32h5)]
let source = config.source;
#[cfg(stm32h7)]
@ -593,31 +638,25 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
let wide_allowed = ref_range != Pllrge::RANGE1;
let vco_clk = ref_clk * config.mul;
let vco_range = if VCO_RANGE.contains(&vco_clk.0) {
let vco_range = if VCO_RANGE.contains(&vco_clk) {
Pllvcosel::MEDIUMVCO
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk.0) {
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
Pllvcosel::WIDEVCO
} else {
panic!("pll vco_clk out of range: {} mhz", vco_clk.0)
};
let p = config.divp.map(|div| {
assert!(1 <= div && div <= 128);
if num == 0 {
// on PLL1, DIVP must be even.
assert!(div % 2 == 0);
// The enum value is 1 less than the divider, so check it's odd.
assert!(div.to_bits() % 2 == 1);
}
vco_clk / div
});
let q = config.divq.map(|div| {
assert!(1 <= div && div <= 128);
vco_clk / div
});
let r = config.divr.map(|div| {
assert!(1 <= div && div <= 128);
vco_clk / div
});
let q = config.divq.map(|div| vco_clk / div);
let r = config.divr.map(|div| vco_clk / div);
#[cfg(stm32h5)]
RCC.pllcfgr(num).write(|w| {
@ -648,10 +687,10 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
}
RCC.plldivr(num).write(|w| {
w.set_plln(config.mul - 1);
w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
w.set_plln(config.mul);
w.set_pllp(config.divp.unwrap_or(PllDiv::DIV2));
w.set_pllq(config.divq.unwrap_or(PllDiv::DIV2));
w.set_pllr(config.divr.unwrap_or(PllDiv::DIV2));
});
RCC.cr().modify(|w| w.set_pllon(num, true));

349
embassy-stm32/src/rcc/l0.rs
View File

@ -1,349 +0,0 @@
use super::bd::BackupDomain;
pub use super::bus::{AHBPrescaler, APBPrescaler};
use super::RtcClockSource;
pub use crate::pac::pwr::vals::Vos as VoltageScale;
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
#[cfg(crs)]
use crate::pac::{crs, CRS, SYSCFG};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLMul, PLLDiv),
HSE(Hertz),
HSI16,
}
/// MSI Clock Range
///
/// These ranges control the frequency of the MSI. Internally, these ranges map
/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
#[derive(Clone, Copy)]
pub enum MSIRange {
/// Around 65.536 kHz
Range0,
/// Around 131.072 kHz
Range1,
/// Around 262.144 kHz
Range2,
/// Around 524.288 kHz
Range3,
/// Around 1.048 MHz
Range4,
/// Around 2.097 MHz (reset value)
Range5,
/// Around 4.194 MHz
Range6,
}
impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range5
}
}
/// PLL divider
#[derive(Clone, Copy)]
pub enum PLLDiv {
Div2,
Div3,
Div4,
}
/// PLL multiplier
#[derive(Clone, Copy)]
pub enum PLLMul {
Mul3,
Mul4,
Mul6,
Mul8,
Mul12,
Mul16,
Mul24,
Mul32,
Mul48,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI16,
HSE(Hertz),
}
impl From<PLLMul> for Pllmul {
fn from(val: PLLMul) -> Pllmul {
match val {
PLLMul::Mul3 => Pllmul::MUL3,
PLLMul::Mul4 => Pllmul::MUL4,
PLLMul::Mul6 => Pllmul::MUL6,
PLLMul::Mul8 => Pllmul::MUL8,
PLLMul::Mul12 => Pllmul::MUL12,
PLLMul::Mul16 => Pllmul::MUL16,
PLLMul::Mul24 => Pllmul::MUL24,
PLLMul::Mul32 => Pllmul::MUL32,
PLLMul::Mul48 => Pllmul::MUL48,
}
}
}
impl From<PLLDiv> for Plldiv {
fn from(val: PLLDiv) -> Plldiv {
match val {
PLLDiv::Div2 => Plldiv::DIV2,
PLLDiv::Div3 => Plldiv::DIV3,
PLLDiv::Div4 => Plldiv::DIV4,
}
}
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI16,
PLLSource::HSE(_) => Pllsrc::HSE,
}
}
}
impl From<MSIRange> for Msirange {
fn from(val: MSIRange) -> Msirange {
match val {
MSIRange::Range0 => Msirange::RANGE0,
MSIRange::Range1 => Msirange::RANGE1,
MSIRange::Range2 => Msirange::RANGE2,
MSIRange::Range3 => Msirange::RANGE3,
MSIRange::Range4 => Msirange::RANGE4,
MSIRange::Range5 => Msirange::RANGE5,
MSIRange::Range6 => Msirange::RANGE6,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
#[cfg(crs)]
pub enable_hsi48: bool,
pub rtc: Option<RtcClockSource>,
pub lse: Option<Hertz>,
pub lsi: bool,
pub voltage_scale: VoltageScale,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::default()),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
#[cfg(crs)]
enable_hsi48: false,
rtc: None,
lse: None,
lsi: false,
voltage_scale: VoltageScale::RANGE1,
}
}
}
pub(crate) unsafe fn init(config: Config) {
// Set voltage scale
while PWR.csr().read().vosf() {}
PWR.cr().write(|w| w.set_vos(config.voltage_scale));
while PWR.csr().read().vosf() {}
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Set MSI range
RCC.icscr().write(|w| w.set_msirange(range.into()));
// Enable MSI
RCC.cr().write(|w| w.set_msion(true));
while !RCC.cr().read().msirdy() {}
let freq = 32_768 * (1 << (range as u8 + 1));
(freq, Sw::MSI)
}
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdyf() {}
(HSI_FREQ.0, Sw::HSI16)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
}
ClockSrc::PLL(src, mul, div) => {
let freq = match src {
PLLSource::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
}
PLLSource::HSI16 => {
// Enable HSI
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdyf() {}
HSI_FREQ.0
}
};
// Disable PLL
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let freq = match mul {
PLLMul::Mul3 => freq * 3,
PLLMul::Mul4 => freq * 4,
PLLMul::Mul6 => freq * 6,
PLLMul::Mul8 => freq * 8,
PLLMul::Mul12 => freq * 12,
PLLMul::Mul16 => freq * 16,
PLLMul::Mul24 => freq * 24,
PLLMul::Mul32 => freq * 32,
PLLMul::Mul48 => freq * 48,
};
let freq = match div {
PLLDiv::Div2 => freq / 2,
PLLDiv::Div3 => freq / 3,
PLLDiv::Div4 => freq / 4,
};
assert!(freq <= 32_000_000);
RCC.cfgr().write(move |w| {
w.set_pllmul(mul.into());
w.set_plldiv(div.into());
w.set_pllsrc(src.into());
});
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
(freq, Sw::PLL)
}
};
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let wait_states = match config.voltage_scale {
VoltageScale::RANGE1 => match sys_clk {
..=16_000_000 => 0,
_ => 1,
},
VoltageScale::RANGE2 => match sys_clk {
..=8_000_000 => 0,
_ => 1,
},
VoltageScale::RANGE3 => 0,
_ => unreachable!(),
};
FLASH.acr().modify(|w| {
w.set_latency(wait_states != 0);
});
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: Hpre = pre.into();
let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
#[cfg(crs)]
if config.enable_hsi48 {
// Reset CRS peripheral
RCC.apb1rstr().modify(|w| w.set_crsrst(true));
RCC.apb1rstr().modify(|w| w.set_crsrst(false));
// Enable CRS peripheral
RCC.apb1enr().modify(|w| w.set_crsen(true));
// Initialize CRS
CRS.cfgr().write(|w|
// Select LSE as synchronization source
w.set_syncsrc(crs::vals::Syncsrc::LSE));
CRS.cr().modify(|w| {
w.set_autotrimen(true);
w.set_cen(true);
});
// Enable VREFINT reference for HSI48 oscillator
SYSCFG.cfgr3().modify(|w| {
w.set_enref_hsi48(true);
w.set_en_vrefint(true);
});
// Select HSI48 as USB clock
RCC.ccipr().modify(|w| w.set_hsi48msel(true));
// Enable dedicated USB clock
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
}
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
});
}

219
embassy-stm32/src/rcc/l0l1.rs Normal file
View File

@ -0,0 +1,219 @@
pub use crate::pac::pwr::vals::Vos as VoltageScale;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Pllmul as PLLMul, Ppre as APBPrescaler,
};
use crate::pac::rcc::vals::{Pllsrc, Sw};
#[cfg(crs)]
use crate::pac::{crs, CRS, SYSCFG};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLMul, PLLDiv),
HSE(Hertz),
HSI16,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI16,
HSE(Hertz),
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI,
PLLSource::HSE(_) => Pllsrc::HSE,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
#[cfg(crs)]
pub enable_hsi48: bool,
pub ls: super::LsConfig,
pub voltage_scale: VoltageScale,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::RANGE5),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
#[cfg(crs)]
enable_hsi48: false,
voltage_scale: VoltageScale::RANGE1,
ls: Default::default(),
}
}
}
pub(crate) unsafe fn init(config: Config) {
// Set voltage scale
while PWR.csr().read().vosf() {}
PWR.cr().write(|w| w.set_vos(config.voltage_scale));
while PWR.csr().read().vosf() {}
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Set MSI range
RCC.icscr().write(|w| w.set_msirange(range));
// Enable MSI
RCC.cr().write(|w| w.set_msion(true));
while !RCC.cr().read().msirdy() {}
let freq = 32_768 * (1 << (range as u8 + 1));
(Hertz(freq), Sw::MSI)
}
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdy() {}
(HSI_FREQ, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq, Sw::HSE)
}
ClockSrc::PLL(src, mul, div) => {
let freq = match src {
PLLSource::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq
}
PLLSource::HSI16 => {
// Enable HSI
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdy() {}
HSI_FREQ
}
};
// Disable PLL
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let freq = freq * mul / div;
assert!(freq <= Hertz(32_000_000));
RCC.cfgr().write(move |w| {
w.set_pllmul(mul);
w.set_plldiv(div);
w.set_pllsrc(src.into());
});
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
(freq, Sw::PLL1_P)
}
};
let rtc = config.ls.init();
let wait_states = match (config.voltage_scale, sys_clk.0) {
(VoltageScale::RANGE1, ..=16_000_000) => 0,
(VoltageScale::RANGE2, ..=8_000_000) => 0,
(VoltageScale::RANGE3, ..=4_200_000) => 0,
_ => 1,
};
#[cfg(stm32l1)]
FLASH.acr().write(|w| w.set_acc64(true));
FLASH.acr().modify(|w| w.set_prften(true));
FLASH.acr().modify(|w| w.set_latency(wait_states != 0));
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
let ahb_freq = sys_clk / config.ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
#[cfg(crs)]
if config.enable_hsi48 {
// Reset CRS peripheral
RCC.apb1rstr().modify(|w| w.set_crsrst(true));
RCC.apb1rstr().modify(|w| w.set_crsrst(false));
// Enable CRS peripheral
RCC.apb1enr().modify(|w| w.set_crsen(true));
// Initialize CRS
CRS.cfgr().write(|w|
// Select LSE as synchronization source
w.set_syncsrc(crs::vals::Syncsrc::LSE));
CRS.cr().modify(|w| {
w.set_autotrimen(true);
w.set_cen(true);
});
// Enable VREFINT reference for HSI48 oscillator
SYSCFG.cfgr3().modify(|w| {
w.set_enref_hsi48(true);
w.set_en_vrefint(true);
});
// Select HSI48 as USB clock
RCC.ccipr().modify(|w| w.set_hsi48msel(true));
// Enable dedicated USB clock
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
}
set_freqs(Clocks {
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb1_freq,
pclk2: apb2_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
rtc,
});
}

279
embassy-stm32/src/rcc/l1.rs
View File

@ -1,279 +0,0 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLMul, PLLDiv),
HSE(Hertz),
HSI,
}
/// MSI Clock Range
///
/// These ranges control the frequency of the MSI. Internally, these ranges map
/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
#[derive(Clone, Copy)]
pub enum MSIRange {
/// Around 65.536 kHz
Range0,
/// Around 131.072 kHz
Range1,
/// Around 262.144 kHz
Range2,
/// Around 524.288 kHz
Range3,
/// Around 1.048 MHz
Range4,
/// Around 2.097 MHz (reset value)
Range5,
/// Around 4.194 MHz
Range6,
}
impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range5
}
}
/// PLL divider
#[derive(Clone, Copy)]
pub enum PLLDiv {
Div2,
Div3,
Div4,
}
/// PLL multiplier
#[derive(Clone, Copy)]
pub enum PLLMul {
Mul3,
Mul4,
Mul6,
Mul8,
Mul12,
Mul16,
Mul24,
Mul32,
Mul48,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI,
HSE(Hertz),
}
impl From<PLLMul> for Pllmul {
fn from(val: PLLMul) -> Pllmul {
match val {
PLLMul::Mul3 => Pllmul::MUL3,
PLLMul::Mul4 => Pllmul::MUL4,
PLLMul::Mul6 => Pllmul::MUL6,
PLLMul::Mul8 => Pllmul::MUL8,
PLLMul::Mul12 => Pllmul::MUL12,
PLLMul::Mul16 => Pllmul::MUL16,
PLLMul::Mul24 => Pllmul::MUL24,
PLLMul::Mul32 => Pllmul::MUL32,
PLLMul::Mul48 => Pllmul::MUL48,
}
}
}
impl From<PLLDiv> for Plldiv {
fn from(val: PLLDiv) -> Plldiv {
match val {
PLLDiv::Div2 => Plldiv::DIV2,
PLLDiv::Div3 => Plldiv::DIV3,
PLLDiv::Div4 => Plldiv::DIV4,
}
}
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI => Pllsrc::HSI,
PLLSource::HSE(_) => Pllsrc::HSE,
}
}
}
impl From<MSIRange> for Msirange {
fn from(val: MSIRange) -> Msirange {
match val {
MSIRange::Range0 => Msirange::RANGE0,
MSIRange::Range1 => Msirange::RANGE1,
MSIRange::Range2 => Msirange::RANGE2,
MSIRange::Range3 => Msirange::RANGE3,
MSIRange::Range4 => Msirange::RANGE4,
MSIRange::Range5 => Msirange::RANGE5,
MSIRange::Range6 => Msirange::RANGE6,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::default()),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
}
}
}
pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Set MSI range
RCC.icscr().write(|w| w.set_msirange(range.into()));
// Enable MSI
RCC.cr().write(|w| w.set_msion(true));
while !RCC.cr().read().msirdy() {}
let freq = 32_768 * (1 << (range as u8 + 1));
(freq, Sw::MSI)
}
ClockSrc::HSI => {
// Enable HSI
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0, Sw::HSI)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
}
ClockSrc::PLL(src, mul, div) => {
let freq = match src {
PLLSource::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
}
PLLSource::HSI => {
// Enable HSI
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
};
// Disable PLL
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let freq = match mul {
PLLMul::Mul3 => freq * 3,
PLLMul::Mul4 => freq * 4,
PLLMul::Mul6 => freq * 6,
PLLMul::Mul8 => freq * 8,
PLLMul::Mul12 => freq * 12,
PLLMul::Mul16 => freq * 16,
PLLMul::Mul24 => freq * 24,
PLLMul::Mul32 => freq * 32,
PLLMul::Mul48 => freq * 48,
};
let freq = match div {
PLLDiv::Div2 => freq / 2,
PLLDiv::Div3 => freq / 3,
PLLDiv::Div4 => freq / 4,
};
assert!(freq <= 32_000_000);
RCC.cfgr().write(move |w| {
w.set_pllmul(mul.into());
w.set_plldiv(div.into());
w.set_pllsrc(src.into());
});
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
(freq, Sw::PLL)
}
};
// Set flash 64-bit access, prefetch and wait states
if sys_clk >= 16_000_000 {
FLASH.acr().write(|w| w.set_acc64(true));
FLASH.acr().modify(|w| w.set_prften(true));
FLASH.acr().modify(|w| w.set_latency(true));
}
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: Hpre = pre.into();
let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
});
}

619
embassy-stm32/src/rcc/l4.rs
View File

@ -1,619 +0,0 @@
use core::marker::PhantomData;
use embassy_hal_internal::into_ref;
use stm32_metapac::rcc::regs::Cfgr;
use stm32_metapac::rcc::vals::{Mcopre, Mcosel};
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLClkDiv, PLLSrcDiv, PLLMul, Option<PLL48Div>),
HSE(Hertz),
HSI16,
}
/// MSI Clock Range
///
/// These ranges control the frequency of the MSI. Internally, these ranges map
/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
#[derive(Clone, Copy)]
pub enum MSIRange {
/// Around 100 kHz
Range0,
/// Around 200 kHz
Range1,
/// Around 400 kHz
Range2,
/// Around 800 kHz
Range3,
/// Around 1 MHz
Range4,
/// Around 2 MHz
Range5,
/// Around 4 MHz (reset value)
Range6,
/// Around 8 MHz
Range7,
/// Around 16 MHz
Range8,
/// Around 24 MHz
Range9,
/// Around 32 MHz
Range10,
/// Around 48 MHz
Range11,
}
impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range6
}
}
pub type PLL48Div = PLLClkDiv;
pub type PLLSAI1RDiv = PLLClkDiv;
pub type PLLSAI1QDiv = PLLClkDiv;
pub type PLLSAI1PDiv = PLLClkDiv;
/// PLL divider
#[derive(Clone, Copy)]
pub enum PLLDiv {
Div2,
Div3,
Div4,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI16,
HSE(Hertz),
MSI(MSIRange),
}
seq_macro::seq!(N in 8..=86 {
#[derive(Clone, Copy)]
pub enum PLLMul {
#(
Mul~N,
)*
}
impl From<PLLMul> for u8 {
fn from(val: PLLMul) -> u8 {
match val {
#(
PLLMul::Mul~N => N,
)*
}
}
}
impl PLLMul {
pub fn to_mul(self) -> u32 {
match self {
#(
PLLMul::Mul~N => N,
)*
}
}
}
});
#[derive(Clone, Copy)]
pub enum PLLClkDiv {
Div2,
Div4,
Div6,
Div8,
}
impl PLLClkDiv {
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
(val as u32 + 1) * 2
}
}
impl From<PLLClkDiv> for u8 {
fn from(val: PLLClkDiv) -> u8 {
match val {
PLLClkDiv::Div2 => 0b00,
PLLClkDiv::Div4 => 0b01,
PLLClkDiv::Div6 => 0b10,
PLLClkDiv::Div8 => 0b11,
}
}
}
#[derive(Clone, Copy)]
pub enum PLLSrcDiv {
Div1,
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
}
impl PLLSrcDiv {
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
val as u32 + 1
}
}
impl From<PLLSrcDiv> for u8 {
fn from(val: PLLSrcDiv) -> u8 {
match val {
PLLSrcDiv::Div1 => 0b000,
PLLSrcDiv::Div2 => 0b001,
PLLSrcDiv::Div3 => 0b010,
PLLSrcDiv::Div4 => 0b011,
PLLSrcDiv::Div5 => 0b100,
PLLSrcDiv::Div6 => 0b101,
PLLSrcDiv::Div7 => 0b110,
PLLSrcDiv::Div8 => 0b111,
}
}
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI16,
PLLSource::HSE(_) => Pllsrc::HSE,
PLLSource::MSI(_) => Pllsrc::MSI,
}
}
}
impl From<MSIRange> for Msirange {
fn from(val: MSIRange) -> Msirange {
match val {
MSIRange::Range0 => Msirange::RANGE100K,
MSIRange::Range1 => Msirange::RANGE200K,
MSIRange::Range2 => Msirange::RANGE400K,
MSIRange::Range3 => Msirange::RANGE800K,
MSIRange::Range4 => Msirange::RANGE1M,
MSIRange::Range5 => Msirange::RANGE2M,
MSIRange::Range6 => Msirange::RANGE4M,
MSIRange::Range7 => Msirange::RANGE8M,
MSIRange::Range8 => Msirange::RANGE16M,
MSIRange::Range9 => Msirange::RANGE24M,
MSIRange::Range10 => Msirange::RANGE32M,
MSIRange::Range11 => Msirange::RANGE48M,
}
}
}
impl From<MSIRange> for u32 {
fn from(val: MSIRange) -> u32 {
match val {
MSIRange::Range0 => 100_000,
MSIRange::Range1 => 200_000,
MSIRange::Range2 => 400_000,
MSIRange::Range3 => 800_000,
MSIRange::Range4 => 1_000_000,
MSIRange::Range5 => 2_000_000,
MSIRange::Range6 => 4_000_000,
MSIRange::Range7 => 8_000_000,
MSIRange::Range8 => 16_000_000,
MSIRange::Range9 => 24_000_000,
MSIRange::Range10 => 32_000_000,
MSIRange::Range11 => 48_000_000,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub pllsai1: Option<(
PLLMul,
PLLSrcDiv,
Option<PLLSAI1RDiv>,
Option<PLLSAI1QDiv>,
Option<PLLSAI1PDiv>,
)>,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
pub hsi48: bool,
pub rtc_mux: RtcClockSource,
pub lse: Option<Hertz>,
pub lsi: bool,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::Range6),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
pllsai1: None,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
hsi48: false,
rtc_mux: RtcClockSource::LSI,
lsi: true,
lse: None,
}
}
}
pub enum McoClock {
DIV1,
DIV2,
DIV4,
DIV8,
DIV16,
}
impl McoClock {
fn into_raw(&self) -> Mcopre {
match self {
McoClock::DIV1 => Mcopre::DIV1,
McoClock::DIV2 => Mcopre::DIV2,
McoClock::DIV4 => Mcopre::DIV4,
McoClock::DIV8 => Mcopre::DIV8,
McoClock::DIV16 => Mcopre::DIV16,
}
}
}
#[derive(Copy, Clone)]
pub enum Mco1Source {
Disabled,
Lse,
Lsi,
Hse,
Hsi16,
PllClk,
SysClk,
Msi,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
Hsi48,
}
impl Default for Mco1Source {
fn default() -> Self {
Self::Hsi16
}
}
pub trait McoSource {
type Raw;
fn into_raw(&self) -> Self::Raw;
}
impl McoSource for Mco1Source {
type Raw = Mcosel;
fn into_raw(&self) -> Self::Raw {
match self {
Mco1Source::Disabled => Mcosel::NOCLOCK,
Mco1Source::Lse => Mcosel::LSE,
Mco1Source::Lsi => Mcosel::LSI,
Mco1Source::Hse => Mcosel::HSE,
Mco1Source::Hsi16 => Mcosel::HSI16,
Mco1Source::PllClk => Mcosel::PLL,
Mco1Source::SysClk => Mcosel::SYSCLK,
Mco1Source::Msi => Mcosel::MSI,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
Mco1Source::Hsi48 => Mcosel::HSI48,
}
}
}
pub(crate) mod sealed {
use stm32_metapac::rcc::vals::Mcopre;
pub trait McoInstance {
type Source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre);
}
}
pub trait McoInstance: sealed::McoInstance + 'static {}
pin_trait!(McoPin, McoInstance);
impl sealed::McoInstance for peripherals::MCO {
type Source = Mcosel;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
RCC.cfgr().modify(|w| {
w.set_mcosel(source);
w.set_mcopre(prescaler);
});
match source {
Mcosel::HSI16 => {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
Mcosel::HSI48 => {
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
}
_ => {}
}
}
}
impl McoInstance for peripherals::MCO {}
pub struct Mco<'d, T: McoInstance> {
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: McoInstance> Mco<'d, T> {
pub fn new(
_peri: impl Peripheral<P = T> + 'd,
pin: impl Peripheral<P = impl McoPin<T>> + 'd,
source: impl McoSource<Raw = T::Source>,
prescaler: McoClock,
) -> Self {
into_ref!(pin);
critical_section::with(|_| unsafe {
T::apply_clock_settings(source.into_raw(), prescaler.into_raw());
pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
pin.set_speed(Speed::VeryHigh);
});
Self { phantom: PhantomData }
}
}
pub(crate) unsafe fn init(config: Config) {
// Switch to MSI to prevent problems with PLL configuration.
if !RCC.cr().read().msion() {
// Turn on MSI and configure it to 4MHz.
RCC.cr().modify(|w| {
w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
w.set_msirange(MSIRange::default().into());
w.set_msipllen(false);
w.set_msion(true)
});
// Wait until MSI is running
while !RCC.cr().read().msirdy() {}
}
if RCC.cfgr().read().sws() != Sw::MSI {
// Set MSI as a clock source, reset prescalers.
RCC.cfgr().write_value(Cfgr::default());
// Wait for clock switch status bits to change.
while RCC.cfgr().read().sws() != Sw::MSI {}
}
BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Enable MSI
RCC.cr().write(|w| {
let bits: Msirange = range.into();
w.set_msirange(bits);
w.set_msirgsel(true);
w.set_msion(true);
if let RtcClockSource::LSE = config.rtc_mux {
// If LSE is enabled, enable calibration of MSI
w.set_msipllen(true);
} else {
w.set_msipllen(false);
}
});
while !RCC.cr().read().msirdy() {}
// Enable as clock source for USB, RNG if running at 48 MHz
if let MSIRange::Range11 = range {
RCC.ccipr().modify(|w| {
w.set_clk48sel(0b11);
});
}
(range.into(), Sw::MSI)
}
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0, Sw::HSI16)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
}
ClockSrc::PLL(src, div, prediv, mul, pll48div) => {
let src_freq = match src {
PLLSource::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
}
PLLSource::HSI16 => {
// Enable HSI
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
PLLSource::MSI(range) => {
// Enable MSI
RCC.cr().write(|w| {
let bits: Msirange = range.into();
w.set_msirange(bits);
w.set_msipllen(false); // should be turned on if LSE is started
w.set_msirgsel(true);
w.set_msion(true);
});
while !RCC.cr().read().msirdy() {}
range.into()
}
};
// Disable PLL
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / div.to_div();
#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
assert!(freq <= 120_000_000);
#[cfg(not(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx)))]
assert!(freq <= 80_000_000);
RCC.pllcfgr().write(move |w| {
w.set_plln(mul.into());
w.set_pllm(prediv.into());
w.set_pllr(div.into());
if let Some(pll48div) = pll48div {
w.set_pllq(pll48div.into());
w.set_pllqen(true);
}
w.set_pllsrc(src.into());
});
// Enable as clock source for USB, RNG if PLL48 divisor is provided
if let Some(pll48div) = pll48div {
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / pll48div.to_div();
assert!(freq == 48_000_000);
RCC.ccipr().modify(|w| {
w.set_clk48sel(0b10);
});
}
if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
RCC.pllsai1cfgr().write(move |w| {
w.set_pllsai1n(mul.into());
w.set_pllsai1m(prediv.into());
if let Some(r_div) = r_div {
w.set_pllsai1r(r_div.into());
w.set_pllsai1ren(true);
}
if let Some(q_div) = q_div {
w.set_pllsai1q(q_div.into());
w.set_pllsai1qen(true);
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / q_div.to_div();
if freq == 48_000_000 {
RCC.ccipr().modify(|w| {
w.set_clk48sel(0b1);
});
}
}
if let Some(p_div) = p_div {
w.set_pllsai1pdiv(p_div.into());
w.set_pllsai1pen(true);
}
});
RCC.cr().modify(|w| w.set_pllsai1on(true));
}
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
RCC.pllcfgr().modify(|w| w.set_pllren(true));
(freq, Sw::PLL)
}
};
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
if config.hsi48 {
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
// Enable as clock source for USB, RNG and SDMMC
RCC.ccipr().modify(|w| w.set_clk48sel(0));
}
// Set flash wait states
FLASH.acr().modify(|w| {
w.set_latency(if sys_clk <= 16_000_000 {
0b000
} else if sys_clk <= 32_000_000 {
0b001
} else if sys_clk <= 48_000_000 {
0b010
} else if sys_clk <= 64_000_000 {
0b011
} else {
0b100
});
});
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: Hpre = pre.into();
let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
ahb3: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
});
}

441
embassy-stm32/src/rcc/l4l5.rs Normal file
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@ -0,0 +1,441 @@
use crate::pac::rcc::regs::Cfgr;
use crate::pac::rcc::vals::Msirgsel;
pub use crate::pac::rcc::vals::{
Clk48sel as Clk48Src, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
#[derive(Clone, Copy)]
pub struct Pll {
/// PLL source
pub source: PLLSource,
/// PLL pre-divider (DIVM).
pub prediv: PllPreDiv,
/// PLL multiplication factor.
pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled.
pub divp: Option<PllPDiv>,
/// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<PllQDiv>,
/// PLL R division factor. If None, PLL R output is disabled.
pub divr: Option<PllRDiv>,
}
/// Clocks configutation
pub struct Config {
// base clock sources
pub msi: Option<MSIRange>,
pub hsi16: bool,
pub hse: Option<Hertz>,
#[cfg(not(any(stm32l47x, stm32l48x)))]
pub hsi48: bool,
// pll
pub pll: Option<Pll>,
pub pllsai1: Option<Pll>,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
pub pllsai2: Option<Pll>,
// sysclk, buses.
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
// muxes
pub clk48_src: Clk48Src,
// low speed LSI/LSE/RTC
pub ls: super::LsConfig,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
hse: None,
hsi16: false,
msi: Some(MSIRange::RANGE4M),
mux: ClockSrc::MSI,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
pll: None,
pllsai1: None,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
pllsai2: None,
#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
hsi48: true,
clk48_src: Clk48Src::HSI48,
ls: Default::default(),
}
}
}
pub(crate) unsafe fn init(config: Config) {
// Switch to MSI to prevent problems with PLL configuration.
if !RCC.cr().read().msion() {
// Turn on MSI and configure it to 4MHz.
RCC.cr().modify(|w| {
w.set_msirgsel(Msirgsel::CR);
w.set_msirange(MSIRange::RANGE4M);
w.set_msipllen(false);
w.set_msion(true)
});
// Wait until MSI is running
while !RCC.cr().read().msirdy() {}
}
if RCC.cfgr().read().sws() != ClockSrc::MSI {
// Set MSI as a clock source, reset prescalers.
RCC.cfgr().write_value(Cfgr::default());
// Wait for clock switch status bits to change.
while RCC.cfgr().read().sws() != ClockSrc::MSI {}
}
#[cfg(stm32l5)]
crate::pac::PWR.cr1().modify(|w| {
w.set_vos(crate::pac::pwr::vals::Vos::RANGE0);
});
let rtc = config.ls.init();
let msi = config.msi.map(|range| {
// Enable MSI
RCC.cr().write(|w| {
w.set_msirange(range);
w.set_msirgsel(Msirgsel::CR);
w.set_msion(true);
// If LSE is enabled, enable calibration of MSI
w.set_msipllen(config.ls.lse.is_some());
});
while !RCC.cr().read().msirdy() {}
// Enable as clock source for USB, RNG if running at 48 MHz
if range == MSIRange::RANGE48M {}
msirange_to_hertz(range)
});
let hsi16 = config.hsi16.then(|| {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ
});
let hse = config.hse.map(|freq| {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq
});
#[cfg(not(any(stm32l47x, stm32l48x)))]
let hsi48 = config.hsi48.then(|| {
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
Hertz(48_000_000)
});
#[cfg(any(stm32l47x, stm32l48x))]
let hsi48 = None;
let _plls = [
&config.pll,
&config.pllsai1,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
&config.pllsai2,
];
// L4 has shared PLLSRC, PLLM, check it's equal in all PLLs.
#[cfg(all(stm32l4, not(rcc_l4plus)))]
match get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
Err(()) => panic!("Source must be equal across all enabled PLLs."),
Ok(None) => {}
Ok(Some((source, prediv))) => RCC.pllcfgr().write(|w| {
w.set_pllm(prediv);
w.set_pllsrc(source);
}),
};
// L4+ has shared PLLSRC, check it's equal in all PLLs.
#[cfg(any(rcc_l4plus))]
match get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
Err(()) => panic!("Source must be equal across all enabled PLLs."),
Ok(None) => {}
Ok(Some(source)) => RCC.pllcfgr().write(|w| {
w.set_pllsrc(source);
}),
};
let pll_input = PllInput { hse, hsi16, msi };
let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
let sys_clk = match config.mux {
ClockSrc::HSE => hse.unwrap(),
ClockSrc::HSI => hsi16.unwrap(),
ClockSrc::MSI => msi.unwrap(),
#[cfg(rcc_l4)]
ClockSrc::PLL1_P => pll._r.unwrap(),
#[cfg(not(rcc_l4))]
ClockSrc::PLL1_R => pll._r.unwrap(),
};
#[cfg(stm32l4)]
RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
#[cfg(stm32l5)]
RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
let _clk48 = match config.clk48_src {
Clk48Src::HSI48 => hsi48,
Clk48Src::MSI => msi,
Clk48Src::PLLSAI1_Q => pllsai1._q,
Clk48Src::PLL1_Q => pll._q,
};
#[cfg(rcc_l4plus)]
assert!(sys_clk.0 <= 120_000_000);
#[cfg(all(stm32l4, not(rcc_l4plus)))]
assert!(sys_clk.0 <= 80_000_000);
// Set flash wait states
#[cfg(stm32l4)]
FLASH.acr().modify(|w| {
w.set_latency(match sys_clk.0 {
0..=16_000_000 => 0,
0..=32_000_000 => 1,
0..=48_000_000 => 2,
0..=64_000_000 => 3,
_ => 4,
})
});
// VCORE Range 0 (performance), others TODO
#[cfg(stm32l5)]
FLASH.acr().modify(|w| {
w.set_latency(match sys_clk.0 {
0..=20_000_000 => 0,
0..=40_000_000 => 1,
0..=60_000_000 => 2,
0..=80_000_000 => 3,
0..=100_000_000 => 4,
_ => 5,
})
});
RCC.cfgr().modify(|w| {
w.set_sw(config.mux);
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
while RCC.cfgr().read().sws() != config.mux {}
let ahb_freq = sys_clk / config.ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
set_freqs(Clocks {
sys: sys_clk,
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk3: ahb_freq,
pclk1: apb1_freq,
pclk2: apb2_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
#[cfg(rcc_l4)]
hsi: None,
#[cfg(rcc_l4)]
lse: None,
#[cfg(rcc_l4)]
pllsai1_p: None,
#[cfg(rcc_l4)]
pllsai2_p: None,
#[cfg(rcc_l4)]
pll1_p: None,
#[cfg(rcc_l4)]
pll1_q: None,
#[cfg(rcc_l4)]
sai1_extclk: None,
#[cfg(rcc_l4)]
sai2_extclk: None,
rtc,
});
}
fn msirange_to_hertz(range: MSIRange) -> Hertz {
match range {
MSIRange::RANGE100K => Hertz(100_000),
MSIRange::RANGE200K => Hertz(200_000),
MSIRange::RANGE400K => Hertz(400_000),
MSIRange::RANGE800K => Hertz(800_000),
MSIRange::RANGE1M => Hertz(1_000_000),
MSIRange::RANGE2M => Hertz(2_000_000),
MSIRange::RANGE4M => Hertz(4_000_000),
MSIRange::RANGE8M => Hertz(8_000_000),
MSIRange::RANGE16M => Hertz(16_000_000),
MSIRange::RANGE24M => Hertz(24_000_000),
MSIRange::RANGE32M => Hertz(32_000_000),
MSIRange::RANGE48M => Hertz(48_000_000),
_ => unreachable!(),
}
}
#[allow(unused)]
fn get_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> Result<Option<T>, ()> {
let Some(x) = iter.next() else { return Ok(None) };
if !iter.all(|y| y == x) {
return Err(());
}
return Ok(Some(x));
}
struct PllInput {
hsi16: Option<Hertz>,
hse: Option<Hertz>,
msi: Option<Hertz>,
}
#[derive(Default)]
struct PllOutput {
_p: Option<Hertz>,
_q: Option<Hertz>,
_r: Option<Hertz>,
}
#[derive(PartialEq, Eq, Clone, Copy)]
enum PllInstance {
Pll,
Pllsai1,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
Pllsai2,
}
fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
// Disable PLL
match instance {
PllInstance::Pll => {
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
}
PllInstance::Pllsai1 => {
RCC.cr().modify(|w| w.set_pllsai1on(false));
while RCC.cr().read().pllsai1rdy() {}
}
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
PllInstance::Pllsai2 => {
RCC.cr().modify(|w| w.set_pllsai2on(false));
while RCC.cr().read().pllsai2rdy() {}
}
}
let Some(pll) = config else { return PllOutput::default() };
let pll_src = match pll.source {
PLLSource::NONE => panic!("must not select PLL source as NONE"),
PLLSource::HSE => input.hse,
PLLSource::HSI => input.hsi16,
PLLSource::MSI => input.msi,
};
let pll_src = pll_src.unwrap();
let vco_freq = pll_src / pll.prediv * pll.mul;
let p = pll.divp.map(|div| vco_freq / div);
let q = pll.divq.map(|div| vco_freq / div);
let r = pll.divr.map(|div| vco_freq / div);
#[cfg(stm32l5)]
if instance == PllInstance::Pllsai2 {
assert!(q.is_none(), "PLLSAI2_Q is not available on L5");
assert!(r.is_none(), "PLLSAI2_R is not available on L5");
}
macro_rules! write_fields {
($w:ident) => {
$w.set_plln(pll.mul);
if let Some(divp) = pll.divp {
$w.set_pllp(divp);
$w.set_pllpen(true);
}
if let Some(divq) = pll.divq {
$w.set_pllq(divq);
$w.set_pllqen(true);
}
if let Some(divr) = pll.divr {
$w.set_pllr(divr);
$w.set_pllren(true);
}
};
}
match instance {
PllInstance::Pll => RCC.pllcfgr().write(|w| {
w.set_pllm(pll.prediv);
w.set_pllsrc(pll.source);
write_fields!(w);
}),
PllInstance::Pllsai1 => RCC.pllsai1cfgr().write(|w| {
#[cfg(any(rcc_l4plus, stm32l5))]
w.set_pllm(pll.prediv);
#[cfg(stm32l5)]
w.set_pllsrc(pll.source);
write_fields!(w);
}),
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
PllInstance::Pllsai2 => RCC.pllsai2cfgr().write(|w| {
#[cfg(any(rcc_l4plus, stm32l5))]
w.set_pllm(pll.prediv);
#[cfg(stm32l5)]
w.set_pllsrc(pll.source);
write_fields!(w);
}),
}
// Enable PLL
match instance {
PllInstance::Pll => {
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
}
PllInstance::Pllsai1 => {
RCC.cr().modify(|w| w.set_pllsai1on(true));
while !RCC.cr().read().pllsai1rdy() {}
}
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
PllInstance::Pllsai2 => {
RCC.cr().modify(|w| w.set_pllsai2on(true));
while !RCC.cr().read().pllsai2rdy() {}
}
}
PllOutput { _p: p, _q: q, _r: r }
}

443
embassy-stm32/src/rcc/l5.rs
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@ -1,443 +0,0 @@
use stm32_metapac::PWR;
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLClkDiv, PLLSrcDiv, PLLMul, Option<PLL48Div>),
HSE(Hertz),
HSI16,
}
/// MSI Clock Range
///
/// These ranges control the frequency of the MSI. Internally, these ranges map
/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
#[derive(Clone, Copy)]
pub enum MSIRange {
/// Around 100 kHz
Range0,
/// Around 200 kHz
Range1,
/// Around 400 kHz
Range2,
/// Around 800 kHz
Range3,
/// Around 1 MHz
Range4,
/// Around 2 MHz
Range5,
/// Around 4 MHz (reset value)
Range6,
/// Around 8 MHz
Range7,
/// Around 16 MHz
Range8,
/// Around 24 MHz
Range9,
/// Around 32 MHz
Range10,
/// Around 48 MHz
Range11,
}
impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range6
}
}
pub type PLL48Div = PLLClkDiv;
pub type PLLSAI1RDiv = PLLClkDiv;
pub type PLLSAI1QDiv = PLLClkDiv;
pub type PLLSAI1PDiv = PLLClkDiv;
/// PLL divider
#[derive(Clone, Copy)]
pub enum PLLDiv {
Div2,
Div3,
Div4,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI16,
HSE(Hertz),
MSI(MSIRange),
}
seq_macro::seq!(N in 8..=86 {
#[derive(Clone, Copy)]
pub enum PLLMul {
#(
Mul~N,
)*
}
impl From<PLLMul> for u8 {
fn from(val: PLLMul) -> u8 {
match val {
#(
PLLMul::Mul~N => N,
)*
}
}
}
impl PLLMul {
pub fn to_mul(self) -> u32 {
match self {
#(
PLLMul::Mul~N => N,
)*
}
}
}
});
#[derive(Clone, Copy)]
pub enum PLLClkDiv {
Div2,
Div4,
Div6,
Div8,
}
impl PLLClkDiv {
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
(val as u32 + 1) * 2
}
}
impl From<PLLClkDiv> for u8 {
fn from(val: PLLClkDiv) -> u8 {
match val {
PLLClkDiv::Div2 => 0b00,
PLLClkDiv::Div4 => 0b01,
PLLClkDiv::Div6 => 0b10,
PLLClkDiv::Div8 => 0b11,
}
}
}
#[derive(Clone, Copy)]
pub enum PLLSrcDiv {
Div1,
Div2,
Div3,
Div4,
Div5,
Div6,
Div7,
Div8,
}
impl PLLSrcDiv {
pub fn to_div(self) -> u32 {
let val: u8 = self.into();
val as u32 + 1
}
}
impl From<PLLSrcDiv> for u8 {
fn from(val: PLLSrcDiv) -> u8 {
match val {
PLLSrcDiv::Div1 => 0b000,
PLLSrcDiv::Div2 => 0b001,
PLLSrcDiv::Div3 => 0b010,
PLLSrcDiv::Div4 => 0b011,
PLLSrcDiv::Div5 => 0b100,
PLLSrcDiv::Div6 => 0b101,
PLLSrcDiv::Div7 => 0b110,
PLLSrcDiv::Div8 => 0b111,
}
}
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI16,
PLLSource::HSE(_) => Pllsrc::HSE,
PLLSource::MSI(_) => Pllsrc::MSI,
}
}
}
impl From<MSIRange> for Msirange {
fn from(val: MSIRange) -> Msirange {
match val {
MSIRange::Range0 => Msirange::RANGE100K,
MSIRange::Range1 => Msirange::RANGE200K,
MSIRange::Range2 => Msirange::RANGE400K,
MSIRange::Range3 => Msirange::RANGE800K,
MSIRange::Range4 => Msirange::RANGE1M,
MSIRange::Range5 => Msirange::RANGE2M,
MSIRange::Range6 => Msirange::RANGE4M,
MSIRange::Range7 => Msirange::RANGE8M,
MSIRange::Range8 => Msirange::RANGE16M,
MSIRange::Range9 => Msirange::RANGE24M,
MSIRange::Range10 => Msirange::RANGE32M,
MSIRange::Range11 => Msirange::RANGE48M,
}
}
}
impl From<MSIRange> for u32 {
fn from(val: MSIRange) -> u32 {
match val {
MSIRange::Range0 => 100_000,
MSIRange::Range1 => 200_000,
MSIRange::Range2 => 400_000,
MSIRange::Range3 => 800_000,
MSIRange::Range4 => 1_000_000,
MSIRange::Range5 => 2_000_000,
MSIRange::Range6 => 4_000_000,
MSIRange::Range7 => 8_000_000,
MSIRange::Range8 => 16_000_000,
MSIRange::Range9 => 24_000_000,
MSIRange::Range10 => 32_000_000,
MSIRange::Range11 => 48_000_000,
}
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub pllsai1: Option<(
PLLMul,
PLLSrcDiv,
Option<PLLSAI1RDiv>,
Option<PLLSAI1QDiv>,
Option<PLLSAI1PDiv>,
)>,
pub hsi48: bool,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::Range6),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
pllsai1: None,
hsi48: false,
}
}
}
pub(crate) unsafe fn init(config: Config) {
PWR.cr1().modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {
// Enable MSI
RCC.cr().write(|w| {
let bits: Msirange = range.into();
w.set_msirange(bits);
w.set_msipllen(false);
w.set_msirgsel(true);
w.set_msion(true);
});
while !RCC.cr().read().msirdy() {}
// Enable as clock source for USB, RNG if running at 48 MHz
if let MSIRange::Range11 = range {
RCC.ccipr1().modify(|w| {
w.set_clk48msel(0b11);
});
}
(range.into(), Sw::MSI)
}
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0, Sw::HSI16)
}
ClockSrc::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq.0, Sw::HSE)
}
ClockSrc::PLL(src, div, prediv, mul, pll48div) => {
let src_freq = match src {
PLLSource::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
}
PLLSource::HSI16 => {
// Enable HSI
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
PLLSource::MSI(range) => {
// Enable MSI
RCC.cr().write(|w| {
let bits: Msirange = range.into();
w.set_msirange(bits);
w.set_msipllen(false); // should be turned on if LSE is started
w.set_msirgsel(true);
w.set_msion(true);
});
while !RCC.cr().read().msirdy() {}
range.into()
}
};
// Disable PLL
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / div.to_div();
RCC.pllcfgr().write(move |w| {
w.set_plln(mul.into());
w.set_pllm(prediv.into());
w.set_pllr(div.into());
if let Some(pll48div) = pll48div {
w.set_pllq(pll48div.into());
w.set_pllqen(true);
}
w.set_pllsrc(src.into());
});
// Enable as clock source for USB, RNG if PLL48 divisor is provided
if let Some(pll48div) = pll48div {
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / pll48div.to_div();
assert!(freq == 48_000_000);
RCC.ccipr1().modify(|w| {
w.set_clk48msel(0b10);
});
}
if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
RCC.pllsai1cfgr().write(move |w| {
w.set_pllsai1n(mul.into());
w.set_pllsai1m(prediv.into());
if let Some(r_div) = r_div {
w.set_pllsai1r(r_div.into());
w.set_pllsai1ren(true);
}
if let Some(q_div) = q_div {
w.set_pllsai1q(q_div.into());
w.set_pllsai1qen(true);
let freq = (src_freq / prediv.to_div() * mul.to_mul()) / q_div.to_div();
if freq == 48_000_000 {
RCC.ccipr1().modify(|w| {
w.set_clk48msel(0b1);
});
}
}
if let Some(p_div) = p_div {
w.set_pllsai1pdiv(p_div.into());
w.set_pllsai1pen(true);
}
});
RCC.cr().modify(|w| w.set_pllsai1on(true));
}
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
RCC.pllcfgr().modify(|w| w.set_pllren(true));
(freq, Sw::PLL)
}
};
if config.hsi48 {
RCC.crrcr().modify(|w| w.set_hsi48on(true));
while !RCC.crrcr().read().hsi48rdy() {}
// Enable as clock source for USB, RNG and SDMMC
RCC.ccipr1().modify(|w| w.set_clk48msel(0));
}
// Set flash wait states
// VCORE Range 0 (performance), others TODO
FLASH.acr().modify(|w| {
w.set_latency(match sys_clk {
0..=20_000_000 => 0,
0..=40_000_000 => 1,
0..=60_000_000 => 2,
0..=80_000_000 => 3,
0..=100_000_000 => 4,
_ => 5,
})
});
RCC.cfgr().modify(|w| {
w.set_sw(sw);
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: Hpre = pre.into();
let pre = 1 << (pre.to_bits() as u32 - 7);
sys_clk / pre
}
};
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.to_bits() - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
}
};
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
ahb3: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
});
}

46
embassy-stm32/src/rcc/mco.rs
View File

@ -4,14 +4,19 @@ use embassy_hal_internal::into_ref;
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
pub use crate::pac::rcc::vals::{Mco1 as Mco1Source, Mco2 as Mco2Source};
#[cfg(not(stm32f1))]
pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
pub use crate::pac::rcc::vals::Mcosel as McoSource;
#[cfg(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7))]
pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
use crate::pac::RCC;
use crate::{peripherals, Peripheral};
pub(crate) mod sealed {
pub trait McoInstance {
type Source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8);
unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: super::McoPrescaler);
}
}
@ -24,9 +29,15 @@ macro_rules! impl_peri {
impl sealed::McoInstance for peripherals::$peri {
type Source = $source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8) {
RCC.cfgr().modify(|w| {
unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: McoPrescaler) {
#[cfg(not(any(stm32u5, stm32wba)))]
let r = RCC.cfgr();
#[cfg(any(stm32u5, stm32wba))]
let r = RCC.cfgr1();
r.modify(|w| {
w.$set_source(source);
#[cfg(not(stm32f1))]
w.$set_prescaler(prescaler);
});
}
@ -36,8 +47,16 @@ macro_rules! impl_peri {
};
}
impl_peri!(MCO1, Mco1Source, set_mco1, set_mco1pre);
impl_peri!(MCO2, Mco2Source, set_mco2, set_mco2pre);
#[cfg(any(rcc_c0, rcc_g0))]
#[allow(unused_imports)]
use self::{McoSource as Mco1Source, McoSource as Mco2Source};
#[cfg(mco)]
impl_peri!(MCO, McoSource, set_mcosel, set_mcopre);
#[cfg(mco1)]
impl_peri!(MCO1, Mco1Source, set_mco1sel, set_mco1pre);
#[cfg(mco2)]
impl_peri!(MCO2, Mco2Source, set_mco2sel, set_mco2pre);
pub struct Mco<'d, T: McoInstance> {
phantom: PhantomData<&'d mut T>,
@ -45,23 +64,20 @@ pub struct Mco<'d, T: McoInstance> {
impl<'d, T: McoInstance> Mco<'d, T> {
/// Create a new MCO instance.
///
/// `prescaler` must be between 1 and 15.
pub fn new(
_peri: impl Peripheral<P = T> + 'd,
pin: impl Peripheral<P = impl McoPin<T>> + 'd,
source: T::Source,
prescaler: u8,
#[cfg(not(stm32f1))] prescaler: McoPrescaler,
) -> Self {
into_ref!(pin);
assert!(
1 <= prescaler && prescaler <= 15,
"Mco prescaler must be between 1 and 15. Refer to the reference manual for more information."
);
critical_section::with(|_| unsafe {
T::apply_clock_settings(source, prescaler);
T::apply_clock_settings(
source,
#[cfg(not(stm32f1))]
prescaler,
);
pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
pin.set_speed(Speed::VeryHigh);
});

202
embassy-stm32/src/rcc/mod.rs
View File

@ -2,38 +2,33 @@
use core::mem::MaybeUninit;
pub use crate::rcc::bd::RtcClockSource;
use crate::time::Hertz;
pub(crate) mod bd;
mod bus;
#[cfg(any(stm32h5, stm32h7))]
mod bd;
mod mco;
#[cfg(any(stm32h5, stm32h7))]
pub use bd::*;
pub use mco::*;
#[cfg_attr(rcc_f0, path = "f0.rs")]
#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
#[cfg_attr(rcc_f2, path = "f2.rs")]
#[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
#[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
#[cfg_attr(rcc_f7, path = "f7.rs")]
#[cfg_attr(any(rcc_f4, rcc_f410, rcc_f7), path = "f4f7.rs")]
#[cfg_attr(rcc_c0, path = "c0.rs")]
#[cfg_attr(rcc_g0, path = "g0.rs")]
#[cfg_attr(rcc_g4, path = "g4.rs")]
#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab), path = "h.rs")]
#[cfg_attr(rcc_l0, path = "l0.rs")]
#[cfg_attr(rcc_l1, path = "l1.rs")]
#[cfg_attr(rcc_l4, path = "l4.rs")]
#[cfg_attr(rcc_l5, path = "l5.rs")]
#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
#[cfg_attr(any(rcc_l4, rcc_l4plus, rcc_l5), path = "l4l5.rs")]
#[cfg_attr(rcc_u5, path = "u5.rs")]
#[cfg_attr(rcc_wb, path = "wb.rs")]
#[cfg_attr(rcc_wba, path = "wba.rs")]
#[cfg_attr(any(rcc_wl5, rcc_wle), path = "wl.rs")]
mod _version;
pub use _version::*;
#[cfg(feature = "low-power")]
use atomic_polyfill::{AtomicU32, Ordering};
use core::sync::atomic::{AtomicU32, Ordering};
pub use _version::*;
// Model Clock Configuration
//
@ -51,44 +46,107 @@ pub struct Clocks {
pub sys: Hertz,
// APB
pub apb1: Hertz,
pub apb1_tim: Hertz,
pub pclk1: Hertz,
pub pclk1_tim: Hertz,
#[cfg(not(any(rcc_c0, rcc_g0)))]
pub apb2: Hertz,
pub pclk2: Hertz,
#[cfg(not(any(rcc_c0, rcc_g0)))]
pub apb2_tim: Hertz,
#[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5))]
pub apb3: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]
pub apb4: Hertz,
pub pclk2_tim: Hertz,
#[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_u5))]
pub pclk3: Hertz,
#[cfg(any(rcc_h7, rcc_h7rm0433, rcc_h7ab, stm32h5))]
pub pclk4: Hertz,
#[cfg(any(rcc_wba))]
pub apb7: Hertz,
pub pclk7: Hertz,
// AHB
pub ahb1: Hertz,
pub hclk1: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb,
rcc_wba, rcc_wl5, rcc_wle
))]
pub ahb2: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5,
rcc_l4,
rcc_l4plus,
rcc_l5,
rcc_f2,
rcc_f4,
rcc_f410,
rcc_f7,
rcc_h5,
rcc_h50,
rcc_h7,
rcc_h7rm0433,
rcc_h7ab,
rcc_g4,
rcc_u5,
rcc_wb,
rcc_wba,
rcc_wl5,
rcc_wle
))]
pub ahb3: Hertz,
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_wba))]
pub ahb4: Hertz,
#[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
pub pll48: Option<Hertz>,
pub hclk2: Hertz,
#[cfg(any(
rcc_l4,
rcc_l4plus,
rcc_l5,
rcc_f2,
rcc_f4,
rcc_f410,
rcc_f7,
rcc_h5,
rcc_h50,
rcc_h7,
rcc_h7rm0433,
rcc_h7ab,
rcc_u5,
rcc_wb,
rcc_wl5,
rcc_wle
))]
pub hclk3: Hertz,
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
pub hclk4: Hertz,
#[cfg(all(rcc_f4, not(stm32f410)))]
pub plli2s: Option<Hertz>,
pub plli2s1_q: Option<Hertz>,
#[cfg(all(rcc_f4, not(stm32f410)))]
pub plli2s1_r: Option<Hertz>,
#[cfg(rcc_l4)]
pub pllsai1_p: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai: Option<Hertz>,
pub pllsai1_q: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai1_r: Option<Hertz>,
#[cfg(rcc_l4)]
pub pllsai2_p: Option<Hertz>,
#[cfg(any(rcc_f1, rcc_f100, rcc_f1cl, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_f3, rcc_g4))]
#[cfg(any(stm32g4, rcc_l4))]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_l4))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_r: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_r: Option<Hertz>,
#[cfg(any(
rcc_f1,
rcc_f100,
rcc_f1cl,
rcc_h5,
rcc_h50,
rcc_h7,
rcc_h7rm0433,
rcc_h7ab,
rcc_f3,
rcc_g4
))]
pub adc: Option<Hertz>,
#[cfg(any(rcc_f3, rcc_g4))]
@ -97,13 +155,33 @@ pub struct Clocks {
#[cfg(stm32f334)]
pub hrtim: Option<Hertz>,
#[cfg(any(rcc_wb, rcc_f4, rcc_f410, rcc_f7))]
/// Set only if the lsi or lse is configured, indicates stop is supported
pub rtc: Option<Hertz>,
#[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
/// Set if the hse is configured, indicates stop is not supported
pub rtc_hse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
pub hsi: Option<Hertz>,
#[cfg(stm32h5)]
pub hsi48: Option<Hertz>,
#[cfg(stm32h5)]
pub lsi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
pub lse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub hse: Option<Hertz>,
#[cfg(stm32h5)]
pub audioclk: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub per: Option<Hertz>,
#[cfg(stm32h7)]
pub rcc_pclk_d3: Option<Hertz>,
#[cfg(rcc_l4)]
pub sai1_extclk: Option<Hertz>,
#[cfg(rcc_l4)]
pub sai2_extclk: Option<Hertz>,
}
#[cfg(feature = "low-power")]
@ -111,20 +189,22 @@ static CLOCK_REFCOUNT: AtomicU32 = AtomicU32::new(0);
#[cfg(feature = "low-power")]
pub fn low_power_ready() -> bool {
trace!("clock refcount: {}", CLOCK_REFCOUNT.load(Ordering::SeqCst));
// trace!("clock refcount: {}", CLOCK_REFCOUNT.load(Ordering::SeqCst));
CLOCK_REFCOUNT.load(Ordering::SeqCst) == 0
}
#[cfg(feature = "low-power")]
pub(crate) fn clock_refcount_add() {
pub(crate) fn clock_refcount_add(_cs: critical_section::CriticalSection) {
// We don't check for overflow because constructing more than u32 peripherals is unlikely
CLOCK_REFCOUNT.fetch_add(1, Ordering::Relaxed);
let n = CLOCK_REFCOUNT.load(Ordering::Relaxed);
CLOCK_REFCOUNT.store(n + 1, Ordering::Relaxed);
}
#[cfg(feature = "low-power")]
pub(crate) fn clock_refcount_sub() {
assert!(CLOCK_REFCOUNT.fetch_sub(1, Ordering::Relaxed) != 0);
pub(crate) fn clock_refcount_sub(_cs: critical_section::CriticalSection) {
let n = CLOCK_REFCOUNT.load(Ordering::Relaxed);
assert!(n != 0);
CLOCK_REFCOUNT.store(n - 1, Ordering::Relaxed);
}
/// Frozen clock frequencies
@ -132,14 +212,6 @@ pub(crate) fn clock_refcount_sub() {
/// The existence of this value indicates that the clock configuration can no longer be changed
static mut CLOCK_FREQS: MaybeUninit<Clocks> = MaybeUninit::uninit();
#[cfg(stm32wb)]
/// RCC initialization function
pub(crate) unsafe fn init(config: Config) {
set_freqs(compute_clocks(&config));
configure_clocks(&config);
}
/// Sets the clock frequencies
///
/// Safety: Sets a mutable global.
@ -159,11 +231,19 @@ pub mod low_level {
}
pub(crate) mod sealed {
use critical_section::CriticalSection;
pub trait RccPeripheral {
fn frequency() -> crate::time::Hertz;
fn reset();
fn enable();
fn disable();
fn enable_and_reset_with_cs(cs: CriticalSection);
fn disable_with_cs(cs: CriticalSection);
fn enable_and_reset() {
critical_section::with(|cs| Self::enable_and_reset_with_cs(cs))
}
fn disable() {
critical_section::with(|cs| Self::disable_with_cs(cs))
}
}
}

569
embassy-stm32/src/rcc/u5.rs
View File

@ -1,124 +1,102 @@
use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllsrc, Sw};
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::pac::{FLASH, RCC};
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler};
use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
pub use crate::pac::pwr::vals::Vos as VoltageScale;
#[derive(Copy, Clone)]
pub enum ClockSrc {
MSI(MSIRange),
/// Use an internal medium speed oscillator (MSIS) as the system clock.
MSI(Msirange),
/// Use the external high speed clock as the system clock.
///
/// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
/// never exceed 50 MHz.
HSE(Hertz),
/// Use the 16 MHz internal high speed oscillator as the system clock.
HSI16,
PLL1R(PllSrc, PllM, PllN, PllClkDiv),
/// Use PLL1 as the system clock.
PLL1R(PllConfig),
}
#[derive(Clone, Copy, Debug)]
impl Default for ClockSrc {
fn default() -> Self {
// The default system clock source is MSIS @ 4 MHz, per RM0456 § 11.4.9
ClockSrc::MSI(Msirange::RANGE_4MHZ)
}
}
#[derive(Clone, Copy)]
pub struct PllConfig {
/// The clock source for the PLL.
pub source: PllSrc,
/// The PLL prescaler.
///
/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
pub m: Pllm,
/// The PLL multiplier.
///
/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
pub n: Plln,
/// The divider for the R output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
pub r: Plldiv,
}
impl PllConfig {
/// A configuration for HSI16 / 1 * 10 / 1 = 160 MHz
pub const fn hsi16_160mhz() -> Self {
PllConfig {
source: PllSrc::HSI16,
m: Pllm::DIV1,
n: Plln::MUL10,
r: Plldiv::DIV1,
}
}
/// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
pub const fn msis_160mhz() -> Self {
PllConfig {
source: PllSrc::MSIS(Msirange::RANGE_48MHZ),
m: Pllm::DIV3,
n: Plln::MUL10,
r: Plldiv::DIV1,
}
}
}
#[derive(Clone, Copy)]
pub enum PllSrc {
MSI(MSIRange),
/// Use an internal medium speed oscillator as the PLL source.
MSIS(Msirange),
/// Use the external high speed clock as the system PLL source.
///
/// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
/// never exceed 50 MHz.
HSE(Hertz),
/// Use the 16 MHz internal high speed oscillator as the PLL source.
HSI16,
}
impl Into<Pllsrc> for PllSrc {
fn into(self) -> Pllsrc {
match self {
PllSrc::MSI(..) => Pllsrc::MSIS,
PllSrc::MSIS(..) => Pllsrc::MSIS,
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI16 => Pllsrc::HSI16,
}
}
}
seq_macro::seq!(N in 2..=128 {
#[derive(Copy, Clone, Debug)]
pub enum PllClkDiv {
NotDivided,
#(
Div~N = (N-1),
)*
}
impl PllClkDiv {
fn to_div(&self) -> u8 {
match self {
PllClkDiv::NotDivided => 1,
#(
PllClkDiv::Div~N => N + 1,
)*
}
}
}
});
impl Into<u8> for PllClkDiv {
fn into(self) -> u8 {
(self as u8) + 1
}
}
seq_macro::seq!(N in 4..=512 {
#[derive(Copy, Clone, Debug)]
pub enum PllN {
NotMultiplied,
#(
Mul~N = N-1,
)*
}
impl PllN {
fn to_mul(&self) -> u16 {
match self {
PllN::NotMultiplied => 1,
#(
PllN::Mul~N => N + 1,
)*
}
}
}
});
impl Into<u16> for PllN {
fn into(self) -> u16 {
(self as u16) + 1
}
}
// Pre-division
#[derive(Copy, Clone, Debug)]
pub enum PllM {
NotDivided = 0b0000,
Div2 = 0b0001,
Div3 = 0b0010,
Div4 = 0b0011,
Div5 = 0b0100,
Div6 = 0b0101,
Div7 = 0b0110,
Div8 = 0b0111,
Div9 = 0b1000,
Div10 = 0b1001,
Div11 = 0b1010,
Div12 = 0b1011,
Div13 = 0b1100,
Div14 = 0b1101,
Div15 = 0b1110,
Div16 = 0b1111,
}
impl Into<Pllm> for PllM {
fn into(self) -> Pllm {
Pllm::from_bits(self as u8)
}
}
impl Into<Sw> for ClockSrc {
fn into(self) -> Sw {
match self {
@ -130,62 +108,6 @@ impl Into<Sw> for ClockSrc {
}
}
#[derive(Debug, Copy, Clone)]
pub enum MSIRange {
Range48mhz = 48_000_000,
Range24mhz = 24_000_000,
Range16mhz = 16_000_000,
Range12mhz = 12_000_000,
Range4mhz = 4_000_000,
Range2mhz = 2_000_000,
Range1_33mhz = 1_330_000,
Range1mhz = 1_000_000,
Range3_072mhz = 3_072_000,
Range1_536mhz = 1_536_000,
Range1_024mhz = 1_024_000,
Range768khz = 768_000,
Range400khz = 400_000,
Range200khz = 200_000,
Range133khz = 133_000,
Range100khz = 100_000,
}
impl Into<u32> for MSIRange {
fn into(self) -> u32 {
self as u32
}
}
impl Into<Msirange> for MSIRange {
fn into(self) -> Msirange {
match self {
MSIRange::Range48mhz => Msirange::RANGE_48MHZ,
MSIRange::Range24mhz => Msirange::RANGE_24MHZ,
MSIRange::Range16mhz => Msirange::RANGE_16MHZ,
MSIRange::Range12mhz => Msirange::RANGE_12MHZ,
MSIRange::Range4mhz => Msirange::RANGE_4MHZ,
MSIRange::Range2mhz => Msirange::RANGE_2MHZ,
MSIRange::Range1_33mhz => Msirange::RANGE_1_33MHZ,
MSIRange::Range1mhz => Msirange::RANGE_1MHZ,
MSIRange::Range3_072mhz => Msirange::RANGE_3_072MHZ,
MSIRange::Range1_536mhz => Msirange::RANGE_1_536MHZ,
MSIRange::Range1_024mhz => Msirange::RANGE_1_024MHZ,
MSIRange::Range768khz => Msirange::RANGE_768KHZ,
MSIRange::Range400khz => Msirange::RANGE_400KHZ,
MSIRange::Range200khz => Msirange::RANGE_200KHZ,
MSIRange::Range133khz => Msirange::RANGE_133KHZ,
MSIRange::Range100khz => Msirange::RANGE_100KHZ,
}
}
}
impl Default for MSIRange {
fn default() -> Self {
MSIRange::Range4mhz
}
}
#[derive(Copy, Clone)]
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
@ -193,90 +115,209 @@ pub struct Config {
pub apb2_pre: APBPrescaler,
pub apb3_pre: APBPrescaler,
pub hsi48: bool,
/// The voltage range influences the maximum clock frequencies for different parts of the
/// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
/// exceeding 55 MHz require at least `RANGE2`.
///
/// See RM0456 § 10.5.4 for a general overview and § 11.4.10 for clock source frequency limits.
pub voltage_range: VoltageScale,
pub ls: super::LsConfig,
}
impl Config {
unsafe fn init_hsi16(&self) -> Hertz {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ
}
unsafe fn init_hse(&self, frequency: Hertz) -> Hertz {
// Check frequency limits per RM456 § 11.4.10
match self.voltage_range {
VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
assert!(frequency.0 <= 50_000_000);
}
VoltageScale::RANGE4 => {
assert!(frequency.0 <= 25_000_000);
}
}
// Enable HSE, and wait for it to stabilize
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
frequency
}
unsafe fn init_msis(&self, range: Msirange) -> Hertz {
// Check MSI output per RM0456 § 11.4.10
match self.voltage_range {
VoltageScale::RANGE4 => {
assert!(msirange_to_hertz(range).0 <= 24_000_000);
}
_ => {}
}
// RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
loop {
let cr = RCC.cr().read();
if cr.msison() == false || cr.msisrdy() == true {
break;
}
}
RCC.icscr1().modify(|w| {
w.set_msisrange(range);
w.set_msirgsel(Msirgsel::RCC_ICSCR1);
});
RCC.cr().write(|w| {
w.set_msipllen(false);
w.set_msison(true);
});
while !RCC.cr().read().msisrdy() {}
msirange_to_hertz(range)
}
}
impl Default for Config {
fn default() -> Self {
Self {
mux: ClockSrc::MSI(MSIRange::default()),
mux: ClockSrc::default(),
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
apb3_pre: APBPrescaler::DIV1,
hsi48: false,
hsi48: true,
voltage_range: VoltageScale::RANGE3,
ls: Default::default(),
}
}
}
pub(crate) unsafe fn init(config: Config) {
// Ensure PWR peripheral clock is enabled
RCC.ahb3enr().modify(|w| {
w.set_pwren(true);
});
RCC.ahb3enr().read(); // synchronize
// Set the requested power mode
PWR.vosr().modify(|w| {
w.set_vos(config.voltage_range);
});
while !PWR.vosr().read().vosrdy() {}
let sys_clk = match config.mux {
ClockSrc::MSI(range) => {
RCC.icscr1().modify(|w| {
let bits: Msirange = range.into();
w.set_msisrange(bits);
w.set_msirgsel(Msirgsel::RCC_ICSCR1);
});
RCC.cr().write(|w| {
w.set_msipllen(false);
w.set_msison(true);
});
while !RCC.cr().read().msisrdy() {}
range.into()
}
ClockSrc::HSE(freq) => {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
}
ClockSrc::HSI16 => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
ClockSrc::PLL1R(src, m, n, div) => {
let freq = match src {
PllSrc::MSI(_) => {
// TODO: enable MSI
MSIRange::default().into()
}
PllSrc::HSE(hertz) => {
// TODO: enable HSE
hertz.0
}
PllSrc::HSI16 => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
ClockSrc::MSI(range) => config.init_msis(range),
ClockSrc::HSE(freq) => config.init_hse(freq),
ClockSrc::HSI16 => config.init_hsi16(),
ClockSrc::PLL1R(pll) => {
// Configure the PLL source
let source_clk = match pll.source {
PllSrc::MSIS(range) => config.init_msis(range),
PllSrc::HSE(hertz) => config.init_hse(hertz),
PllSrc::HSI16 => config.init_hsi16(),
};
// disable
// Calculate the reference clock, which is the source divided by m
let reference_clk = source_clk / pll.m;
// Check limits per RM0456 § 11.4.6
assert!(Hertz::mhz(4) <= reference_clk && reference_clk <= Hertz::mhz(16));
// Calculate the PLL1 VCO clock and PLL1 R output clock
let pll1_clk = reference_clk * pll.n;
let pll1r_clk = pll1_clk / pll.r;
// Check system clock per RM0456 § 11.4.9
assert!(pll1r_clk <= Hertz::mhz(160));
// Check PLL clocks per RM0456 § 11.4.10
match config.voltage_range {
VoltageScale::RANGE1 => {
assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
assert!(pll1r_clk <= Hertz::mhz(208));
}
VoltageScale::RANGE2 => {
assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
assert!(pll1r_clk <= Hertz::mhz(110));
}
VoltageScale::RANGE3 => {
assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(330));
assert!(pll1r_clk <= Hertz::mhz(55));
}
VoltageScale::RANGE4 => {
panic!("PLL is unavailable in voltage range 4");
}
}
// § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
// value that results in an output between 4 and 16 MHz for the PWR EPOD boost
let mboost = if pll1r_clk >= Hertz::mhz(55) {
// source_clk can be up to 50 MHz, so there's just a few cases:
if source_clk > Hertz::mhz(32) {
// Divide by 4, giving EPOD 8-12.5 MHz
Pllmboost::DIV4
} else if source_clk > Hertz::mhz(16) {
// Divide by 2, giving EPOD 8-16 MHz
Pllmboost::DIV2
} else {
// Bypass, giving EPOD 4-16 MHz
Pllmboost::DIV1
}
} else {
// Nothing to do
Pllmboost::DIV1
};
// Disable the PLL, and wait for it to disable
RCC.cr().modify(|w| w.set_pllon(0, false));
while RCC.cr().read().pllrdy(0) {}
let vco = freq * n as u8 as u32;
let pll_ck = vco / (div as u8 as u32 + 1);
// Configure the PLL
RCC.pll1cfgr().write(|w| {
w.set_pllm(m.into());
w.set_pllsrc(src.into());
// Configure PLL1 source and prescaler
w.set_pllsrc(pll.source.into());
w.set_pllm(pll.m);
// Configure PLL1 input frequncy range
let input_range = if reference_clk <= Hertz::mhz(8) {
Pllrge::FREQ_4TO8MHZ
} else {
Pllrge::FREQ_8TO16MHZ
};
w.set_pllrge(input_range);
// Set the prescaler for PWR EPOD
w.set_pllmboost(mboost);
// Enable PLL1R output
w.set_pllren(true);
});
// Configure the PLL divisors
RCC.pll1divr().modify(|w| {
w.set_pllr(div.to_div());
w.set_plln(n.to_mul());
// Set the VCO multiplier
w.set_plln(pll.n);
// Set the R output divisor
w.set_pllr(pll.r);
});
// Enable PLL
// Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
if pll1r_clk >= Hertz::mhz(55) {
// Enable the booster
PWR.vosr().modify(|w| {
w.set_boosten(true);
});
while !PWR.vosr().read().boostrdy() {}
}
// Enable the PLL
RCC.cr().modify(|w| w.set_pllon(0, true));
while !RCC.cr().read().pllrdy(0) {}
pll_ck
pll1r_clk
}
};
@ -285,20 +326,18 @@ pub(crate) unsafe fn init(config: Config) {
while !RCC.cr().read().hsi48rdy() {}
}
// TODO make configurable
let power_vos = VoltageScale::RANGE3;
// states and programming delay
let wait_states = match power_vos {
// The clock source is ready
// Calculate and set the flash wait states
let wait_states = match config.voltage_range {
// VOS 1 range VCORE 1.26V - 1.40V
VoltageScale::RANGE1 => {
if sys_clk < 32_000_000 {
if sys_clk.0 < 32_000_000 {
0
} else if sys_clk < 64_000_000 {
} else if sys_clk.0 < 64_000_000 {
1
} else if sys_clk < 96_000_000 {
} else if sys_clk.0 < 96_000_000 {
2
} else if sys_clk < 128_000_000 {
} else if sys_clk.0 < 128_000_000 {
3
} else {
4
@ -306,11 +345,11 @@ pub(crate) unsafe fn init(config: Config) {
}
// VOS 2 range VCORE 1.15V - 1.26V
VoltageScale::RANGE2 => {
if sys_clk < 30_000_000 {
if sys_clk.0 < 30_000_000 {
0
} else if sys_clk < 60_000_000 {
} else if sys_clk.0 < 60_000_000 {
1
} else if sys_clk < 90_000_000 {
} else if sys_clk.0 < 90_000_000 {
2
} else {
3
@ -318,9 +357,9 @@ pub(crate) unsafe fn init(config: Config) {
}
// VOS 3 range VCORE 1.05V - 1.15V
VoltageScale::RANGE3 => {
if sys_clk < 24_000_000 {
if sys_clk.0 < 24_000_000 {
0
} else if sys_clk < 48_000_000 {
} else if sys_clk.0 < 48_000_000 {
1
} else {
2
@ -328,80 +367,104 @@ pub(crate) unsafe fn init(config: Config) {
}
// VOS 4 range VCORE 0.95V - 1.05V
VoltageScale::RANGE4 => {
if sys_clk < 12_000_000 {
if sys_clk.0 < 12_000_000 {
0
} else {
1
}
}
};
FLASH.acr().modify(|w| {
w.set_latency(wait_states);
});
// Switch the system clock source
RCC.cfgr1().modify(|w| {
w.set_sw(config.mux.into());
});
// RM0456 § 11.4.9 specifies maximum bus frequencies per voltage range, but the maximum bus
// frequency for each voltage range exactly matches the maximum permitted PLL output frequency.
// Given that:
//
// 1. Any bus frequency can never exceed the system clock frequency;
// 2. We checked the PLL output frequency if we're using it as a system clock;
// 3. The maximum HSE frequencies at each voltage range are lower than the bus limits, and
// we checked the HSE frequency if configured as a system clock; and
// 4. The maximum frequencies from the other clock sources are lower than the lowest bus
// frequency limit
//
// ...then we do not need to perform additional bus-related frequency checks.
// Configure the bus prescalers
RCC.cfgr2().modify(|w| {
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
RCC.cfgr3().modify(|w| {
w.set_ppre3(config.apb3_pre.into());
w.set_ppre3(config.apb3_pre);
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1 << (pre as u32 - 7);
sys_clk / pre
}
};
let ahb_freq = sys_clk / config.ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
ahb3: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb3: Hertz(apb3_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
sys: sys_clk,
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk3: ahb_freq,
pclk1: apb1_freq,
pclk2: apb2_freq,
pclk3: apb3_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
rtc,
});
}
fn msirange_to_hertz(range: Msirange) -> Hertz {
match range {
Msirange::RANGE_48MHZ => Hertz(48_000_000),
Msirange::RANGE_24MHZ => Hertz(24_000_000),
Msirange::RANGE_16MHZ => Hertz(16_000_000),
Msirange::RANGE_12MHZ => Hertz(12_000_000),
Msirange::RANGE_4MHZ => Hertz(4_000_000),
Msirange::RANGE_2MHZ => Hertz(2_000_000),
Msirange::RANGE_1_33MHZ => Hertz(1_330_000),
Msirange::RANGE_1MHZ => Hertz(1_000_000),
Msirange::RANGE_3_072MHZ => Hertz(3_072_000),
Msirange::RANGE_1_536MHZ => Hertz(1_536_000),
Msirange::RANGE_1_024MHZ => Hertz(1_024_000),
Msirange::RANGE_768KHZ => Hertz(768_000),
Msirange::RANGE_400KHZ => Hertz(400_000),
Msirange::RANGE_200KHZ => Hertz(200_000),
Msirange::RANGE_133KHZ => Hertz(133_000),
Msirange::RANGE_100KHZ => Hertz(100_000),
}
}

256
embassy-stm32/src/rcc/wb.rs
View File

@ -1,118 +1,46 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::Clocks;
use crate::time::{khz, mhz, Hertz};
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
/// and with the addition of the init function to configure a system clock.
/// Only the basic setup using the HSE and HSI clocks are supported as of now.
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Hsepre as HsePrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Pllsrc as PllSource,
Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::rcc::{set_freqs, Clocks};
use crate::time::{mhz, Hertz};
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
#[derive(Clone, Copy)]
pub enum HsePrescaler {
NotDivided,
Div2,
}
impl From<HsePrescaler> for bool {
fn from(value: HsePrescaler) -> Self {
match value {
HsePrescaler::NotDivided => false,
HsePrescaler::Div2 => true,
}
}
}
pub struct Hse {
pub prediv: HsePrescaler,
pub frequency: Hertz,
}
/// System clock mux source
#[derive(Clone, Copy, PartialEq)]
pub enum Sysclk {
/// MSI selected as sysclk
MSI,
/// HSI selected as sysclk
HSI,
/// HSE selected as sysclk
HSE,
/// PLL selected as sysclk
Pll,
}
impl From<Sysclk> for u8 {
fn from(value: Sysclk) -> Self {
match value {
Sysclk::MSI => 0b00,
Sysclk::HSI => 0b01,
Sysclk::HSE => 0b10,
Sysclk::Pll => 0b11,
}
}
}
#[derive(Clone, Copy, PartialEq)]
pub enum PllSource {
Hsi,
Msi,
Hse,
}
impl From<PllSource> for u8 {
fn from(value: PllSource) -> Self {
match value {
PllSource::Msi => 0b01,
PllSource::Hsi => 0b10,
PllSource::Hse => 0b11,
}
}
}
pub enum Pll48Source {
PllSai,
Pll,
Msi,
Hsi48,
}
pub struct PllMux {
/// Source clock selection.
pub source: PllSource,
/// PLL pre-divider (DIVM). Must be between 1 and 63.
pub prediv: u8,
pub prediv: Pllm,
}
pub struct Pll {
/// PLL multiplication factor. Must be between 4 and 512.
pub mul: u16,
pub mul: Plln,
/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
/// On PLL1, it must be even (in particular, it cannot be 1.)
pub divp: Option<u16>,
pub divp: Option<Pllp>,
/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
pub divq: Option<u16>,
pub divq: Option<Pllq>,
/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
pub divr: Option<u16>,
pub divr: Option<Pllr>,
}
/// Clocks configutation
pub struct Config {
pub hse: Option<Hse>,
pub lse: Option<Hertz>,
pub lsi: bool,
pub sys: Sysclk,
pub mux: Option<PllMux>,
pub pll48: Option<Pll48Source>,
pub rtc: Option<RtcClockSource>,
pub hsi48: bool,
pub pll: Option<Pll>,
pub pllsai: Option<Pll>,
@ -122,28 +50,29 @@ pub struct Config {
pub ahb3_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub ls: super::LsConfig,
}
pub const WPAN_DEFAULT: Config = Config {
hse: Some(Hse {
frequency: mhz(32),
prediv: HsePrescaler::NotDivided,
prediv: HsePrescaler::DIV1,
}),
lse: Some(khz(32)),
sys: Sysclk::Pll,
sys: Sysclk::PLL,
mux: Some(PllMux {
source: PllSource::Hse,
prediv: 2,
source: PllSource::HSE,
prediv: Pllm::DIV2,
}),
pll48: None,
rtc: Some(RtcClockSource::LSE),
lsi: false,
hsi48: true,
ls: super::LsConfig::default_lse(),
pll: Some(Pll {
mul: 12,
divp: Some(3),
divq: Some(4),
divr: Some(3),
mul: Plln::MUL12,
divp: Some(Pllp::DIV3),
divq: Some(Pllq::DIV4),
divr: Some(Pllr::DIV3),
}),
pllsai: None,
@ -159,14 +88,13 @@ impl Default for Config {
fn default() -> Config {
Config {
hse: None,
lse: None,
sys: Sysclk::HSI,
sys: Sysclk::HSI16,
mux: None,
pll48: None,
pll: None,
pllsai: None,
rtc: None,
lsi: false,
hsi48: true,
ls: Default::default(),
ahb1_pre: AHBPrescaler::DIV1,
ahb2_pre: AHBPrescaler::DIV1,
@ -177,16 +105,15 @@ impl Default for Config {
}
}
pub(crate) fn compute_clocks(config: &Config) -> Clocks {
let hse_clk = config.hse.as_ref().map(|hse| match hse.prediv {
HsePrescaler::NotDivided => hse.frequency,
HsePrescaler::Div2 => hse.frequency / 2u32,
});
#[cfg(stm32wb)]
/// RCC initialization function
pub(crate) unsafe fn init(config: Config) {
let hse_clk = config.hse.as_ref().map(|hse| hse.frequency / hse.prediv);
let mux_clk = config.mux.as_ref().map(|pll_mux| {
(match pll_mux.source {
PllSource::Hse => hse_clk.unwrap(),
PllSource::Hsi => HSI_FREQ,
PllSource::HSE => hse_clk.unwrap(),
PllSource::HSI16 => HSI_FREQ,
_ => unreachable!(),
} / pll_mux.prediv)
});
@ -206,44 +133,19 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
let sys_clk = match config.sys {
Sysclk::HSE => hse_clk.unwrap(),
Sysclk::HSI => HSI_FREQ,
Sysclk::Pll => pll_r.unwrap(),
Sysclk::HSI16 => HSI_FREQ,
Sysclk::PLL => pll_r.unwrap(),
_ => unreachable!(),
};
let ahb1_clk = match config.ahb1_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1u32 << (pre as u32 - 7);
sys_clk / pre
}
};
let ahb2_clk = match config.ahb2_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1u32 << (pre as u32 - 7);
sys_clk / pre
}
};
let ahb3_clk = match config.ahb3_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1u32 << (pre as u32 - 7);
sys_clk / pre
}
};
let ahb1_clk = sys_clk / config.ahb1_pre;
let ahb2_clk = sys_clk / config.ahb2_pre;
let ahb3_clk = sys_clk / config.ahb3_pre;
let (apb1_clk, apb1_tim_clk) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb1_clk / pre as u32;
let freq = ahb1_clk / pre;
(freq, freq * 2u32)
}
};
@ -251,43 +153,20 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
let (apb2_clk, apb2_tim_clk) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb1_clk / pre as u32;
let freq = ahb1_clk / pre;
(freq, freq * 2u32)
}
};
let rtc_clk = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ),
Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
_ => None,
};
Clocks {
sys: sys_clk,
ahb1: ahb1_clk,
ahb2: ahb2_clk,
ahb3: ahb3_clk,
apb1: apb1_clk,
apb2: apb2_clk,
apb1_tim: apb1_tim_clk,
apb2_tim: apb2_tim_clk,
rtc: rtc_clk,
rtc_hse: None,
}
}
pub(crate) fn configure_clocks(config: &Config) {
let rcc = crate::pac::RCC;
let needs_hsi = if let Some(pll_mux) = &config.mux {
pll_mux.source == PllSource::Hsi
pll_mux.source == PllSource::HSI16
} else {
false
};
if needs_hsi || config.sys == Sysclk::HSI {
if needs_hsi || config.sys == Sysclk::HSI16 {
rcc.cr().modify(|w| {
w.set_hsion(true);
});
@ -297,16 +176,12 @@ pub(crate) fn configure_clocks(config: &Config) {
rcc.cfgr().modify(|w| w.set_stopwuck(true));
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = config.ls.init();
match &config.hse {
Some(hse) => {
rcc.cr().modify(|w| {
w.set_hsepre(hse.prediv.into());
w.set_hsepre(hse.prediv);
w.set_hseon(true);
});
@ -328,18 +203,18 @@ pub(crate) fn configure_clocks(config: &Config) {
match &config.pll {
Some(pll) => {
rcc.pllcfgr().modify(|w| {
w.set_plln(pll.mul as u8);
w.set_plln(pll.mul);
pll.divp.map(|divp| {
w.set_pllpen(true);
w.set_pllp((divp - 1) as u8)
w.set_pllp(divp)
});
pll.divq.map(|divq| {
w.set_pllqen(true);
w.set_pllq((divq - 1) as u8)
w.set_pllq(divq)
});
pll.divr.map(|divr| {
// w.set_pllren(true);
w.set_pllr((divr - 1) as u8);
w.set_pllren(true);
w.set_pllr(divr);
});
});
@ -350,15 +225,34 @@ pub(crate) fn configure_clocks(config: &Config) {
_ => {}
}
let _hsi48 = config.hsi48.then(|| {
rcc.crrcr().modify(|w| w.set_hsi48on(true));
while !rcc.crrcr().read().hsi48rdy() {}
Hertz(48_000_000)
});
rcc.cfgr().modify(|w| {
w.set_sw(config.sys.into());
w.set_hpre(config.ahb1_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_hpre(config.ahb1_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
rcc.extcfgr().modify(|w| {
w.set_c2hpre(config.ahb2_pre.into());
w.set_shdhpre(config.ahb3_pre.into());
w.set_c2hpre(config.ahb2_pre);
w.set_shdhpre(config.ahb3_pre);
});
set_freqs(Clocks {
sys: sys_clk,
hclk1: ahb1_clk,
hclk2: ahb2_clk,
hclk3: ahb3_clk,
pclk1: apb1_clk,
pclk2: apb2_clk,
pclk1_tim: apb1_tim_clk,
pclk2_tim: apb2_tim_clk,
rtc,
})
}

37
embassy-stm32/src/rcc/wba.rs
View File

@ -7,9 +7,6 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
pub use crate::pac::pwr::vals::Vos as VoltageScale;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
@ -28,7 +25,7 @@ pub enum PllSrc {
impl Into<Pllsrc> for PllSrc {
fn into(self) -> Pllsrc {
match self {
PllSrc::HSE(..) => Pllsrc::HSE32,
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI16 => Pllsrc::HSI16,
}
}
@ -37,19 +34,19 @@ impl Into<Pllsrc> for PllSrc {
impl Into<Sw> for ClockSrc {
fn into(self) -> Sw {
match self {
ClockSrc::HSE(..) => Sw::HSE32,
ClockSrc::HSE(..) => Sw::HSE,
ClockSrc::HSI16 => Sw::HSI16,
}
}
}
#[derive(Copy, Clone)]
pub struct Config {
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb7_pre: APBPrescaler,
pub ls: super::LsConfig,
}
impl Default for Config {
@ -60,6 +57,7 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
apb7_pre: APBPrescaler::DIV1,
ls: Default::default(),
}
}
}
@ -108,13 +106,13 @@ pub(crate) unsafe fn init(config: Config) {
});
RCC.cfgr2().modify(|w| {
w.set_hpre(config.ahb_pre.into());
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
RCC.cfgr3().modify(|w| {
w.set_ppre7(config.apb7_pre.into());
w.set_ppre7(config.apb7_pre);
});
let ahb_freq = sys_clk / config.ahb_pre;
@ -140,15 +138,18 @@ pub(crate) unsafe fn init(config: Config) {
}
};
let rtc = config.ls.init();
set_freqs(Clocks {
sys: sys_clk,
ahb1: ahb_freq,
ahb2: ahb_freq,
ahb4: ahb_freq,
apb1: apb1_freq,
apb2: apb2_freq,
apb7: apb7_freq,
apb1_tim: apb1_tim_freq,
apb2_tim: apb2_tim_freq,
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk4: ahb_freq,
pclk1: apb1_freq,
pclk2: apb2_freq,
pclk7: apb7_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
rtc,
});
}

264
embassy-stm32/src/rcc/wl.rs
View File

@ -1,136 +1,27 @@
pub use super::bus::{AHBPrescaler, APBPrescaler};
pub use crate::pac::pwr::vals::Vos as VoltageScale;
use crate::pac::rcc::vals::Adcsel;
use crate::pac::rcc::vals::Sw;
pub use crate::pac::rcc::vals::{
Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm, Plln, Pllp, Pllq, Pllr,
Pllsrc as PllSource, Ppre as APBPrescaler,
};
use crate::pac::{FLASH, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
/// and with the addition of the init function to configure a system clock.
/// Only the basic setup using the HSE and HSI clocks are supported as of now.
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// HSE32 speed
pub const HSE32_FREQ: Hertz = Hertz(32_000_000);
/// HSE speed
pub const HSE_FREQ: Hertz = Hertz(32_000_000);
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
MSI(MSIRange),
HSE32,
HSE,
HSI16,
}
#[derive(Clone, Copy, PartialOrd, PartialEq)]
pub enum MSIRange {
/// Around 100 kHz
Range0,
/// Around 200 kHz
Range1,
/// Around 400 kHz
Range2,
/// Around 800 kHz
Range3,
/// Around 1 MHz
Range4,
/// Around 2 MHz
Range5,
/// Around 4 MHz (reset value)
Range6,
/// Around 8 MHz
Range7,
/// Around 16 MHz
Range8,
/// Around 24 MHz
Range9,
/// Around 32 MHz
Range10,
/// Around 48 MHz
Range11,
}
impl MSIRange {
fn freq(&self) -> u32 {
match self {
MSIRange::Range0 => 100_000,
MSIRange::Range1 => 200_000,
MSIRange::Range2 => 400_000,
MSIRange::Range3 => 800_000,
MSIRange::Range4 => 1_000_000,
MSIRange::Range5 => 2_000_000,
MSIRange::Range6 => 4_000_000,
MSIRange::Range7 => 8_000_000,
MSIRange::Range8 => 16_000_000,
MSIRange::Range9 => 24_000_000,
MSIRange::Range10 => 32_000_000,
MSIRange::Range11 => 48_000_000,
}
}
fn vos(&self) -> VoltageScale {
if self > &MSIRange::Range8 {
VoltageScale::RANGE1
} else {
VoltageScale::RANGE2
}
}
}
impl Default for MSIRange {
fn default() -> MSIRange {
MSIRange::Range6
}
}
impl Into<u8> for MSIRange {
fn into(self) -> u8 {
match self {
MSIRange::Range0 => 0b0000,
MSIRange::Range1 => 0b0001,
MSIRange::Range2 => 0b0010,
MSIRange::Range3 => 0b0011,
MSIRange::Range4 => 0b0100,
MSIRange::Range5 => 0b0101,
MSIRange::Range6 => 0b0110,
MSIRange::Range7 => 0b0111,
MSIRange::Range8 => 0b1000,
MSIRange::Range9 => 0b1001,
MSIRange::Range10 => 0b1010,
MSIRange::Range11 => 0b1011,
}
}
}
#[derive(Clone, Copy)]
pub enum AdcClockSource {
HSI16,
PLLPCLK,
SYSCLK,
}
impl AdcClockSource {
pub fn adcsel(&self) -> Adcsel {
match self {
AdcClockSource::HSI16 => Adcsel::HSI16,
AdcClockSource::PLLPCLK => Adcsel::PLLPCLK,
AdcClockSource::SYSCLK => Adcsel::SYSCLK,
}
}
}
impl Default for AdcClockSource {
fn default() -> Self {
Self::HSI16
}
}
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
@ -138,91 +29,60 @@ pub struct Config {
pub shd_ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub rtc_mux: RtcClockSource,
pub lse: Option<Hertz>,
pub lsi: bool,
pub adc_clock_source: AdcClockSource,
pub ls: super::LsConfig,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
mux: ClockSrc::MSI(MSIRange::default()),
mux: ClockSrc::MSI(MSIRange::RANGE4M),
ahb_pre: AHBPrescaler::DIV1,
shd_ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
rtc_mux: RtcClockSource::LSI,
lsi: true,
lse: None,
adc_clock_source: AdcClockSource::default(),
adc_clock_source: AdcClockSource::HSI16,
ls: Default::default(),
}
}
}
#[repr(u8)]
pub enum Lsedrv {
Low = 0,
MediumLow = 1,
MediumHigh = 2,
High = 3,
}
pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw, vos) = match config.mux {
ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::RANGE2),
ClockSrc::HSE32 => (HSE32_FREQ.0, 0x02, VoltageScale::RANGE1),
ClockSrc::MSI(range) => (range.freq(), 0x00, range.vos()),
ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI16, VoltageScale::RANGE2),
ClockSrc::HSE => (HSE_FREQ, Sw::HSE, VoltageScale::RANGE1),
ClockSrc::MSI(range) => (msirange_to_hertz(range), Sw::MSI, msirange_to_vos(range)),
};
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1 << (pre as u32 - 7);
sys_clk / pre
}
};
let shd_ahb_freq: u32 = match config.shd_ahb_pre {
AHBPrescaler::DIV1 => sys_clk,
pre => {
let pre: u8 = pre.into();
let pre = 1 << (pre as u32 - 7);
sys_clk / pre
}
};
let ahb_freq = sys_clk / config.ahb_pre;
let shd_ahb_freq = sys_clk / config.shd_ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let pre: u8 = pre.into();
let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32;
(freq, freq * 2)
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
// Adjust flash latency
let flash_clk_src_freq: u32 = shd_ahb_freq;
let flash_clk_src_freq = shd_ahb_freq;
let ws = match vos {
VoltageScale::RANGE1 => match flash_clk_src_freq {
VoltageScale::RANGE1 => match flash_clk_src_freq.0 {
0..=18_000_000 => 0b000,
18_000_001..=36_000_000 => 0b001,
_ => 0b010,
},
VoltageScale::RANGE2 => match flash_clk_src_freq {
VoltageScale::RANGE2 => match flash_clk_src_freq.0 {
0..=6_000_000 => 0b000,
6_000_001..=12_000_000 => 0b001,
_ => 0b010,
@ -236,17 +96,14 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != ws {}
// Enables the LSI if configured
BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
match config.mux {
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
ClockSrc::HSE32 => {
// Enable HSE32
ClockSrc::HSE => {
// Enable HSE
RCC.cr().write(|w| {
w.set_hsebyppwr(true);
w.set_hseon(true);
@ -258,49 +115,70 @@ pub(crate) unsafe fn init(config: Config) {
assert!(!cr.msion() || cr.msirdy());
RCC.cr().write(|w| {
w.set_msirgsel(true);
w.set_msirange(range.into());
w.set_msirange(range);
w.set_msion(true);
if let RtcClockSource::LSE = config.rtc_mux {
// If LSE is enabled, enable calibration of MSI
w.set_msipllen(true);
} else {
w.set_msipllen(false);
}
// If LSE is enabled, enable calibration of MSI
w.set_msipllen(config.ls.lse.is_some());
});
while !RCC.cr().read().msirdy() {}
}
}
RCC.extcfgr().modify(|w| {
if config.shd_ahb_pre == AHBPrescaler::DIV1 {
w.set_shdhpre(0);
} else {
w.set_shdhpre(config.shd_ahb_pre.into());
}
w.set_shdhpre(config.shd_ahb_pre);
});
RCC.cfgr().modify(|w| {
w.set_sw(sw.into());
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
// ADC clock MUX
RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel()));
RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
// TODO: switch voltage range
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
ahb3: Hertz(shd_ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb3: Hertz(shd_ahb_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
sys: sys_clk,
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk3: shd_ahb_freq,
pclk1: apb1_freq,
pclk2: apb2_freq,
pclk3: shd_ahb_freq,
pclk1_tim: apb1_tim_freq,
pclk2_tim: apb2_tim_freq,
rtc,
});
}
fn msirange_to_hertz(range: MSIRange) -> Hertz {
match range {
MSIRange::RANGE100K => Hertz(100_000),
MSIRange::RANGE200K => Hertz(200_000),
MSIRange::RANGE400K => Hertz(400_000),
MSIRange::RANGE800K => Hertz(800_000),
MSIRange::RANGE1M => Hertz(1_000_000),
MSIRange::RANGE2M => Hertz(2_000_000),
MSIRange::RANGE4M => Hertz(4_000_000),
MSIRange::RANGE8M => Hertz(8_000_000),
MSIRange::RANGE16M => Hertz(16_000_000),
MSIRange::RANGE24M => Hertz(24_000_000),
MSIRange::RANGE32M => Hertz(32_000_000),
MSIRange::RANGE48M => Hertz(48_000_000),
_ => unreachable!(),
}
}
fn msirange_to_vos(range: MSIRange) -> VoltageScale {
if range.to_bits() > MSIRange::RANGE16M.to_bits() {
VoltageScale::RANGE1
} else {
VoltageScale::RANGE2
}
}

10
embassy-stm32/src/rng.rs
View File

@ -13,6 +13,7 @@ use crate::{interrupt, pac, peripherals, Peripheral};
static RNG_WAKER: AtomicWaker = AtomicWaker::new();
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
SeedError,
@ -42,8 +43,7 @@ impl<'d, T: Instance> Rng<'d, T> {
inner: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
T::enable();
T::reset();
T::enable_and_reset();
into_ref!(inner);
let mut random = Self { _inner: inner };
random.reset();
@ -85,7 +85,7 @@ impl<'d, T: Instance> Rng<'d, T> {
reg.set_ie(false);
reg.set_rngen(true);
});
T::regs().cr().write(|reg| {
T::regs().cr().modify(|reg| {
reg.set_ced(false);
});
// wait for CONDRST to be set
@ -164,7 +164,7 @@ impl<'d, T: Instance> Rng<'d, T> {
return Err(Error::SeedError);
}
// write bytes to chunk
for (dest, src) in chunk.iter_mut().zip(random_word.to_be_bytes().iter()) {
for (dest, src) in chunk.iter_mut().zip(random_word.to_ne_bytes().iter()) {
*dest = *src
}
}
@ -195,7 +195,7 @@ impl<'d, T: Instance> RngCore for Rng<'d, T> {
fn fill_bytes(&mut self, dest: &mut [u8]) {
for chunk in dest.chunks_mut(4) {
let rand = self.next_u32();
for (slot, num) in chunk.iter_mut().zip(rand.to_be_bytes().iter()) {
for (slot, num) in chunk.iter_mut().zip(rand.to_ne_bytes().iter()) {
*slot = *num
}
}

73
embassy-stm32/src/rtc/mod.rs
View File

@ -10,7 +10,6 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex;
pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
pub use crate::rcc::RtcClockSource;
use crate::time::Hertz;
/// refer to AN4759 to compare features of RTC2 and RTC3
@ -93,21 +92,50 @@ impl RtcTimeProvider {
///
/// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
pub fn now(&self) -> Result<DateTime, RtcError> {
let r = RTC::regs();
let tr = r.tr().read();
let second = bcd2_to_byte((tr.st(), tr.su()));
let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
let hour = bcd2_to_byte((tr.ht(), tr.hu()));
// Reading either RTC_SSR or RTC_TR locks the values in the higher-order
// calendar shadow registers until RTC_DR is read.
let dr = r.dr().read();
// For RM0433 we use BYPSHAD=1 to work around errata ES0392 2.19.1
#[cfg(rcc_h7rm0433)]
loop {
let r = RTC::regs();
let ss = r.ssr().read().ss();
let dr = r.dr().read();
let tr = r.tr().read();
let weekday = dr.wdu();
let day = bcd2_to_byte((dr.dt(), dr.du()));
let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
// If an RTCCLK edge occurs during read we may see inconsistent values
// so read ssr again and see if it has changed. (see RM0433 Rev 7 46.3.9)
let ss_after = r.ssr().read().ss();
if ss == ss_after {
let second = bcd2_to_byte((tr.st(), tr.su()));
let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
let hour = bcd2_to_byte((tr.ht(), tr.hu()));
self::datetime::datetime(year, month, day, weekday, hour, minute, second).map_err(RtcError::InvalidDateTime)
let weekday = dr.wdu();
let day = bcd2_to_byte((dr.dt(), dr.du()));
let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
return self::datetime::datetime(year, month, day, weekday, hour, minute, second)
.map_err(RtcError::InvalidDateTime);
}
}
#[cfg(not(rcc_h7rm0433))]
{
let r = RTC::regs();
let tr = r.tr().read();
let second = bcd2_to_byte((tr.st(), tr.su()));
let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
let hour = bcd2_to_byte((tr.ht(), tr.hu()));
// Reading either RTC_SSR or RTC_TR locks the values in the higher-order
// calendar shadow registers until RTC_DR is read.
let dr = r.dr().read();
let weekday = dr.wdu();
let day = bcd2_to_byte((dr.dt(), dr.du()));
let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 1970_u16;
self::datetime::datetime(year, month, day, weekday, hour, minute, second).map_err(RtcError::InvalidDateTime)
}
}
}
@ -155,8 +183,8 @@ impl Default for RtcCalibrationCyclePeriod {
impl Rtc {
pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
#[cfg(any(rcc_wle, rcc_wl5, rcc_g4, rcc_g0, rtc_v2l4, rtc_v2wb))]
<RTC as crate::rcc::sealed::RccPeripheral>::enable();
#[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
<RTC as crate::rcc::sealed::RccPeripheral>::enable_and_reset();
let mut this = Self {
#[cfg(feature = "low-power")]
@ -175,19 +203,8 @@ impl Rtc {
}
fn frequency() -> Hertz {
#[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
let freqs = unsafe { crate::rcc::get_freqs() };
// Load the clock frequency from the rcc mod, if supported
#[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
match freqs.rtc {
Some(hertz) => hertz,
None => freqs.rtc_hse.unwrap(),
}
// Assume the default value, if not supported
#[cfg(not(any(rcc_wb, rcc_f4, rcc_f410)))]
Hertz(32_768)
freqs.rtc.unwrap()
}
/// Acquire a [`RtcTimeProvider`] instance.

33
embassy-stm32/src/rtc/v2.rs
View File

@ -112,25 +112,26 @@ impl super::Rtc {
pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
use crate::interrupt::typelevel::Interrupt;
trace!("rtc: stop wakeup alarm at {}", self.instant());
if RTC::regs().cr().read().wute() {
trace!("rtc: stop wakeup alarm at {}", self.instant());
self.write(false, |regs| {
regs.cr().modify(|w| w.set_wutie(false));
regs.cr().modify(|w| w.set_wute(false));
regs.isr().modify(|w| w.set_wutf(false));
self.write(false, |regs| {
regs.cr().modify(|w| w.set_wutie(false));
regs.cr().modify(|w| w.set_wute(false));
regs.isr().modify(|w| w.set_wutf(false));
crate::pac::EXTI
.pr(0)
.modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
crate::pac::EXTI
.pr(0)
.modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
<RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
});
if let Some(stop_time) = self.stop_time.borrow(cs).take() {
Some(self.instant() - stop_time)
} else {
None
<RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
});
}
self.stop_time
.borrow(cs)
.take()
.map(|stop_time| self.instant() - stop_time)
}
#[cfg(feature = "low-power")]
@ -156,6 +157,8 @@ impl super::Rtc {
w.set_fmt(stm32_metapac::rtc::vals::Fmt::TWENTY_FOUR_HOUR);
w.set_osel(Osel::DISABLED);
w.set_pol(Pol::HIGH);
#[cfg(rcc_h7rm0433)]
w.set_bypshad(true);
});
rtc.prer().modify(|w| {

306
embassy-stm32/src/sai/mod.rs
View File

@ -4,14 +4,14 @@ use embassy_embedded_hal::SetConfig;
use embassy_hal_internal::{into_ref, PeripheralRef};
pub use crate::dma::word;
use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::AnyPin;
use crate::pac::sai::{vals, Sai as Regs};
use crate::rcc::RccPeripheral;
use crate::{peripherals, Peripheral};
#[derive(Debug)]
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
NotATransmitter,
@ -48,8 +48,8 @@ pub enum Mode {
}
#[derive(Copy, Clone)]
enum TxRx {
Transmiter,
pub enum TxRx {
Transmitter,
Receiver,
}
@ -57,7 +57,7 @@ impl Mode {
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
match tx_rx {
TxRx::Transmiter => match self {
TxRx::Transmitter => match self {
Mode::Master => vals::Mode::MASTERTX,
Mode::Slave => vals::Mode::SLAVETX,
},
@ -206,12 +206,13 @@ impl Protocol {
}
}
#[derive(Copy, Clone)]
#[derive(Copy, Clone, PartialEq)]
pub enum SyncEnable {
Asynchronous,
/// Syncs with the other A/B sub-block within the SAI unit
Internal,
/// Syncs with a sub-block in the other SAI unit - use set_sync_output() and set_sync_input()
#[cfg(any(sai_v4))]
External,
}
@ -221,6 +222,7 @@ impl SyncEnable {
match self {
SyncEnable::Asynchronous => vals::Syncen::ASYNCHRONOUS,
SyncEnable::Internal => vals::Syncen::INTERNAL,
#[cfg(any(sai_v4))]
SyncEnable::External => vals::Syncen::EXTERNAL,
}
}
@ -425,6 +427,7 @@ impl MasterClockDivider {
#[derive(Copy, Clone)]
pub struct Config {
pub mode: Mode,
pub tx_rx: TxRx,
pub sync_enable: SyncEnable,
pub is_sync_output: bool,
pub protocol: Protocol,
@ -455,6 +458,7 @@ impl Default for Config {
fn default() -> Self {
Self {
mode: Mode::Master,
tx_rx: TxRx::Transmitter,
is_sync_output: false,
sync_enable: SyncEnable::Asynchronous,
protocol: Protocol::Free,
@ -498,43 +502,130 @@ impl Config {
}
#[derive(Copy, Clone)]
pub enum SubBlock {
enum WhichSubBlock {
A = 0,
B = 1,
}
enum RingBuffer<'d, C: Channel, W: word::Word> {
Writable(WritableRingBuffer<'d, C, W>),
#[allow(dead_code)] // remove this after implementing new_* functions for receiver
Readable(ReadableRingBuffer<'d, C, W>),
}
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
fn wdr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: SubBlock) -> *mut W {
fn dr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: WhichSubBlock) -> *mut W {
let ch = w.ch(sub_block as usize);
ch.dr().as_ptr() as _
}
pub struct Sai<'d, T: Instance, C: Channel, W: word::Word> {
pub struct SubBlock<'d, T: Instance, C: Channel, W: word::Word> {
_peri: PeripheralRef<'d, T>,
sd: Option<PeripheralRef<'d, AnyPin>>,
fs: Option<PeripheralRef<'d, AnyPin>>,
sck: Option<PeripheralRef<'d, AnyPin>>,
mclk: Option<PeripheralRef<'d, AnyPin>>,
ring_buffer: RingBuffer<'d, C, W>,
sub_block: SubBlock,
sub_block: WhichSubBlock,
}
impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
fn get_transmitter_af_types(mode: Mode) -> (AFType, AFType) {
pub struct SubBlockA {}
pub struct SubBlockB {}
pub struct SubBlockAPeripheral<'d, T>(PeripheralRef<'d, T>);
pub struct SubBlockBPeripheral<'d, T>(PeripheralRef<'d, T>);
pub struct Sai<'d, T: Instance> {
_peri: PeripheralRef<'d, T>,
sub_block_a_peri: Option<SubBlockAPeripheral<'d, T>>,
sub_block_b_peri: Option<SubBlockBPeripheral<'d, T>>,
}
// return the type for (sd, sck)
fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AFType, AFType) {
(
//sd is defined by tx/rx mode
match tx_rx {
TxRx::Transmitter => AFType::OutputPushPull,
TxRx::Receiver => AFType::Input,
},
//clocks (mclk, sck and fs) are defined by master/slave
match mode {
Mode::Master => (AFType::OutputPushPull, AFType::OutputPushPull),
Mode::Slave => (AFType::OutputPushPull, AFType::Input),
Mode::Master => AFType::OutputPushPull,
Mode::Slave => AFType::Input,
},
)
}
fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
request: Request,
sub_block: WhichSubBlock,
tx_rx: TxRx,
) -> RingBuffer<'d, C, W> {
let opts = TransferOptions {
half_transfer_ir: true,
//the new_write() and new_read() always use circular mode
..Default::default()
};
match tx_rx {
TxRx::Transmitter => RingBuffer::Writable(unsafe {
WritableRingBuffer::new_write(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
}),
TxRx::Receiver => RingBuffer::Readable(unsafe {
ReadableRingBuffer::new_read(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
}),
}
}
impl<'d, T: Instance> Sai<'d, T> {
pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
T::enable_and_reset();
Self {
_peri: unsafe { peri.clone_unchecked().into_ref() },
sub_block_a_peri: Some(SubBlockAPeripheral(unsafe { peri.clone_unchecked().into_ref() })),
sub_block_b_peri: Some(SubBlockBPeripheral(peri.into_ref())),
}
}
pub fn new_asynchronous_transmitter_with_mclk_a(
peri: impl Peripheral<P = T> + 'd,
pub fn take_sub_block_a(self: &mut Self) -> Option<SubBlockAPeripheral<'d, T>> {
if self.sub_block_a_peri.is_some() {
self.sub_block_a_peri.take()
} else {
None
}
}
pub fn take_sub_block_b(self: &mut Self) -> Option<SubBlockBPeripheral<'d, T>> {
if self.sub_block_b_peri.is_some() {
self.sub_block_b_peri.take()
} else {
None
}
}
}
fn update_synchronous_config(config: &mut Config) {
config.mode = Mode::Slave;
config.is_sync_output = false;
#[cfg(any(sai_v1, sai_v2, sai_v3))]
{
config.sync_enable = SyncEnable::Internal;
}
#[cfg(any(sai_v4))]
{
//this must either be Internal or External
//The asynchronous sub-block on the same SAI needs to enable is_sync_output
assert!(config.sync_enable != SyncEnable::Asynchronous);
}
}
impl SubBlockA {
pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockAPeripheral<'d, T>,
sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
@ -542,37 +633,40 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
) -> Self
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaA<T>,
{
into_ref!(mclk);
mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
mclk.set_as_af(mclk.af_num(), ck_af_type);
mclk.set_speed(crate::gpio::Speed::VeryHigh);
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
config.master_clock_divider = MasterClockDivider::Div1;
}
Self::new_asynchronous_transmitter_a(peri, sck, sd, fs, dma, dma_buf, config)
Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
}
pub fn new_asynchronous_transmitter_a(
peri: impl Peripheral<P = T> + 'd,
pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockAPeripheral<'d, T>,
sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
config: Config,
) -> Self
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaA<T>,
{
let peri = peri.0;
into_ref!(peri, dma, sck, sd, fs);
let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
sd.set_as_af(sd.af_num(), sd_af_type);
sd.set_speed(crate::gpio::Speed::VeryHigh);
@ -581,31 +675,60 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
fs.set_as_af(fs.af_num(), ck_af_type);
fs.set_speed(crate::gpio::Speed::VeryHigh);
let sub_block = WhichSubBlock::A;
let request = dma.request();
let opts = TransferOptions {
half_transfer_ir: true,
circular: true,
..Default::default()
};
let sub_block = SubBlock::A;
Self::new_inner(
SubBlock::new_inner(
peri,
sub_block,
Some(sck.map_into()),
None,
Some(sd.map_into()),
Some(fs.map_into()),
RingBuffer::Writable(unsafe {
WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
}),
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
pub fn new_asynchronous_transmitter_with_mclk_b(
peri: impl Peripheral<P = T> + 'd,
pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockAPeripheral<'d, T>,
sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaA<T>,
{
update_synchronous_config(&mut config);
let peri = peri.0;
into_ref!(dma, peri, sd);
let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
sd.set_as_af(sd.af_num(), sd_af_type);
sd.set_speed(crate::gpio::Speed::VeryHigh);
let sub_block = WhichSubBlock::A;
let request = dma.request();
SubBlock::new_inner(
peri,
sub_block,
None,
None,
Some(sd.map_into()),
None,
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
}
impl SubBlockB {
pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockBPeripheral<'d, T>,
sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
@ -613,37 +736,40 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
) -> Self
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaB<T>,
{
into_ref!(mclk);
mclk.set_as_af(mclk.af_num(), AFType::OutputPushPull);
let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
mclk.set_as_af(mclk.af_num(), ck_af_type);
mclk.set_speed(crate::gpio::Speed::VeryHigh);
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
config.master_clock_divider = MasterClockDivider::Div1;
}
Self::new_asynchronous_transmitter_b(peri, sck, sd, fs, dma, dma_buf, config)
Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
}
pub fn new_asynchronous_transmitter_b(
peri: impl Peripheral<P = T> + 'd,
pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockBPeripheral<'d, T>,
sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
config: Config,
) -> Self
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaB<T>,
{
let peri = peri.0;
into_ref!(dma, peri, sck, sd, fs);
let (sd_af_type, ck_af_type) = Self::get_transmitter_af_types(config.mode);
let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
sd.set_as_af(sd.af_num(), sd_af_type);
sd.set_speed(crate::gpio::Speed::VeryHigh);
@ -653,28 +779,57 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
fs.set_as_af(fs.af_num(), ck_af_type);
fs.set_speed(crate::gpio::Speed::VeryHigh);
let sub_block = WhichSubBlock::B;
let request = dma.request();
let opts = TransferOptions {
half_transfer_ir: true,
..Default::default()
};
let sub_block = SubBlock::B;
Self::new_inner(
SubBlock::new_inner(
peri,
sub_block,
Some(sck.map_into()),
None,
Some(sd.map_into()),
Some(fs.map_into()),
RingBuffer::Writable(unsafe {
WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
}),
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
peri: SubBlockBPeripheral<'d, T>,
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
dma: impl Peripheral<P = C> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
) -> SubBlock<'d, T, C, W>
where
C: Channel + DmaB<T>,
{
update_synchronous_config(&mut config);
let peri = peri.0;
into_ref!(dma, peri, sd);
let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
sd.set_as_af(sd.af_num(), sd_af_type);
sd.set_speed(crate::gpio::Speed::VeryHigh);
let sub_block = WhichSubBlock::B;
let request = dma.request();
SubBlock::new_inner(
peri,
sub_block,
None,
None,
Some(sd.map_into()),
None,
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
}
impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> {
pub fn start(self: &mut Self) {
match self.ring_buffer {
RingBuffer::Writable(ref mut rb) => {
@ -695,7 +850,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
fn new_inner(
peri: impl Peripheral<P = T> + 'd,
sub_block: SubBlock,
sub_block: WhichSubBlock,
sck: Option<PeripheralRef<'d, AnyPin>>,
mclk: Option<PeripheralRef<'d, AnyPin>>,
sd: Option<PeripheralRef<'d, AnyPin>>,
@ -703,13 +858,18 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
ring_buffer: RingBuffer<'d, C, W>,
config: Config,
) -> Self {
T::enable();
T::reset();
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
{
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
}
#[cfg(any(sai_v4))]
{
// Not totally clear from the datasheet if this is right
// This is only used if using SyncEnable::External
// This is only used if using SyncEnable::External on the other SAI unit
// Syncing from SAIX subblock A to subblock B does not require this
// Only syncing from SAI1 subblock A/B to SAI2 subblock A/B
let value: u8 = if T::REGS.as_ptr() == stm32_metapac::SAI1.as_ptr() {
1 //this is SAI1, so sync with SAI2
} else {
@ -721,8 +881,8 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
if config.is_sync_output {
let syncout: u8 = match sub_block {
SubBlock::A => 0b01,
SubBlock::B => 0b10,
WhichSubBlock::A => 0b01,
WhichSubBlock::B => 0b10,
};
T::REGS.gcr().modify(|w| {
w.set_syncout(syncout);
@ -735,7 +895,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| {
w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
TxRx::Transmiter
TxRx::Transmitter
} else {
TxRx::Receiver
}));
@ -770,7 +930,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
w.set_fsoff(config.frame_sync_offset.fsoff());
w.set_fspol(config.frame_sync_polarity.fspol());
w.set_fsdef(config.frame_sync_definition.fsdef());
w.set_fsall(config.frame_sync_active_level_length.0 as u8);
w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
w.set_frl(config.frame_length - 1);
});
@ -782,6 +942,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
});
ch.cr1().modify(|w| w.set_saien(true));
if ch.cr1().read().saien() == false {
panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
}
}
Self {
@ -795,6 +959,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
}
}
pub fn reset() {
T::enable_and_reset();
}
pub fn flush(&mut self) {
let ch = T::REGS.ch(self.sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
@ -814,8 +982,9 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
ch.cr2().modify(|w| w.set_mute(value));
}
#[allow(dead_code)]
/// Reconfigures it with the supplied config.
pub fn reconfigure(&mut self, _config: Config) {}
fn reconfigure(&mut self, _config: Config) {}
pub fn get_current_config(&self) -> Config {
Config::default()
@ -842,7 +1011,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
}
}
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for Sai<'d, T, C, W> {
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for SubBlock<'d, T, C, W> {
fn drop(&mut self) {
let ch = T::REGS.ch(self.sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
@ -886,9 +1055,12 @@ foreach_peripheral!(
};
);
impl<'d, T: Instance, C: Channel, W: word::Word> SetConfig for Sai<'d, T, C, W> {
impl<'d, T: Instance> SetConfig for Sai<'d, T> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
self.reconfigure(*config);
type ConfigError = ();
fn set_config(&mut self, _config: &Self::Config) -> Result<(), ()> {
// self.reconfigure(*config);
Ok(())
}
}

9
embassy-stm32/src/sdmmc/mod.rs
View File

@ -452,8 +452,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
) -> Self {
into_ref!(sdmmc, dma);
T::enable();
T::reset();
T::enable_and_reset();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
@ -1458,7 +1457,7 @@ cfg_if::cfg_if! {
macro_rules! kernel_clk {
($inst:ident) => {
critical_section::with(|_| unsafe {
crate::rcc::get_freqs().pll48
crate::rcc::get_freqs().pll1_q
}).expect("PLL48 is required for SDIO")
}
}
@ -1470,7 +1469,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC")
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
}
})
};
@ -1480,7 +1479,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC")
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
}
})
};

13
embassy-stm32/src/spi/mod.rs
View File

@ -15,7 +15,7 @@ use crate::rcc::RccPeripheral;
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
#[derive(Debug)]
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
Framing,
@ -230,8 +230,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let lsbfirst = config.raw_byte_order();
T::enable();
T::reset();
T::enable_and_reset();
#[cfg(any(spi_v1, spi_f1))]
{
@ -323,7 +322,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
/// Reconfigures it with the supplied config.
pub fn set_config(&mut self, config: Config) {
pub fn set_config(&mut self, config: &Config) -> Result<(), ()> {
let cpha = config.raw_phase();
let cpol = config.raw_polarity();
@ -352,6 +351,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_mbr(br);
});
}
Ok(())
}
pub fn get_current_config(&self) -> Config {
@ -1061,7 +1061,8 @@ foreach_peripheral!(
impl<'d, T: Instance, Tx, Rx> SetConfig for Spi<'d, T, Tx, Rx> {
type Config = Config;
fn set_config(&mut self, config: &Self::Config) {
self.set_config(*config);
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config)
}
}

7
embassy-stm32/src/time.rs
View File

@ -77,3 +77,10 @@ impl Div<u8> for Hertz {
self / (rhs as u32)
}
}
impl Div<Hertz> for Hertz {
type Output = u32;
fn div(self, rhs: Hertz) -> Self::Output {
self.0 / rhs.0
}
}

85
embassy-stm32/src/time_driver.rs
View File

@ -1,9 +1,8 @@
use core::cell::Cell;
use core::convert::TryInto;
use core::sync::atomic::{compiler_fence, Ordering};
use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use core::{mem, ptr};
use atomic_polyfill::{AtomicU32, AtomicU8};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex;
@ -153,46 +152,43 @@ embassy_time::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
});
impl RtcDriver {
fn init(&'static self) {
fn init(&'static self, cs: critical_section::CriticalSection) {
let r = T::regs_gp16();
<T as RccPeripheral>::enable();
<T as RccPeripheral>::reset();
<T as RccPeripheral>::enable_and_reset_with_cs(cs);
let timer_freq = T::frequency();
critical_section::with(|_| {
r.cr1().modify(|w| w.set_cen(false));
r.cnt().write(|w| w.set_cnt(0));
r.cr1().modify(|w| w.set_cen(false));
r.cnt().write(|w| w.set_cnt(0));
let psc = timer_freq.0 / TICK_HZ as u32 - 1;
let psc: u16 = match psc.try_into() {
Err(_) => panic!("psc division overflow: {}", psc),
Ok(n) => n,
};
let psc = timer_freq.0 / TICK_HZ as u32 - 1;
let psc: u16 = match psc.try_into() {
Err(_) => panic!("psc division overflow: {}", psc),
Ok(n) => n,
};
r.psc().write(|w| w.set_psc(psc));
r.arr().write(|w| w.set_arr(u16::MAX));
r.psc().write(|w| w.set_psc(psc));
r.arr().write(|w| w.set_arr(u16::MAX));
// Set URS, generate update and clear URS
r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTERONLY));
r.egr().write(|w| w.set_ug(true));
r.cr1().modify(|w| w.set_urs(vals::Urs::ANYEVENT));
// Set URS, generate update and clear URS
r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTERONLY));
r.egr().write(|w| w.set_ug(true));
r.cr1().modify(|w| w.set_urs(vals::Urs::ANYEVENT));
// Mid-way point
r.ccr(0).write(|w| w.set_ccr(0x8000));
// Mid-way point
r.ccr(0).write(|w| w.set_ccr(0x8000));
// Enable overflow and half-overflow interrupts
r.dier().write(|w| {
w.set_uie(true);
w.set_ccie(0, true);
});
// Enable overflow and half-overflow interrupts
r.dier().write(|w| {
w.set_uie(true);
w.set_ccie(0, true);
});
<T as BasicInstance>::Interrupt::unpend();
unsafe { <T as BasicInstance>::Interrupt::enable() };
<T as BasicInstance>::Interrupt::unpend();
unsafe { <T as BasicInstance>::Interrupt::enable() };
r.cr1().modify(|w| w.set_cen(true));
})
r.cr1().modify(|w| w.set_cen(true));
}
fn on_interrupt(&self) {
@ -229,7 +225,9 @@ impl RtcDriver {
fn next_period(&self) {
let r = T::regs_gp16();
let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
// We only modify the period from the timer interrupt, so we know this can't race.
let period = self.period.load(Ordering::Relaxed) + 1;
self.period.store(period, Ordering::Relaxed);
let t = (period as u64) << 15;
critical_section::with(move |cs| {
@ -340,7 +338,11 @@ impl RtcDriver {
#[cfg(feature = "low-power")]
/// Set the rtc but panic if it's already been set
pub(crate) fn set_rtc(&self, rtc: &'static Rtc) {
critical_section::with(|cs| assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none()));
critical_section::with(|cs| {
rtc.stop_wakeup_alarm(cs);
assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none())
});
}
#[cfg(feature = "low-power")]
@ -399,18 +401,15 @@ impl Driver for RtcDriver {
}
unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
let id = self.alarm_count.fetch_update(Ordering::AcqRel, Ordering::Acquire, |x| {
if x < ALARM_COUNT as u8 {
Some(x + 1)
critical_section::with(|_| {
let id = self.alarm_count.load(Ordering::Relaxed);
if id < ALARM_COUNT as u8 {
self.alarm_count.store(id + 1, Ordering::Relaxed);
Some(AlarmHandle::new(id))
} else {
None
}
});
match id {
Ok(id) => Some(AlarmHandle::new(id)),
Err(_) => None,
}
})
}
fn set_alarm_callback(&self, alarm: AlarmHandle, callback: fn(*mut ()), ctx: *mut ()) {
@ -461,6 +460,6 @@ pub(crate) fn get_driver() -> &'static RtcDriver {
&DRIVER
}
pub(crate) fn init() {
DRIVER.init()
pub(crate) fn init(cs: CriticalSection) {
DRIVER.init(cs)
}

45
embassy-stm32/src/timer/complementary_pwm.rs
View File

@ -65,8 +65,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
into_ref!(tim);
T::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
T::enable_and_reset();
let mut this = Self { inner: tim };
@ -74,7 +73,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
this.set_freq(freq);
this.inner.start();
this.inner.enable_outputs(true);
this.inner.enable_outputs();
this.inner
.set_output_compare_mode(Channel::Ch1, OutputCompareMode::PwmMode1);
@ -129,6 +128,46 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
}
}
impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
self.inner.enable_complementary_channel(channel, false);
self.inner.enable_channel(channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
self.inner.enable_channel(channel, true);
self.inner.enable_complementary_channel(channel, true);
}
fn get_period(&self) -> Self::Time {
self.inner.get_frequency().into()
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
self.inner.get_compare_value(channel)
}
fn get_max_duty(&self) -> Self::Duty {
self.inner.get_max_compare_value() + 1
}
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
self.inner.set_compare_value(channel, duty)
}
fn set_period<P>(&mut self, period: P)
where
P: Into<Self::Time>,
{
self.inner.set_frequency(period.into());
}
}
fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
/*
Dead-time = T_clk * T_dts * T_dtg

42
embassy-stm32/src/timer/mod.rs
View File

@ -77,6 +77,16 @@ pub(crate) mod sealed {
fn set_autoreload_preload(&mut self, enable: vals::Arpe) {
Self::regs().cr1().modify(|r| r.set_arpe(enable));
}
fn get_frequency(&self) -> Hertz {
let timer_f = Self::frequency();
let regs = Self::regs();
let arr = regs.arr().read().arr();
let psc = regs.psc().read().psc();
timer_f / arr / (psc + 1)
}
}
pub trait GeneralPurpose16bitInstance: Basic16bitInstance {
@ -123,6 +133,16 @@ pub(crate) mod sealed {
regs.egr().write(|r| r.set_ug(true));
regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
}
fn get_frequency(&self) -> Hertz {
let timer_f = Self::frequency();
let regs = Self::regs_gp32();
let arr = regs.arr().read().arr();
let psc = regs.psc().read().psc();
timer_f / arr / (psc + 1)
}
}
pub trait AdvancedControlInstance: GeneralPurpose16bitInstance {
@ -173,7 +193,7 @@ pub(crate) mod sealed {
}
});
}
fn enable_outputs(&mut self, _enable: bool) {}
fn enable_outputs(&mut self);
fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
let r = Self::regs_gp16();
@ -203,6 +223,10 @@ pub(crate) mod sealed {
fn get_max_compare_value(&self) -> u16 {
Self::regs_gp16().arr().read().arr()
}
fn get_compare_value(&self, channel: Channel) -> u16 {
Self::regs_gp16().ccr(channel.raw()).read().ccr()
}
}
pub trait ComplementaryCaptureCompare16bitInstance: CaptureCompare16bitInstance + AdvancedControlInstance {
@ -239,6 +263,10 @@ pub(crate) mod sealed {
fn get_max_compare_value(&self) -> u32 {
Self::regs_gp32().arr().read().arr()
}
fn get_compare_value(&self, channel: Channel) -> u32 {
Self::regs_gp32().ccr(channel.raw()).read().ccr()
}
}
}
@ -460,7 +488,9 @@ macro_rules! impl_32bit_timer {
#[allow(unused)]
macro_rules! impl_compare_capable_16bit {
($inst:ident) => {
impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {
fn enable_outputs(&mut self) {}
}
};
}
@ -509,7 +539,13 @@ foreach_interrupt! {
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
impl AdvancedControlInstance for crate::peripherals::$inst {}
impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {
fn enable_outputs(&mut self) {
use crate::timer::sealed::AdvancedControlInstance;
let r = Self::regs_advanced();
r.bdtr().modify(|w| w.set_moe(true));
}
}
impl sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
fn regs_gp16() -> crate::pac::timer::TimGp16 {

3
embassy-stm32/src/timer/qei.rs
View File

@ -55,8 +55,7 @@ impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(tim);
T::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
T::enable_and_reset();
// Configure TxC1 and TxC2 as captures
T::regs_gp16().ccmr_input(0).modify(|w| {

43
embassy-stm32/src/timer/simple_pwm.rs
View File

@ -64,8 +64,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
into_ref!(tim);
T::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
T::enable_and_reset();
let mut this = Self { inner: tim };
@ -73,7 +72,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
this.set_freq(freq);
this.inner.start();
this.inner.enable_outputs(true);
this.inner.enable_outputs();
this.inner
.set_output_compare_mode(Channel::Ch1, OutputCompareMode::PwmMode1);
@ -116,3 +115,41 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
self.inner.set_output_polarity(channel, polarity);
}
}
impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
self.inner.enable_channel(channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
self.inner.enable_channel(channel, true);
}
fn get_period(&self) -> Self::Time {
self.inner.get_frequency().into()
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
self.inner.get_compare_value(channel)
}
fn get_max_duty(&self) -> Self::Duty {
self.inner.get_max_compare_value() + 1
}
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
self.inner.set_compare_value(channel, duty)
}
fn set_period<P>(&mut self, period: P)
where
P: Into<Self::Time>,
{
self.inner.set_frequency(period.into());
}
}

30
embassy-stm32/src/usart/buffered.rs
View File

@ -116,25 +116,28 @@ pub struct BufferedUartRx<'d, T: BasicInstance> {
impl<'d, T: BasicInstance> SetConfig for BufferedUart<'d, T> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config))
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}
impl<'d, T: BasicInstance> SetConfig for BufferedUartRx<'d, T> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config))
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}
impl<'d, T: BasicInstance> SetConfig for BufferedUartTx<'d, T> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config))
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}
@ -149,9 +152,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
config: Config,
) -> Result<Self, ConfigError> {
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
}
@ -170,9 +172,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
cts.set_as_af(cts.af_num(), AFType::Input);
@ -198,9 +199,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
de.set_as_af(de.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {

48
embassy-stm32/src/usart/mod.rs
View File

@ -181,10 +181,11 @@ pub struct Uart<'d, T: BasicInstance, TxDma = NoDma, RxDma = NoDma> {
impl<'d, T: BasicInstance, TxDma, RxDma> SetConfig for Uart<'d, T, TxDma, RxDma> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.tx.set_config(config));
unwrap!(self.rx.set_config(config));
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.tx.set_config(config).map_err(|_| ())?;
self.rx.set_config(config).map_err(|_| ())
}
}
@ -195,9 +196,10 @@ pub struct UartTx<'d, T: BasicInstance, TxDma = NoDma> {
impl<'d, T: BasicInstance, TxDma> SetConfig for UartTx<'d, T, TxDma> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config));
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}
@ -211,9 +213,10 @@ pub struct UartRx<'d, T: BasicInstance, RxDma = NoDma> {
impl<'d, T: BasicInstance, RxDma> SetConfig for UartRx<'d, T, RxDma> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config));
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}
@ -225,8 +228,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> {
tx_dma: impl Peripheral<P = TxDma> + 'd,
config: Config,
) -> Result<Self, ConfigError> {
T::enable();
T::reset();
T::enable_and_reset();
Self::new_inner(peri, tx, tx_dma, config)
}
@ -240,8 +242,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> {
) -> Result<Self, ConfigError> {
into_ref!(cts);
T::enable();
T::reset();
T::enable_and_reset();
cts.set_as_af(cts.af_num(), AFType::Input);
T::regs().cr3().write(|w| {
@ -318,8 +319,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
rx_dma: impl Peripheral<P = RxDma> + 'd,
config: Config,
) -> Result<Self, ConfigError> {
T::enable();
T::reset();
T::enable_and_reset();
Self::new_inner(peri, rx, rx_dma, config)
}
@ -334,8 +334,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
) -> Result<Self, ConfigError> {
into_ref!(rts);
T::enable();
T::reset();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {
@ -692,9 +691,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
config: Config,
) -> Result<Self, ConfigError> {
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
}
@ -713,9 +711,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
cts.set_as_af(cts.af_num(), AFType::Input);
@ -740,9 +737,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
T::enable_and_reset();
T::enable_and_reset();
de.set_as_af(de.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {
@ -803,10 +799,6 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
})
}
pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
reconfigure::<T>(config)
}
pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error>
where
TxDma: crate::usart::TxDma<T>,

5
embassy-stm32/src/usart/ringbuffered.rs
View File

@ -18,9 +18,10 @@ pub struct RingBufferedUartRx<'d, T: BasicInstance, RxDma: super::RxDma<T>> {
impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> SetConfig for RingBufferedUartRx<'d, T, RxDma> {
type Config = Config;
type ConfigError = ();
fn set_config(&mut self, config: &Self::Config) {
unwrap!(self.set_config(config));
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
self.set_config(config).map_err(|_| ())
}
}

3
embassy-stm32/src/usb/usb.rs
View File

@ -269,8 +269,7 @@ impl<'d, T: Instance> Driver<'d, T> {
#[cfg(pwr_h5)]
crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true));
<T as RccPeripheral>::enable();
<T as RccPeripheral>::reset();
<T as RccPeripheral>::enable_and_reset();
regs.cntr().write(|w| {
w.set_pdwn(false);

3
embassy-stm32/src/usb_otg/usb.rs
View File

@ -632,8 +632,7 @@ impl<'d, T: Instance> Bus<'d, T> {
});
}
<T as RccPeripheral>::enable();
<T as RccPeripheral>::reset();
<T as RccPeripheral>::enable_and_reset();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };