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configure flash latency after axi clock and handle different flash in STM32H7A/B devices

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This commit is contained in:
Dominik Sliwa
2023-08-18 22:10:13 +02:00
parent 97da34595c
commit 5bc0175be9
4 changed files with 62 additions and 7 deletions
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12
embassy-stm32/src/flash/h7.rs
View File

@ -11,7 +11,7 @@ pub const fn is_default_layout() -> bool {
}
const fn is_dual_bank() -> bool {
FLASH_REGIONS.len() == 2
FLASH_REGIONS.len() >= 2
}
pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
@ -49,6 +49,7 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
};
bank.cr().write(|w| {
w.set_pg(true);
#[cfg(flash_h7)]
w.set_psize(2); // 32 bits at once
});
cortex_m::asm::isb();
@ -85,7 +86,10 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
let bank = pac::FLASH.bank(sector.bank as usize);
bank.cr().modify(|w| {
w.set_ser(true);
w.set_snb(sector.index_in_bank)
#[cfg(flash_h7)]
w.set_snb(sector.index_in_bank);
#[cfg(flash_h7ab)]
w.set_ssn(sector.index_in_bank);
});
bank.cr().modify(|w| {
@ -126,6 +130,10 @@ unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
error!("incerr");
return Err(Error::Seq);
}
if sr.crcrderr() {
error!("crcrderr");
return Err(Error::Seq);
}
if sr.operr() {
return Err(Error::Prog);
}

4
embassy-stm32/src/flash/mod.rs
View File

@ -65,9 +65,11 @@ impl FlashRegion {
#[cfg_attr(flash_f7, path = "f7.rs")]
#[cfg_attr(flash_g0, path = "g0.rs")]
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(flash_h7ab, path = "h7.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_h7
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_h7,
flash_h7ab
)),
path = "other.rs"
)]