Add fmt.rs to improve log/debug and embbed and PC
Also add `defmt` to the features list.
This commit is contained in:
René van Dorst
@ -6,6 +6,9 @@
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#![allow(clippy::missing_panics_doc)]
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#![doc = include_str!("../README.md")]
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// must go first!
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mod fmt;
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mod crc32;
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mod crc8;
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mod mdio;
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@ -20,12 +23,13 @@ use embassy_net_driver_channel as ch;
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use embassy_time::{Duration, Timer};
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use embedded_hal_1::digital::OutputPin;
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use embedded_hal_async::digital::Wait;
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use embedded_hal_async::spi::{Operation, SpiDevice};
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use embedded_hal_async::spi::{Error, Operation, SpiDevice};
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use heapless::Vec;
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pub use mdio::MdioBus;
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pub use phy::{Phy10BaseT1x, RegsC22, RegsC45};
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pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1};
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use crate::fmt::Bytes;
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use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader};
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pub const PHYID: u32 = 0x0283_BC91;
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@ -153,8 +157,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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let value = u32::from_be_bytes(rx_buf[0..4].try_into().unwrap());
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#[cfg(feature = "defmt")]
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defmt::trace!("REG Read {} = {:08x} SPI {:02x}", reg, value, &tx_buf);
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trace!("REG Read {} = {:08x} SPI {}", reg, value, Bytes(&tx_buf));
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Ok(value)
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}
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@ -181,8 +184,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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let _ = tx_buf.push(crc8(val.as_slice()));
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}
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#[cfg(feature = "defmt")]
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defmt::trace!("REG Write {} = {:08x} SPI {:02x}", reg, value, &tx_buf);
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trace!("REG Write {} = {:08x} SPI {}", reg, value, Bytes(&tx_buf));
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self.spi.write(&tx_buf).await.map_err(AdinError::Spi)
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}
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@ -219,8 +221,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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let packet_size = fifo_frame_size - FRAME_HEADER_LEN - FCS_LEN;
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if packet_size > frame.len() {
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#[cfg(feature = "defmt")]
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defmt::trace!("MAX: {} WANT: {}", frame.len(), packet_size);
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trace!("MAX: {} WANT: {}", frame.len(), packet_size);
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return Err(AdinError::PACKET_TOO_BIG);
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}
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@ -333,14 +334,13 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
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self.write_reg(sr::TX_FSIZE, send_len).await?;
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#[cfg(feature = "defmt")]
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defmt::trace!(
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"TX: hdr {} [{}] {:02x}-{:02x}-{:02x} SIZE: {}",
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trace!(
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"TX: hdr {} [{}] {}-{}-{} SIZE: {}",
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head_data.len(),
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frame.len(),
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head_data.as_slice(),
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frame,
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tail_data.as_slice(),
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Bytes(head_data.as_slice()),
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Bytes(frame),
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Bytes(tail_data.as_slice()),
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send_len,
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);
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@ -445,16 +445,14 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
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let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
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loop {
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#[cfg(feature = "defmt")]
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defmt::debug!("Waiting for interrupts");
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debug!("Waiting for interrupts");
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match select(self.int.wait_for_low(), tx_chan.tx_buf()).await {
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Either::First(_) => {
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let mut status1_clr = Status1(0);
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let mut status1 = Status1(self.mac.read_reg(sr::STATUS1).await.unwrap());
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while status1.p1_rx_rdy() {
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#[cfg(feature = "defmt")]
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defmt::debug!("alloc RX packet buffer");
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debug!("alloc RX packet buffer");
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match select(rx_chan.rx_buf(), tx_chan.tx_buf()).await {
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// Handle frames that needs to transmit from the wire.
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// Note: rx_chan.rx_buf() channel don´t accept new request
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@ -466,22 +464,18 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
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}
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Err(e) => match e {
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AdinError::PACKET_TOO_BIG => {
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#[cfg(feature = "defmt")]
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defmt::error!("RX Packet too big, DROP");
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error!("RX Packet too big, DROP");
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self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap();
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}
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AdinError::PACKET_TOO_SMALL => {
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#[cfg(feature = "defmt")]
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defmt::error!("RX Packet too small, DROP");
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error!("RX Packet too small, DROP");
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self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap();
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}
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AdinError::Spi(_) => {
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#[cfg(feature = "defmt")]
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defmt::error!("RX Spi error")
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AdinError::Spi(e) => {
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error!("RX Spi error {}", e.kind());
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}
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_ => {
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#[cfg(feature = "defmt")]
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defmt::error!("RX Error")
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error!("RX Error");
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}
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},
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},
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@ -496,21 +490,18 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
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let status0 = Status0(self.mac.read_reg(sr::STATUS0).await.unwrap());
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if status1.0 & !0x1b != 0 {
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#[cfg(feature = "defmt")]
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defmt::error!("SPE CHIP STATUS 0:{:08x} 1:{:08x}", status0.0, status1.0);
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error!("SPE CHIP STATUS 0:{:08x} 1:{:08x}", status0.0, status1.0);
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}
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if status1.tx_rdy() {
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status1_clr.set_tx_rdy(true);
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#[cfg(feature = "defmt")]
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defmt::info!("TX_DONE");
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trace!("TX_DONE");
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}
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if status1.link_change() {
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let link = status1.p1_link_status();
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self.is_link_up = link;
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#[cfg(feature = "defmt")]
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if link {
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let link_status = self
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.mac
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@ -530,9 +521,9 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
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.await
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.unwrap();
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defmt::info!("LINK Changed: Link Up, Volt: {} V p-p, MSE: {:0004}", volt, mse);
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info!("LINK Changed: Link Up, Volt: {} V p-p, MSE: {:0004}", volt, mse);
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} else {
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defmt::info!("LINK Changed: Link Down");
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info!("LINK Changed: Link Down");
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}
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state_chan.set_link_state(if link { LinkState::Up } else { LinkState::Down });
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@ -540,50 +531,42 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
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}
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if status1.tx_ecc_err() {
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#[cfg(feature = "defmt")]
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defmt::error!("SPI TX_ECC_ERR error, CLEAR TX FIFO");
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error!("SPI TX_ECC_ERR error, CLEAR TX FIFO");
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self.mac.write_reg(sr::FIFO_CLR, 2).await.unwrap();
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status1_clr.set_tx_ecc_err(true);
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}
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if status1.rx_ecc_err() {
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#[cfg(feature = "defmt")]
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defmt::error!("SPI RX_ECC_ERR error");
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error!("SPI RX_ECC_ERR error");
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status1_clr.set_rx_ecc_err(true);
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}
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if status1.spi_err() {
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#[cfg(feature = "defmt")]
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defmt::error!("SPI SPI_ERR CRC error");
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error!("SPI SPI_ERR CRC error");
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status1_clr.set_spi_err(true);
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}
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if status0.phyint() {
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#[cfg_attr(not(feature = "defmt"), allow(unused_variables))]
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let crsm_irq_st = self
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.mac
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.read_cl45(MDIO_PHY_ADDR, RegsC45::DA1E::CRSM_IRQ_STATUS.into())
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.await
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.unwrap();
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#[cfg_attr(not(feature = "defmt"), allow(unused_variables))]
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let phy_irq_st = self
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.mac
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.read_cl45(MDIO_PHY_ADDR, RegsC45::DA1F::PHY_SYBSYS_IRQ_STATUS.into())
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.await
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.unwrap();
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#[cfg(feature = "defmt")]
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defmt::warn!(
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warn!(
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"SPE CHIP PHY CRSM_IRQ_STATUS {:04x} PHY_SUBSYS_IRQ_STATUS {:04x}",
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crsm_irq_st,
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phy_irq_st
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crsm_irq_st, phy_irq_st
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);
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}
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if status0.txfcse() {
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#[cfg(feature = "defmt")]
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defmt::error!("SPE CHIP PHY TX Frame CRC error");
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error!("Ethernet Frame FCS and calc FCS don't match!");
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}
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// Clear status0
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@ -613,8 +596,7 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
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) -> (Device<'_>, Runner<'_, SPI, INT, RST>) {
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use crate::regs::{IMask0, IMask1};
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#[cfg(feature = "defmt")]
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defmt::info!("INIT ADIN1110");
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info!("INIT ADIN1110");
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// Reset sequence
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reset.set_low().unwrap();
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@ -634,23 +616,20 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
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let id = mac.read_reg(sr::PHYID).await.unwrap();
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assert_eq!(id, PHYID);
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#[cfg(feature = "defmt")]
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defmt::debug!("SPE: CHIP MAC/ID: {:08x}", id);
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debug!("SPE: CHIP MAC/ID: {:08x}", id);
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#[cfg(feature = "defmt")]
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let adin_phy = Phy10BaseT1x::default();
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#[cfg(feature = "defmt")]
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let phy_id = adin_phy.get_id(&mut mac).await.unwrap();
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#[cfg(feature = "defmt")]
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defmt::debug!("SPE: CHIP: PHY ID: {:08x}", phy_id);
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#[cfg(any(feature = "defmt", feature = "log"))]
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{
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let adin_phy = Phy10BaseT1x::default();
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let phy_id = adin_phy.get_id(&mut mac).await.unwrap();
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debug!("SPE: CHIP: PHY ID: {:08x}", phy_id);
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}
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let mi_control = mac.read_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8).await.unwrap();
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#[cfg(feature = "defmt")]
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defmt::println!("SPE CHIP PHY MI_CONTROL {:04x}", mi_control);
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debug!("SPE CHIP PHY MI_CONTROL {:04x}", mi_control);
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if mi_control & 0x0800 != 0 {
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let val = mi_control & !0x0800;
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#[cfg(feature = "defmt")]
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defmt::println!("SPE CHIP PHY MI_CONTROL Disable PowerDown");
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debug!("SPE CHIP PHY MI_CONTROL Disable PowerDown");
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mac.write_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8, val)
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.await
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.unwrap();
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