Merge #1353
1353: Add empty test binary for riscv r=Dirbaio a=royb3 As discussed with `@Dirbaio,` this empty test binary should cause a build to fail when it is not possible to build or link a riscv binary. Co-authored-by: Roy Buitenhuis <roy.buitenhuis@technolution.nl>
This commit is contained in:
commit
5c42ca13bd
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ci.sh
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ci.sh
@ -124,6 +124,7 @@ cargo batch \
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--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/iot-stm32u585ai \
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--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/iot-stm32u585ai \
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--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
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--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
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--- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
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--- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
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--- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
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$BUILD_EXTRA
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$BUILD_EXTRA
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5
tests/riscv32/.cargo/config.toml
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5
tests/riscv32/.cargo/config.toml
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@ -0,0 +1,5 @@
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[target.riscv32imac-unknown-none-elf]
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runner = "true"
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[build]
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target = "riscv32imac-unknown-none-elf"
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46
tests/riscv32/Cargo.toml
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46
tests/riscv32/Cargo.toml
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@ -0,0 +1,46 @@
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[package]
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edition = "2021"
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name = "embassy-riscv-tests"
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version = "0.1.0"
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license = "MIT OR Apache-2.0"
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[dependencies]
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critical-section = { version = "1.1.1", features = ["restore-state-bool"] }
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embassy-sync = { version = "0.1.0", path = "../../embassy-sync" }
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embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-riscv32", "nightly", "executor-thread"] }
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embassy-time = { version = "0.1.0", path = "../../embassy-time" }
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embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
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riscv-rt = "0.11"
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riscv = { version = "0.10", features = ["critical-section-single-hart"] }
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[profile.dev]
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debug = 2
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debug-assertions = true
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opt-level = 's'
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overflow-checks = true
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[profile.release]
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codegen-units = 1
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debug = 2
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debug-assertions = false
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incremental = false
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lto = "fat"
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opt-level = 's'
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overflow-checks = false
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# do not optimize proc-macro crates = faster builds from scratch
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[profile.dev.build-override]
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codegen-units = 8
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debug = false
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debug-assertions = false
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opt-level = 0
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overflow-checks = false
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[profile.release.build-override]
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codegen-units = 8
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debug = false
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debug-assertions = false
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opt-level = 0
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overflow-checks = false
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8
tests/riscv32/build.rs
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8
tests/riscv32/build.rs
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@ -0,0 +1,8 @@
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use std::error::Error;
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fn main() -> Result<(), Box<dyn Error>> {
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println!("cargo:rustc-link-arg-bins=-Tmemory.x");
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println!("cargo:rustc-link-arg-bins=-Tlink.x");
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Ok(())
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}
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14
tests/riscv32/memory.x
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tests/riscv32/memory.x
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MEMORY
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{
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ROM : ORIGIN = 0x80000000, LENGTH = 0x00020000
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RAM : ORIGIN = 0x84000000, LENGTH = 0x00008000
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}
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REGION_ALIAS("REGION_TEXT", ROM);
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REGION_ALIAS("REGION_RODATA", ROM);
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REGION_ALIAS("REGION_DATA", RAM);
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REGION_ALIAS("REGION_BSS", RAM);
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REGION_ALIAS("REGION_HEAP", RAM);
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REGION_ALIAS("REGION_STACK", RAM);
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_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4;
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16
tests/riscv32/src/bin/empty.rs
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tests/riscv32/src/bin/empty.rs
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@ -0,0 +1,16 @@
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use embassy_executor::Spawner;
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#[panic_handler]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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loop {}
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}
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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// Don't do anything, just make sure it compiles.
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loop {}
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}
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