From 5cfb9adad807954148310bb56ad98e74718ceca6 Mon Sep 17 00:00:00 2001 From: Thales Fragoso Date: Wed, 28 Jul 2021 17:32:36 -0300 Subject: [PATCH] f4-pll: Add max values per chip --- embassy-stm32/src/rcc/f4/max.rs | 268 ++++++++++++++++++++++++++++++ embassy-stm32/src/rcc/f4/mod.rs | 16 +- examples/stm32f4/src/bin/hello.rs | 2 +- 3 files changed, 273 insertions(+), 13 deletions(-) create mode 100644 embassy-stm32/src/rcc/f4/max.rs diff --git a/embassy-stm32/src/rcc/f4/max.rs b/embassy-stm32/src/rcc/f4/max.rs new file mode 100644 index 00000000..03e1e983 --- /dev/null +++ b/embassy-stm32/src/rcc/f4/max.rs @@ -0,0 +1,268 @@ +#[cfg(any( + feature = "stm32f401cb", + feature = "stm32f401cc", + feature = "stm32f401cd", + feature = "stm32f401ce", + feature = "stm32f401rb", + feature = "stm32f401rc", + feature = "stm32f401rd", + feature = "stm32f401re", + feature = "stm32f401vb", + feature = "stm32f401vc", + feature = "stm32f401vd", + feature = "stm32f401ve", +))] +pub(crate) const SYSCLK_MAX: u32 = 84_000_000; + +#[cfg(any( + feature = "stm32f405oe", + feature = "stm32f405og", + feature = "stm32f405rg", + feature = "stm32f405vg", + feature = "stm32f405zg", + feature = "stm32f407ie", + feature = "stm32f407ig", + feature = "stm32f407ve", + feature = "stm32f407vg", + feature = "stm32f407ze", + feature = "stm32f407zg", + feature = "stm32f415og", + feature = "stm32f415rg", + feature = "stm32f415vg", + feature = "stm32f415zg", + feature = "stm32f417ie", + feature = "stm32f417ig", + feature = "stm32f417ve", + feature = "stm32f417vg", + feature = "stm32f417ze", + feature = "stm32f417zg", +))] +pub(crate) const SYSCLK_MAX: u32 = 168_000_000; + +#[cfg(any( + feature = "stm32f410c8", + feature = "stm32f410cb", + feature = "stm32f410r8", + feature = "stm32f410rb", + feature = "stm32f410t8", + feature = "stm32f410tb", + feature = "stm32f411cc", + feature = "stm32f411ce", + feature = "stm32f411rc", + feature = "stm32f411re", + feature = "stm32f411vc", + feature = "stm32f411ve", + feature = "stm32f412ce", + feature = "stm32f412cg", + feature = "stm32f412re", + feature = "stm32f412rg", + feature = "stm32f412ve", + feature = "stm32f412vg", + feature = "stm32f412ze", + feature = "stm32f412zg", + feature = "stm32f413cg", + feature = "stm32f413ch", + feature = "stm32f413mg", + feature = "stm32f413mh", + feature = "stm32f413rg", + feature = "stm32f413rh", + feature = "stm32f413vg", + feature = "stm32f413vh", + feature = "stm32f413zg", + feature = "stm32f413zh", + feature = "stm32f423ch", + feature = "stm32f423mh", + feature = "stm32f423rh", + feature = "stm32f423vh", + feature = "stm32f423zh", +))] +pub(crate) const SYSCLK_MAX: u32 = 100_000_000; + +#[cfg(any( + feature = "stm32f427ag", + feature = "stm32f427ai", + feature = "stm32f427ig", + feature = "stm32f427ii", + feature = "stm32f427vg", + feature = "stm32f427vi", + feature = "stm32f427zg", + feature = "stm32f427zi", + feature = "stm32f429ag", + feature = "stm32f429ai", + feature = "stm32f429be", + feature = "stm32f429bg", + feature = "stm32f429bi", + feature = "stm32f429ie", + feature = "stm32f429ig", + feature = "stm32f429ii", + feature = "stm32f429ne", + feature = "stm32f429ng", + feature = "stm32f429ni", + feature = "stm32f429ve", + feature = "stm32f429vg", + feature = "stm32f429vi", + feature = "stm32f429ze", + feature = "stm32f429zg", + feature = "stm32f429zi", + feature = "stm32f437ai", + feature = "stm32f437ig", + feature = "stm32f437ii", + feature = "stm32f437vg", + feature = "stm32f437vi", + feature = "stm32f437zg", + feature = "stm32f437zi", + feature = "stm32f439ai", + feature = "stm32f439bg", + feature = "stm32f439bi", + feature = "stm32f439ig", + feature = "stm32f439ii", + feature = "stm32f439ng", + feature = "stm32f439ni", + feature = "stm32f439vg", + feature = "stm32f439vi", + feature = "stm32f439zg", + feature = "stm32f439zi", + feature = "stm32f446mc", + feature = "stm32f446me", + feature = "stm32f446rc", + feature = "stm32f446re", + feature = "stm32f446vc", + feature = "stm32f446ve", + feature = "stm32f446zc", + feature = "stm32f446ze", + feature = "stm32f469ae", + feature = "stm32f469ag", + feature = "stm32f469ai", + feature = "stm32f469be", + feature = "stm32f469bg", + feature = "stm32f469bi", + feature = "stm32f469ie", + feature = "stm32f469ig", + feature = "stm32f469ii", + feature = "stm32f469ne", + feature = "stm32f469ng", + feature = "stm32f469ni", + feature = "stm32f469ve", + feature = "stm32f469vg", + feature = "stm32f469vi", + feature = "stm32f469ze", + feature = "stm32f469zg", + feature = "stm32f469zi", + feature = "stm32f479ag", + feature = "stm32f479ai", + feature = "stm32f479bg", + feature = "stm32f479bi", + feature = "stm32f479ig", + feature = "stm32f479ii", + feature = "stm32f479ng", + feature = "stm32f479ni", + feature = "stm32f479vg", + feature = "stm32f479vi", + feature = "stm32f479zg", + feature = "stm32f479zi", +))] +pub(crate) const SYSCLK_MAX: u32 = 180_000_000; + +#[cfg(any( + feature = "stm32f401cb", + feature = "stm32f401cc", + feature = "stm32f401cd", + feature = "stm32f401ce", + feature = "stm32f401rb", + feature = "stm32f401rc", + feature = "stm32f401rd", + feature = "stm32f401re", + feature = "stm32f401vb", + feature = "stm32f401vc", + feature = "stm32f401vd", + feature = "stm32f401ve", + feature = "stm32f410c8", + feature = "stm32f410cb", + feature = "stm32f410r8", + feature = "stm32f410rb", + feature = "stm32f410t8", + feature = "stm32f410tb", + feature = "stm32f411cc", + feature = "stm32f411ce", + feature = "stm32f411rc", + feature = "stm32f411re", + feature = "stm32f411vc", + feature = "stm32f411ve", + feature = "stm32f412ce", + feature = "stm32f412cg", + feature = "stm32f412re", + feature = "stm32f412rg", + feature = "stm32f412ve", + feature = "stm32f412vg", + feature = "stm32f412ze", + feature = "stm32f412zg", + feature = "stm32f413cg", + feature = "stm32f413ch", + feature = "stm32f413mg", + feature = "stm32f413mh", + feature = "stm32f413rg", + feature = "stm32f413rh", + feature = "stm32f413vg", + feature = "stm32f413vh", + feature = "stm32f413zg", + feature = "stm32f413zh", + feature = "stm32f423ch", + feature = "stm32f423mh", + feature = "stm32f423rh", + feature = "stm32f423vh", + feature = "stm32f423zh", +))] +pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX; + +#[cfg(not(any( + feature = "stm32f401cb", + feature = "stm32f401cc", + feature = "stm32f401cd", + feature = "stm32f401ce", + feature = "stm32f401rb", + feature = "stm32f401rc", + feature = "stm32f401rd", + feature = "stm32f401re", + feature = "stm32f401vb", + feature = "stm32f401vc", + feature = "stm32f401vd", + feature = "stm32f401ve", + feature = "stm32f410c8", + feature = "stm32f410cb", + feature = "stm32f410r8", + feature = "stm32f410rb", + feature = "stm32f410t8", + feature = "stm32f410tb", + feature = "stm32f411cc", + feature = "stm32f411ce", + feature = "stm32f411rc", + feature = "stm32f411re", + feature = "stm32f411vc", + feature = "stm32f411ve", + feature = "stm32f412ce", + feature = "stm32f412cg", + feature = "stm32f412re", + feature = "stm32f412rg", + feature = "stm32f412ve", + feature = "stm32f412vg", + feature = "stm32f412ze", + feature = "stm32f412zg", + feature = "stm32f413cg", + feature = "stm32f413ch", + feature = "stm32f413mg", + feature = "stm32f413mh", + feature = "stm32f413rg", + feature = "stm32f413rh", + feature = "stm32f413vg", + feature = "stm32f413vh", + feature = "stm32f413zg", + feature = "stm32f413zh", + feature = "stm32f423ch", + feature = "stm32f423mh", + feature = "stm32f423rh", + feature = "stm32f423vh", + feature = "stm32f423zh", +)))] +pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2; + +pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2; diff --git a/embassy-stm32/src/rcc/f4/mod.rs b/embassy-stm32/src/rcc/f4/mod.rs index a5773ec1..0962d252 100644 --- a/embassy-stm32/src/rcc/f4/mod.rs +++ b/embassy-stm32/src/rcc/f4/mod.rs @@ -5,13 +5,10 @@ use crate::time::Hertz; use core::marker::PhantomData; use embassy::util::Unborrow; -const HSI: u32 = 16_000_000; +mod max; +use max::{PCLK1_MAX, PCLK2_MAX}; -// TODO: This is for the F401, find a way to make it compile time configurable -const SYSCLK_MIN: u32 = 24_000_000; -const SYSCLK_MAX: u32 = 84_000_000; -const PCLK2_MAX: u32 = SYSCLK_MAX; -const PCLK1_MAX: u32 = PCLK2_MAX / 2; +const HSI: u32 = 16_000_000; /// Clocks configutation #[non_exhaustive] @@ -69,7 +66,6 @@ impl<'d> Rcc<'d> { } else { sysclk }; - assert!((SYSCLK_MIN..=SYSCLK_MAX).contains(&sysclk), "sysclk"); let hclk = self.config.hclk.map(|h| h.0).unwrap_or(sysclk); let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk { @@ -247,7 +243,7 @@ impl<'d> Rcc<'d> { .unwrap(); let vco_in = pllsrcclk / pllm; - assert!((1_000_000..=2_000_000).contains(&vco_in), "vco_in"); + assert!((1_000_000..=2_000_000).contains(&vco_in)); // Main scaler, must result in >= 100MHz (>= 192MHz for F401) // and <= 432MHz, min 50, max 432 @@ -266,10 +262,6 @@ impl<'d> Rcc<'d> { } else { sysclk * sysclk_div / vco_in }; - assert!( - (192_000_000..=432_000_000).contains(&(vco_in * plln)), - "plln" - ); let pllp = (sysclk_div / 2) - 1; diff --git a/examples/stm32f4/src/bin/hello.rs b/examples/stm32f4/src/bin/hello.rs index 8d4be715..8ee6c1ef 100644 --- a/examples/stm32f4/src/bin/hello.rs +++ b/examples/stm32f4/src/bin/hello.rs @@ -19,7 +19,7 @@ mod example_common; fn config() -> Config { let mut rcc_config = RccConfig::default(); - rcc_config.sys_ck = Some(Hertz(32_000_000)); + rcc_config.sys_ck = Some(Hertz(84_000_000)); rcc_config.enable_debug_wfe = true; Config::default().rcc(rcc_config)