issue #1986 separate blocks to prevent unsafe user code
This commit is contained in:
Tyler Gilbert
parent
d42cfda2db
commit
5dd9e9b3b7
@ -502,7 +502,7 @@ impl Config {
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}
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#[derive(Copy, Clone)]
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pub enum SubBlock {
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enum WhichSubBlock {
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A = 0,
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B = 1,
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}
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@ -513,28 +513,30 @@ enum RingBuffer<'d, C: Channel, W: word::Word> {
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}
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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fn wdr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: SubBlock) -> *mut W {
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fn dr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: WhichSubBlock) -> *mut W {
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let ch = w.ch(sub_block as usize);
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ch.dr().as_ptr() as _
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}
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#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
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fn rdr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: SubBlock) -> *mut W {
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let ch = w.ch(sub_block as usize);
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ch.dr().as_ptr() as _
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}
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pub struct Sai<'d, T: Instance, C: Channel, W: word::Word> {
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pub struct SubBlock<'d, T: Instance, C: Channel, W: word::Word> {
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_peri: PeripheralRef<'d, T>,
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sd: Option<PeripheralRef<'d, AnyPin>>,
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fs: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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mclk: Option<PeripheralRef<'d, AnyPin>>,
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ring_buffer: RingBuffer<'d, C, W>,
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sub_block: SubBlock,
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sub_block: WhichSubBlock,
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}
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pub struct SubBlockA {}
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pub struct SubBlockB {}
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pub struct Sai<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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sub_block_a_peri: Option<PeripheralRef<'d, T>>,
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sub_block_b_peri: Option<PeripheralRef<'d, T>>,
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}
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impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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// return the type for (sd, sck)
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fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AFType, AFType) {
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(
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@ -551,11 +553,11 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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)
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}
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fn get_ring_buffer(
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fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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request: Request,
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sub_block: SubBlock,
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sub_block: WhichSubBlock,
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tx_rx: TxRx,
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) -> RingBuffer<'d, C, W> {
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let opts = TransferOptions {
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@ -565,143 +567,41 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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};
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match tx_rx {
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TxRx::Transmitter => RingBuffer::Writable(unsafe {
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WritableRingBuffer::new_write(dma, request, wdr(T::REGS, sub_block), dma_buf, opts)
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WritableRingBuffer::new_write(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
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}),
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TxRx::Receiver => RingBuffer::Readable(unsafe {
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ReadableRingBuffer::new_read(dma, request, rdr(T::REGS, sub_block), dma_buf, opts)
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ReadableRingBuffer::new_read(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
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}),
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}
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}
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pub fn new_asynchronous_block_a_with_mclk(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
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mclk: impl Peripheral<P = impl MclkAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> Self
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(mclk);
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impl<'d, T: Instance> Sai<'d, T> {
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pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
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T::enable();
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T::reset();
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let (_sd_af_type, ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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Self {
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_peri: unsafe { peri.clone_unchecked().into_ref() },
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sub_block_a_peri: Some(unsafe { peri.clone_unchecked().into_ref() }),
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sub_block_b_peri: Some(peri.into_ref()),
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}
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}
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Self::new_asynchronous_block_a(peri, sck, sd, fs, dma, dma_buf, config)
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pub fn take_sub_block_a(self: &mut Self) -> Option<PeripheralRef<'d, T>> {
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if self.sub_block_a_peri.is_some() {
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self.sub_block_a_peri.take()
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} else {
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None
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}
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}
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pub fn new_asynchronous_block_a(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> Self
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(peri, dma, sck, sd, fs);
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let (sd_af_type, ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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sck.set_as_af(sck.af_num(), ck_af_type);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = SubBlock::A;
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let request = dma.request();
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Self::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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Self::get_ring_buffer(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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pub fn take_sub_block_b(self: &mut Self) -> Option<PeripheralRef<'d, T>> {
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if self.sub_block_b_peri.is_some() {
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self.sub_block_b_peri.take()
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} else {
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None
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}
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pub fn new_asynchronous_block_b_with_mclk(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
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mclk: impl Peripheral<P = impl MclkBPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> Self
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(mclk);
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let (_sd_af_type, ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous_block_b(peri, sck, sd, fs, dma, dma_buf, config)
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}
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pub fn new_asynchronous_block_b(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> Self
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(dma, peri, sck, sd, fs);
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let (sd_af_type, ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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sck.set_as_af(sck.af_num(), ck_af_type);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = SubBlock::B;
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let request = dma.request();
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Self::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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Self::get_ring_buffer(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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fn update_synchronous_config(config: &mut Config) {
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@ -721,74 +621,210 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
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}
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}
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pub fn new_synchronous_block_a(
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impl SubBlockA {
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pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
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mclk: impl Peripheral<P = impl MclkAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(mclk);
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let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
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}
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pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckAPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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into_ref!(peri, dma, sck, sd, fs);
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let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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sck.set_as_af(sck.af_num(), ck_af_type);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::A;
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let request = dma.request();
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SubBlock::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl SdAPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> Self
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaA<T>,
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{
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Self::update_synchronous_config(&mut config);
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update_synchronous_config(&mut config);
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into_ref!(dma, peri, sd);
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let (sd_af_type, _ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
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let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = SubBlock::A;
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let sub_block = WhichSubBlock::A;
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let request = dma.request();
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Self::new_inner(
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SubBlock::new_inner(
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peri,
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sub_block,
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None,
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None,
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Some(sd.map_into()),
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None,
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Self::get_ring_buffer(dma, dma_buf, request, sub_block, config.tx_rx),
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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}
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impl SubBlockB {
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pub fn new_asynchronous_with_mclk<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
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mclk: impl Peripheral<P = impl MclkBPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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mut config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(mclk);
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let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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mclk.set_speed(crate::gpio::Speed::VeryHigh);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
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}
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pub fn new_asynchronous<'d, T: Instance, C: Channel, W: word::Word>(
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peri: impl Peripheral<P = T> + 'd,
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sck: impl Peripheral<P = impl SckBPin<T>> + 'd,
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sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
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fs: impl Peripheral<P = impl FsBPin<T>> + 'd,
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dma: impl Peripheral<P = C> + 'd,
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dma_buf: &'d mut [W],
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config: Config,
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) -> SubBlock<T, C, W>
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where
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C: Channel + DmaB<T>,
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{
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into_ref!(dma, peri, sck, sd, fs);
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let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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sd.set_as_af(sd.af_num(), sd_af_type);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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sck.set_as_af(sck.af_num(), ck_af_type);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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fs.set_as_af(fs.af_num(), ck_af_type);
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fs.set_speed(crate::gpio::Speed::VeryHigh);
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let sub_block = WhichSubBlock::B;
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let request = dma.request();
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SubBlock::new_inner(
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peri,
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sub_block,
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Some(sck.map_into()),
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None,
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Some(sd.map_into()),
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Some(fs.map_into()),
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get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
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config,
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)
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}
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pub fn new_synchronous_block_b(
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pub fn new_synchronous<'d, T: Instance, C: Channel, W: word::Word>(
|
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peri: impl Peripheral<P = T> + 'd,
|
||||
sd: impl Peripheral<P = impl SdBPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = C> + 'd,
|
||||
dma_buf: &'d mut [W],
|
||||
mut config: Config,
|
||||
) -> Self
|
||||
) -> SubBlock<T, C, W>
|
||||
where
|
||||
C: Channel + DmaB<T>,
|
||||
{
|
||||
Self::update_synchronous_config(&mut config);
|
||||
update_synchronous_config(&mut config);
|
||||
|
||||
into_ref!(dma, peri, sd);
|
||||
|
||||
let (sd_af_type, _ck_af_type) = Self::get_af_types(config.mode, config.tx_rx);
|
||||
let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
|
||||
|
||||
sd.set_as_af(sd.af_num(), sd_af_type);
|
||||
sd.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
let sub_block = SubBlock::B;
|
||||
let sub_block = WhichSubBlock::B;
|
||||
let request = dma.request();
|
||||
|
||||
Self::new_inner(
|
||||
SubBlock::new_inner(
|
||||
peri,
|
||||
sub_block,
|
||||
None,
|
||||
None,
|
||||
Some(sd.map_into()),
|
||||
None,
|
||||
Self::get_ring_buffer(dma, dma_buf, request, sub_block, config.tx_rx),
|
||||
get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
|
||||
config,
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> {
|
||||
pub fn start(self: &mut Self) {
|
||||
match self.ring_buffer {
|
||||
RingBuffer::Writable(ref mut rb) => {
|
||||
@ -809,7 +845,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
sub_block: SubBlock,
|
||||
sub_block: WhichSubBlock,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
mclk: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sd: Option<PeripheralRef<'d, AnyPin>>,
|
||||
@ -974,7 +1010,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for Sai<'d, T, C, W> {
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> Drop for SubBlock<'d, T, C, W> {
|
||||
fn drop(&mut self) {
|
||||
let ch = T::REGS.ch(self.sub_block as usize);
|
||||
ch.cr1().modify(|w| w.set_saien(false));
|
||||
@ -1018,9 +1054,9 @@ foreach_peripheral!(
|
||||
};
|
||||
);
|
||||
|
||||
impl<'d, T: Instance, C: Channel, W: word::Word> SetConfig for Sai<'d, T, C, W> {
|
||||
impl<'d, T: Instance> SetConfig for Sai<'d, T> {
|
||||
type Config = Config;
|
||||
fn set_config(&mut self, config: &Self::Config) {
|
||||
self.reconfigure(*config);
|
||||
// self.reconfigure(*config);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user