Add wb55 clocks

embassy-stm32/src/rcc/f4/mod.rs

@@ -191,6 +191,7 @@ impl RccExt for RCC {
             sys: sys_clk.hz(),
             ahb1: ahb_freq.hz(),
             ahb2: ahb_freq.hz(),
+            ahb3: ahb_freq.hz(),
             apb1: apb1_freq.hz(),
             apb2: apb2_freq.hz(),
         }

embassy-stm32/src/rcc/h7/mod.rs

@@ -531,6 +531,7 @@ pub unsafe fn init(config: Config) {
         sys: core_clocks.c_ck,
         ahb1: core_clocks.hclk,
         ahb2: core_clocks.hclk,
+        ahb3: core_clocks.hclk,
         apb1: core_clocks.pclk1,
         apb2: core_clocks.pclk2,
         apb4: core_clocks.pclk4,

embassy-stm32/src/rcc/l4/mod.rs

@@ -190,6 +190,7 @@ impl RccExt for RCC {
             sys: sys_clk.hz(),
             ahb1: ahb_freq.hz(),
             ahb2: ahb_freq.hz(),
+            ahb3: ahb_freq.hz(),
             apb1: apb1_freq.hz(),
             apb2: apb2_freq.hz(),
         }

embassy-stm32/src/rcc/mod.rs

@@ -14,12 +14,15 @@ pub struct Clocks {
     #[cfg(any(rcc_l0))]
     pub ahb: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_h7))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
     pub ahb1: Hertz,
 
-    #[cfg(any(rcc_l4, rcc_f4, rcc_h7))]
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
     pub ahb2: Hertz,
 
+    #[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb55))]
+    pub ahb3: Hertz,
+
     #[cfg(any(rcc_h7))]
     pub apb4: Hertz,
 }
@@ -54,6 +57,9 @@ cfg_if::cfg_if! {
     } else if #[cfg(rcc_f4)] {
         mod f4;
         pub use f4::*;
+    } else if #[cfg(rcc_wb55)] {
+        mod wb55;
+        pub use wb55::*;
     } else {
         #[derive(Default)]
         pub struct Config {}

embassy-stm32/src/rcc/wb55/mod.rs

@@ -0,0 +1,204 @@
+pub use super::types::*;
+use crate::pac;
+use crate::peripherals::{self, RCC};
+use crate::rcc::{get_freqs, set_freqs, Clocks};
+use crate::time::Hertz;
+use crate::time::U32Ext;
+use core::marker::PhantomData;
+use embassy::util::Unborrow;
+use embassy_extras::unborrow;
+
+/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
+/// and with the addition of the init function to configure a system clock.
+
+/// Only the basic setup using the HSE and HSI clocks are supported as of now.
+
+/// HSI speed
+pub const HSI_FREQ: u32 = 16_000_000;
+
+/// System clock mux source
+#[derive(Clone, Copy)]
+pub enum ClockSrc {
+    HSE(Hertz),
+    HSI16,
+}
+
+impl Into<u8> for APBPrescaler {
+    fn into(self) -> u8 {
+        match self {
+            APBPrescaler::NotDivided => 1,
+            APBPrescaler::Div2 => 0x04,
+            APBPrescaler::Div4 => 0x05,
+            APBPrescaler::Div8 => 0x06,
+            APBPrescaler::Div16 => 0x07,
+        }
+    }
+}
+
+impl Into<u8> for AHBPrescaler {
+    fn into(self) -> u8 {
+        match self {
+            AHBPrescaler::NotDivided => 1,
+            AHBPrescaler::Div2 => 0x08,
+            AHBPrescaler::Div4 => 0x09,
+            AHBPrescaler::Div8 => 0x0a,
+            AHBPrescaler::Div16 => 0x0b,
+            AHBPrescaler::Div64 => 0x0c,
+            AHBPrescaler::Div128 => 0x0d,
+            AHBPrescaler::Div256 => 0x0e,
+            AHBPrescaler::Div512 => 0x0f,
+        }
+    }
+}
+
+/// Clocks configutation
+pub struct Config {
+    mux: ClockSrc,
+    ahb_pre: AHBPrescaler,
+    apb1_pre: APBPrescaler,
+    apb2_pre: APBPrescaler,
+}
+
+impl Default for Config {
+    #[inline]
+    fn default() -> Config {
+        Config {
+            mux: ClockSrc::HSI16,
+            ahb_pre: AHBPrescaler::NotDivided,
+            apb1_pre: APBPrescaler::NotDivided,
+            apb2_pre: APBPrescaler::NotDivided,
+        }
+    }
+}
+
+impl Config {
+    #[inline]
+    pub fn clock_src(mut self, mux: ClockSrc) -> Self {
+        self.mux = mux;
+        self
+    }
+
+    #[inline]
+    pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
+        self.ahb_pre = pre;
+        self
+    }
+
+    #[inline]
+    pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
+        self.apb1_pre = pre;
+        self
+    }
+
+    #[inline]
+    pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
+        self.apb2_pre = pre;
+        self
+    }
+}
+
+/// RCC peripheral
+pub struct Rcc<'d> {
+    _rb: peripherals::RCC,
+    phantom: PhantomData<&'d mut peripherals::RCC>,
+}
+
+impl<'d> Rcc<'d> {
+    pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
+        unborrow!(rcc);
+        Self {
+            _rb: rcc,
+            phantom: PhantomData,
+        }
+    }
+
+    // Safety: RCC init must have been called
+    pub fn clocks(&self) -> &'static Clocks {
+        unsafe { get_freqs() }
+    }
+}
+
+/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
+pub trait RccExt {
+    fn freeze(self, config: Config) -> Clocks;
+}
+
+impl RccExt for RCC {
+    #[inline]
+    fn freeze(self, cfgr: Config) -> Clocks {
+        let rcc = pac::RCC;
+        let (sys_clk, sw) = match cfgr.mux {
+            ClockSrc::HSI16 => {
+                // Enable HSI16
+                unsafe {
+                    rcc.cr().write(|w| w.set_hsion(true));
+                    while !rcc.cr().read().hsirdy() {}
+                }
+
+                (HSI_FREQ, 0x01)
+            }
+            ClockSrc::HSE(freq) => {
+                // Enable HSE
+                unsafe {
+                    rcc.cr().write(|w| w.set_hseon(true));
+                    while !rcc.cr().read().hserdy() {}
+                }
+
+                (freq.0, 0x02)
+            }
+        };
+
+        unsafe {
+            rcc.cfgr().modify(|w| {
+                w.set_sw(sw.into());
+                w.set_hpre(cfgr.ahb_pre.into());
+                w.set_ppre1(cfgr.apb1_pre.into());
+                w.set_ppre2(cfgr.apb2_pre.into());
+            });
+        }
+
+        let ahb_freq: u32 = match cfgr.ahb_pre {
+            AHBPrescaler::NotDivided => sys_clk,
+            pre => {
+                let pre: u8 = pre.into();
+                let pre = 1 << (pre as u32 - 7);
+                sys_clk / pre
+            }
+        };
+
+        let apb1_freq = match cfgr.apb1_pre {
+            APBPrescaler::NotDivided => ahb_freq,
+            pre => {
+                let pre: u8 = pre.into();
+                let pre: u8 = 1 << (pre - 3);
+                let freq = ahb_freq / pre as u32;
+                freq
+            }
+        };
+
+        let apb2_freq = match cfgr.apb2_pre {
+            APBPrescaler::NotDivided => ahb_freq,
+            pre => {
+                let pre: u8 = pre.into();
+                let pre: u8 = 1 << (pre - 3);
+                let freq = ahb_freq / (1 << (pre as u8 - 3));
+                freq
+            }
+        };
+
+        Clocks {
+            sys: sys_clk.hz(),
+            ahb1: ahb_freq.hz(),
+            ahb2: ahb_freq.hz(),
+            ahb3: ahb_freq.hz(),
+            apb1: apb1_freq.hz(),
+            apb2: apb2_freq.hz(),
+        }
+    }
+}
+
+pub unsafe fn init(config: Config) {
+    let r = <peripherals::RCC as embassy::util::Steal>::steal();
+    let clocks = r.freeze(config);
+    set_freqs(clocks);
+}

stm32-metapac/gen/src/lib.rs

@@ -86,7 +86,7 @@ fn find_reg_for_field<'c>(
     rcc.fieldsets.iter().find_map(|(name, fieldset)| {
         // Workaround for some families that prefix register aliases with C1_, which does
         // not help matching for clock name.
-        if name.starts_with("C1") {
+        if name.starts_with("C1") || name.starts_with("C2") {
             None
         } else if name.starts_with(reg_prefix) {
             fieldset