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Merge v1, v2 DAC and update register definitions

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This commit is contained in:
chemicstry
2022-08-04 03:02:57 +03:00
parent 1924f2d67d
commit 5f01e56728
6 changed files with 119 additions and 105 deletions
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145
embassy-stm32/src/dac/v2.rs → embassy-stm32/src/dac.rs
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@ -1,8 +1,10 @@
#![macro_use]
use cfg_if::cfg_if;
use embassy_hal_common::{into_ref, PeripheralRef};
use crate::dac::{DacPin, Instance};
use crate::pac::dac;
use crate::Peripheral;
use crate::{peripherals, Peripheral};
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -18,6 +20,15 @@ pub enum Channel {
Ch2,
}
impl Channel {
fn index(&self) -> usize {
match self {
Channel::Ch1 => 0,
Channel::Ch2 => 1,
}
}
}
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ch1Trigger {
@ -119,27 +130,28 @@ impl<'d, T: Instance> Dac<'d, T> {
// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent DAC clock
// configuration.
critical_section::with(|_| {
#[cfg(rcc_h7)]
enable!(apb1lenr, set_dac12en, apb1lrstr, set_dac12rst);
#[cfg(rcc_h7ab)]
enable!(apb1lenr, set_dac1en, apb1lrstr, set_dac1rst);
#[cfg(stm32g0)]
enable!(apbenr1, set_dac1en, apbrstr1, set_dac1rst);
#[cfg(any(stm32l4, stm32l5))]
enable!(apb1enr1, set_dac1en, apb1rstr1, set_dac1rst);
cfg_if! {
if #[cfg(rcc_f1)] {
enable!(apb1enr, set_dacen, apb1rstr, set_dacrst);
} else if #[cfg(rcc_h7)] {
enable!(apb1lenr, set_dac12en, apb1lrstr, set_dac12rst);
} else if #[cfg(rcc_h7ab)] {
enable!(apb1lenr, set_dac1en, apb1lrstr, set_dac1rst);
} else if #[cfg(stm32g0)] {
enable!(apbenr1, set_dac1en, apbrstr1, set_dac1rst);
} else if #[cfg(any(stm32l4, stm32l5))] {
enable!(apb1enr1, set_dac1en, apb1rstr1, set_dac1rst);
} else {
unimplemented!("DAC enable/reset is not yet implemented for this chip");
}
}
});
if channels >= 1 {
T::regs().cr().modify(|reg| {
reg.set_en1(true);
});
}
if channels >= 2 {
T::regs().cr().modify(|reg| {
reg.set_en2(true);
});
}
T::regs().cr().modify(|reg| {
for ch in 0..channels {
reg.set_en(ch as usize, true);
}
});
}
Self { channels, _peri: peri }
@ -156,17 +168,10 @@ impl<'d, T: Instance> Dac<'d, T> {
fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
self.check_channel_exists(ch)?;
match ch {
Channel::Ch1 => unsafe {
T::regs().cr().modify(|reg| {
reg.set_en1(on);
})
},
Channel::Ch2 => unsafe {
T::regs().cr().modify(|reg| {
reg.set_en2(on);
});
},
unsafe {
T::regs().cr().modify(|reg| {
reg.set_en(ch.index(), on);
})
}
Ok(())
}
@ -203,17 +208,10 @@ impl<'d, T: Instance> Dac<'d, T> {
pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
self.check_channel_exists(ch)?;
match ch {
Channel::Ch1 => unsafe {
T::regs().swtrigr().write(|reg| {
reg.set_swtrig1(true);
});
},
Channel::Ch2 => unsafe {
T::regs().swtrigr().write(|reg| {
reg.set_swtrig2(true);
})
},
unsafe {
T::regs().swtrigr().write(|reg| {
reg.set_swtrig(ch.index(), true);
});
}
Ok(())
}
@ -221,38 +219,53 @@ impl<'d, T: Instance> Dac<'d, T> {
pub fn trigger_all(&mut self) {
unsafe {
T::regs().swtrigr().write(|reg| {
reg.set_swtrig1(true);
reg.set_swtrig2(true);
reg.set_swtrig(Channel::Ch1.index(), true);
reg.set_swtrig(Channel::Ch2.index(), true);
})
}
}
pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
self.check_channel_exists(ch)?;
match ch {
Channel::Ch1 => match value {
Value::Bit8(v) => unsafe {
T::regs().dhr8r1().write(|reg| reg.set_dacc1dhr(v));
},
Value::Bit12(v, Alignment::Left) => unsafe {
T::regs().dhr12l1().write(|reg| reg.set_dacc1dhr(v));
},
Value::Bit12(v, Alignment::Right) => unsafe {
T::regs().dhr12r1().write(|reg| reg.set_dacc1dhr(v));
},
match value {
Value::Bit8(v) => unsafe {
T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v));
},
Channel::Ch2 => match value {
Value::Bit8(v) => unsafe {
T::regs().dhr8r2().write(|reg| reg.set_dacc2dhr(v));
},
Value::Bit12(v, Alignment::Left) => unsafe {
T::regs().dhr12l2().write(|reg| reg.set_dacc2dhr(v));
},
Value::Bit12(v, Alignment::Right) => unsafe {
T::regs().dhr12r2().write(|reg| reg.set_dacc2dhr(v));
},
Value::Bit12(v, Alignment::Left) => unsafe {
T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v));
},
Value::Bit12(v, Alignment::Right) => unsafe {
T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v));
},
}
Ok(())
}
}
pub(crate) mod sealed {
pub trait Instance {
fn regs() -> &'static crate::pac::dac::Dac;
}
}
pub trait Instance: sealed::Instance + 'static {}
pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
foreach_peripheral!(
(dac, $inst:ident) => {
impl crate::dac::sealed::Instance for peripherals::$inst {
fn regs() -> &'static crate::pac::dac::Dac {
&crate::pac::$inst
}
}
impl crate::dac::Instance for peripherals::$inst {}
};
);
macro_rules! impl_dac_pin {
($inst:ident, $pin:ident, $ch:expr) => {
impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
};
}

36
embassy-stm32/src/dac/mod.rs
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@ -1,36 +0,0 @@
#![macro_use]
#[cfg_attr(dac_v1, path = "v1.rs")]
#[cfg_attr(dac_v2, path = "v2.rs")]
mod _version;
pub use _version::*;
use crate::peripherals;
pub(crate) mod sealed {
pub trait Instance {
fn regs() -> &'static crate::pac::dac::Dac;
}
}
pub trait Instance: sealed::Instance + 'static {}
pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
foreach_peripheral!(
(dac, $inst:ident) => {
impl crate::dac::sealed::Instance for peripherals::$inst {
fn regs() -> &'static crate::pac::dac::Dac {
&crate::pac::$inst
}
}
impl crate::dac::Instance for peripherals::$inst {}
};
);
macro_rules! impl_dac_pin {
($inst:ident, $pin:ident, $ch:expr) => {
impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
};
}

1
embassy-stm32/src/dac/v1.rs
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@ -1 +0,0 @@