rp/pio: only clear diag bits if they're set
otherwise we may lose a bit being raised after it was read, but before it was cleared.
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ed843b519b
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5f7ef8bed0
@ -307,7 +307,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
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unsafe {
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unsafe {
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let fdebug = PIO::PIO.fdebug();
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let fdebug = PIO::PIO.fdebug();
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let ret = fdebug.read().rxstall() & (1 << SM) != 0;
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let ret = fdebug.read().rxstall() & (1 << SM) != 0;
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if ret {
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fdebug.write(|w| w.set_rxstall(1 << SM));
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fdebug.write(|w| w.set_rxstall(1 << SM));
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}
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ret
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ret
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}
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}
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}
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}
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@ -316,7 +318,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
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unsafe {
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unsafe {
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let fdebug = PIO::PIO.fdebug();
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let fdebug = PIO::PIO.fdebug();
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let ret = fdebug.read().rxunder() & (1 << SM) != 0;
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let ret = fdebug.read().rxunder() & (1 << SM) != 0;
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if ret {
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fdebug.write(|w| w.set_rxunder(1 << SM));
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fdebug.write(|w| w.set_rxunder(1 << SM));
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}
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ret
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ret
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}
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}
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}
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}
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@ -383,7 +387,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
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unsafe {
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unsafe {
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let fdebug = PIO::PIO.fdebug();
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let fdebug = PIO::PIO.fdebug();
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let ret = fdebug.read().txstall() & (1 << SM) != 0;
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let ret = fdebug.read().txstall() & (1 << SM) != 0;
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if ret {
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fdebug.write(|w| w.set_txstall(1 << SM));
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fdebug.write(|w| w.set_txstall(1 << SM));
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}
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ret
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ret
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}
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}
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}
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}
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@ -392,7 +398,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
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unsafe {
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unsafe {
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let fdebug = PIO::PIO.fdebug();
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let fdebug = PIO::PIO.fdebug();
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let ret = fdebug.read().txover() & (1 << SM) != 0;
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let ret = fdebug.read().txover() & (1 << SM) != 0;
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if ret {
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fdebug.write(|w| w.set_txover(1 << SM));
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fdebug.write(|w| w.set_txover(1 << SM));
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}
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ret
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ret
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}
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}
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}
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}
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