stm32: add H5 support.
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@ -9,7 +9,7 @@ pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
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use super::*;
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::{AnyPin, Speed};
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use crate::pac::{ETH, RCC, SYSCFG};
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use crate::pac::ETH;
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use crate::Peripheral;
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const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
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@ -60,16 +60,33 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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unsafe {
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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#[cfg(not(rcc_h5))]
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critical_section::with(|_| {
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RCC.apb4enr().modify(|w| w.set_syscfgen(true));
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RCC.ahb1enr().modify(|w| {
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crate::pac::RCC.apb4enr().modify(|w| w.set_syscfgen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_eth1macen(true);
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w.set_eth1txen(true);
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w.set_eth1rxen(true);
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});
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// RMII
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SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
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crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
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});
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#[cfg(rcc_h5)]
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critical_section::with(|_| {
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crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII
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crate::pac::SBS
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.pmcr()
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.modify(|w| w.set_eth_sel_phy(crate::pac::sbs::vals::EthSelPhy::B_0X4));
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});
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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