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stm32: add H5 support.

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This commit is contained in:
Dario Nieuwenhuis
2023-04-06 18:53:51 +02:00
parent 9f28d80977
commit 611d023829
22 changed files with 1390 additions and 21 deletions
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18
embassy-stm32/src/exti.rs
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@ -25,11 +25,11 @@ fn cpu_regs() -> pac::exti::Exti {
EXTI
}
#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
fn exticr_regs() -> pac::syscfg::Syscfg {
pac::SYSCFG
}
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
fn exticr_regs() -> pac::exti::Exti {
EXTI
}
@ -39,9 +39,9 @@ fn exticr_regs() -> pac::afio::Afio {
}
pub unsafe fn on_irq() {
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
let bits = EXTI.pr(0).read().0;
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
// Mask all the channels that fired.
@ -53,9 +53,9 @@ pub unsafe fn on_irq() {
}
// Clear pending
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
EXTI.pr(0).write_value(Lines(bits));
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
{
EXTI.rpr(0).write_value(Lines(bits));
EXTI.fpr(0).write_value(Lines(bits));
@ -213,9 +213,9 @@ impl<'a> ExtiInputFuture<'a> {
EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
// clear pending bit
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
EXTI.pr(0).write(|w| w.set_line(pin, true));
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
{
EXTI.rpr(0).write(|w| w.set_line(pin, true));
EXTI.fpr(0).write(|w| w.set_line(pin, true));
@ -364,7 +364,7 @@ pub(crate) unsafe fn init() {
foreach_exti_irq!(enable_irq);
#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1)))]
#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1, exti_h5, exti_h50)))]
<crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable();
#[cfg(stm32f1)]
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();