stm32/rcc: use PLL enums from PAC.

This commit is contained in:
Dario Nieuwenhuis
2023-10-09 02:48:22 +02:00
parent c4cff0b79b
commit 6186fe0807
47 changed files with 599 additions and 1383 deletions

View File

@ -16,12 +16,12 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll {
source: PllSrc::HSI16,
prediv_m: PllM::Div4,
mul_n: PllN::Mul85,
prediv_m: PllM::DIV4,
mul_n: PllN::MUL85,
div_p: None,
div_q: None,
// Main system clock at 170 MHz
div_r: Some(PllR::Div2),
div_r: Some(PllR::DIV2),
});
config.rcc.adc12_clock_source = AdcClockSource::SysClk;

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@ -15,12 +15,12 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll {
source: PllSrc::HSI16,
prediv_m: PllM::Div4,
mul_n: PllN::Mul85,
prediv_m: PllM::DIV4,
mul_n: PllN::MUL85,
div_p: None,
div_q: None,
// Main system clock at 170 MHz
div_r: Some(PllR::Div2),
div_r: Some(PllR::DIV2),
});
config.rcc.mux = ClockSrc::PLL;

View File

@ -25,16 +25,16 @@ async fn main(_spawner: Spawner) {
// Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
const USE_HSI48: bool = true;
let pllq_div = if USE_HSI48 { None } else { Some(PllQ::Div6) };
let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
config.rcc.pll = Some(Pll {
source: PllSrc::HSE(Hertz(8_000_000)),
prediv_m: PllM::Div2,
mul_n: PllN::Mul72,
prediv_m: PllM::DIV2,
mul_n: PllN::MUL72,
div_p: None,
div_q: pllq_div,
// Main system clock at 144 MHz
div_r: Some(PllR::Div2),
div_r: Some(PllR::DIV2),
});
config.rcc.mux = ClockSrc::PLL;