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stm32/rcc: use PLL enums from PAC.

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This commit is contained in:
Dario Nieuwenhuis
2023-10-09 02:48:22 +02:00
parent c4cff0b79b
commit 6186fe0807
47 changed files with 599 additions and 1383 deletions
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14
examples/stm32h7/src/bin/adc.rs
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@ -18,16 +18,16 @@ async fn main(_spawner: Spawner) {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // SPI1 cksel defaults to pll1_q
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
divr: None,
});
config.rcc.pll2 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(8), // 100mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV8), // 100mhz
divq: None,
divr: None,
});

8
examples/stm32h7/src/bin/camera.rs
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@ -32,10 +32,10 @@ async fn main(_spawner: Spawner) {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // 100mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // 100mhz
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

14
examples/stm32h7/src/bin/dac.rs
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@ -20,16 +20,16 @@ fn main() -> ! {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // SPI1 cksel defaults to pll1_q
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // 100mhz
divr: None,
});
config.rcc.pll2 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(8), // 100mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV8), // 100mhz
divq: None,
divr: None,
});

14
examples/stm32h7/src/bin/dac_dma.rs
View File

@ -28,16 +28,16 @@ async fn main(spawner: Spawner) {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // SPI1 cksel defaults to pll1_q
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // 100mhz
divr: None,
});
config.rcc.pll2 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(8), // 100mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV8), // 100mhz
divq: None,
divr: None,
});

6
examples/stm32h7/src/bin/eth.rs
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@ -39,9 +39,9 @@ async fn main(spawner: Spawner) -> ! {
config.rcc.hsi48 = true; // needed for RNG
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: None,
divr: None,
});

6
examples/stm32h7/src/bin/eth_client.rs
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@ -40,9 +40,9 @@ async fn main(spawner: Spawner) -> ! {
config.rcc.hsi48 = true; // needed for RNG
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: None,
divr: None,
});

8
examples/stm32h7/src/bin/fmc.rs
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@ -18,10 +18,10 @@ async fn main(_spawner: Spawner) {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // 100mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // 100mhz
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

8
examples/stm32h7/src/bin/low_level_timer_api.rs
View File

@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) {
config.rcc.hsi48 = true; // needed for RNG
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(8), // 100 Mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // 100mhz
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

6
examples/stm32h7/src/bin/pwm.rs
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@ -21,9 +21,9 @@ async fn main(_spawner: Spawner) {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: None,
divr: None,
});

8
examples/stm32h7/src/bin/sdmmc.rs
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@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) -> ! {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(4), // default clock chosen by SDMMCSEL. 200 Mhz
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

8
examples/stm32h7/src/bin/spi.rs
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@ -44,10 +44,10 @@ fn main() -> ! {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(4), // used by SPI3. 100Mhz.
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

8
examples/stm32h7/src/bin/spi_dma.rs
View File

@ -40,10 +40,10 @@ fn main() -> ! {
config.rcc.csi = true;
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
divq: Some(4), // used by SPI3. 100Mhz.
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
divr: None,
});
config.rcc.sys = Sysclk::Pll1P; // 400 Mhz

6
examples/stm32h7/src/bin/usb_serial.rs
View File

@ -28,9 +28,9 @@ async fn main(_spawner: Spawner) {
config.rcc.hsi48 = true; // needed for USB
config.rcc.pll_src = PllSource::Hsi;
config.rcc.pll1 = Some(Pll {
prediv: 4,
mul: 50,
divp: Some(2),
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL50,
divp: Some(PllDiv::DIV2),
divq: None,
divr: None,
});