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stm32wl: Do not require external SPI pins for SUBGHZ

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For the Seeed Studio Lora-E5 those pins conflict with the radio frontend control GPIOS (PA4 and PA5).
This commit is contained in:
Timo Kröger
2022-06-24 14:31:30 +02:00
parent 24ab21a7dd
commit 61c666212f
4 changed files with 16 additions and 7 deletions
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12
embassy-stm32/src/spi/mod.rs
View File

@ -179,6 +179,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
)
}
/// Useful for on chip peripherals like SUBGHZ which are hardwired.
/// The bus can optionally be exposed externally with `Spi::new()` still.
pub fn new_internal(
peri: impl Peripheral<P = T> + 'd,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
freq: Hertz,
config: Config,
) -> Self {
Self::new_inner(peri, None, None, None, txdma, rxdma, freq, config)
}
fn new_inner(
peri: impl Peripheral<P = T> + 'd,
sck: Option<PeripheralRef<'d, AnyPin>>,

7
embassy-stm32/src/subghz/mod.rs
View File

@ -81,7 +81,7 @@ pub use value_error::ValueError;
use crate::dma::NoDma;
use crate::peripherals::SUBGHZSPI;
use crate::rcc::sealed::RccPeripheral;
use crate::spi::{BitOrder, Config as SpiConfig, MisoPin, MosiPin, SckPin, Spi, MODE_0};
use crate::spi::{BitOrder, Config as SpiConfig, Spi, MODE_0};
use crate::time::Hertz;
use crate::{pac, Peripheral};
@ -212,9 +212,6 @@ impl<'d, Tx, Rx> SubGhz<'d, Tx, Rx> {
/// clock.
pub fn new(
peri: impl Peripheral<P = SUBGHZSPI> + 'd,
sck: impl Peripheral<P = impl SckPin<SUBGHZSPI>> + 'd,
mosi: impl Peripheral<P = impl MosiPin<SUBGHZSPI>> + 'd,
miso: impl Peripheral<P = impl MisoPin<SUBGHZSPI>> + 'd,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
) -> Self {
@ -227,7 +224,7 @@ impl<'d, Tx, Rx> SubGhz<'d, Tx, Rx> {
let mut config = SpiConfig::default();
config.mode = MODE_0;
config.bit_order = BitOrder::MsbFirst;
let spi = Spi::new(peri, sck, mosi, miso, txdma, rxdma, clk, config);
let spi = Spi::new_internal(peri, txdma, rxdma, clk, config);
unsafe { wakeup() };