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Merge #839

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839: Misc LoRaWAN improvements r=lulf a=timokroeger

Trying too get `embassy-lora` running on a [LoRa-E5 Dev Board](https://wiki.seeedstudio.com/LoRa_E5_Dev_Board/).
I can see the join message arriving in the The Things Network console but the device does not receive the accept message yet.
Opening this PR anyway because I think there are some nice things to decouple the lora crate from the nucleo board.

`@lulf` Could you test if this PR breaks your LoRa setup? Marking as draft for the time being.

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
This commit is contained in:
bors[bot]
2022-09-04 07:17:23 +00:00
committed by GitHub
parent 7d5c1fcebf 6cdff72d6d
commit 6264fe39a5
11 changed files with 269 additions and 257 deletions
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116
embassy-stm32/src/rcc/wl.rs
View File

@ -202,54 +202,11 @@ impl Default for Config {
pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw, vos) = match config.mux {
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ.0, 0x01, VoltageScale::Range2)
}
ClockSrc::HSE32 => {
// Enable HSE32
RCC.cr().write(|w| {
w.set_hsebyppwr(true);
w.set_hseon(true);
});
while !RCC.cr().read().hserdy() {}
(HSE32_FREQ.0, 0x02, VoltageScale::Range1)
}
ClockSrc::MSI(range) => {
RCC.cr().write(|w| {
w.set_msirange(range.into());
w.set_msion(true);
});
while !RCC.cr().read().msirdy() {}
(range.freq(), 0x00, range.vos())
}
ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::Range2),
ClockSrc::HSE32 => (HSE32_FREQ.0, 0x02, VoltageScale::Range1),
ClockSrc::MSI(range) => (range.freq(), 0x00, range.vos()),
};
RCC.cfgr().modify(|w| {
w.set_sw(sw.into());
if config.ahb_pre == AHBPrescaler::NotDivided {
w.set_hpre(0);
} else {
w.set_hpre(config.ahb_pre.into());
}
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
RCC.extcfgr().modify(|w| {
if config.shd_ahb_pre == AHBPrescaler::NotDivided {
w.set_shdhpre(0);
} else {
w.set_shdhpre(config.shd_ahb_pre.into());
}
});
let ahb_freq: u32 = match config.ahb_pre {
AHBPrescaler::NotDivided => sys_clk,
pre => {
@ -288,16 +245,6 @@ pub(crate) unsafe fn init(config: Config) {
}
};
let apb3_freq = shd_ahb_freq;
if config.enable_lsi {
let csr = RCC.csr().read();
if !csr.lsion() {
RCC.csr().modify(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
}
}
// Adjust flash latency
let flash_clk_src_freq: u32 = shd_ahb_freq;
let ws = match vos {
@ -319,6 +266,61 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != ws {}
match config.mux {
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
ClockSrc::HSE32 => {
// Enable HSE32
RCC.cr().write(|w| {
w.set_hsebyppwr(true);
w.set_hseon(true);
});
while !RCC.cr().read().hserdy() {}
}
ClockSrc::MSI(range) => {
let cr = RCC.cr().read();
assert!(!cr.msion() || cr.msirdy());
RCC.cr().write(|w| {
w.set_msirgsel(true);
w.set_msirange(range.into());
w.set_msion(true);
});
while !RCC.cr().read().msirdy() {}
}
}
RCC.extcfgr().modify(|w| {
if config.shd_ahb_pre == AHBPrescaler::NotDivided {
w.set_shdhpre(0);
} else {
w.set_shdhpre(config.shd_ahb_pre.into());
}
});
RCC.cfgr().modify(|w| {
w.set_sw(sw.into());
if config.ahb_pre == AHBPrescaler::NotDivided {
w.set_hpre(0);
} else {
w.set_hpre(config.ahb_pre.into());
}
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
});
// TODO: switch voltage range
if config.enable_lsi {
let csr = RCC.csr().read();
if !csr.lsion() {
RCC.csr().modify(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
}
}
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
@ -326,7 +328,7 @@ pub(crate) unsafe fn init(config: Config) {
ahb3: Hertz(shd_ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb3: Hertz(apb3_freq),
apb3: Hertz(shd_ahb_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
});

13
embassy-stm32/src/spi/mod.rs
View File

@ -179,6 +179,19 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
)
}
/// Useful for on chip peripherals like SUBGHZ which are hardwired.
/// The bus can optionally be exposed externally with `Spi::new()` still.
#[allow(dead_code)]
pub(crate) fn new_internal(
peri: impl Peripheral<P = T> + 'd,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
freq: Hertz,
config: Config,
) -> Self {
Self::new_inner(peri, None, None, None, txdma, rxdma, freq, config)
}
fn new_inner(
peri: impl Peripheral<P = T> + 'd,
sck: Option<PeripheralRef<'d, AnyPin>>,

7
embassy-stm32/src/subghz/mod.rs
View File

@ -81,7 +81,7 @@ pub use value_error::ValueError;
use crate::dma::NoDma;
use crate::peripherals::SUBGHZSPI;
use crate::rcc::sealed::RccPeripheral;
use crate::spi::{BitOrder, Config as SpiConfig, MisoPin, MosiPin, SckPin, Spi, MODE_0};
use crate::spi::{BitOrder, Config as SpiConfig, Spi, MODE_0};
use crate::time::Hertz;
use crate::{pac, Peripheral};
@ -212,9 +212,6 @@ impl<'d, Tx, Rx> SubGhz<'d, Tx, Rx> {
/// clock.
pub fn new(
peri: impl Peripheral<P = SUBGHZSPI> + 'd,
sck: impl Peripheral<P = impl SckPin<SUBGHZSPI>> + 'd,
mosi: impl Peripheral<P = impl MosiPin<SUBGHZSPI>> + 'd,
miso: impl Peripheral<P = impl MisoPin<SUBGHZSPI>> + 'd,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
) -> Self {
@ -227,7 +224,7 @@ impl<'d, Tx, Rx> SubGhz<'d, Tx, Rx> {
let mut config = SpiConfig::default();
config.mode = MODE_0;
config.bit_order = BitOrder::MsbFirst;
let spi = Spi::new(peri, sck, mosi, miso, txdma, rxdma, clk, config);
let spi = Spi::new_internal(peri, txdma, rxdma, clk, config);
unsafe { wakeup() };