stm32/rcc: add plli2s to Clocks and cfg directives
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@ -28,6 +28,8 @@ pub struct Config {
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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pub plli2s: Option<Hertz>,
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pub pll48: bool,
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@ -342,7 +344,10 @@ pub(crate) unsafe fn init(config: Config) {
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pllsrcclk,
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config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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config.plli2s.map(|i2s| i2s.0),
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
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None,
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config.pll48,
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);
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@ -473,6 +478,9 @@ pub(crate) unsafe fn init(config: Config) {
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ahb3: Hertz(hclk),
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pll48: plls.pll48clk.map(Hertz),
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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plli2s: plls.plli2sclk.map(Hertz),
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});
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}
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