diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index a2a475e2..e74b2e15 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -451,6 +451,27 @@ fn spin_until_idle(regs: Regs) {
     }
 }
 
+fn finish_dma(regs: Regs) {
+    spin_until_idle(regs);
+
+    unsafe {
+        regs.cr1().modify(|w| {
+            w.set_spe(false);
+        });
+
+        #[cfg(not(spi_v3))]
+        regs.cr2().modify(|reg| {
+            reg.set_txdmaen(false);
+            reg.set_rxdmaen(false);
+        });
+        #[cfg(spi_v3)]
+        regs.cfg1().modify(|reg| {
+            reg.set_txdmaen(false);
+            reg.set_rxdmaen(false);
+        });
+    }
+}
+
 trait Word {
     const WORDSIZE: WordSize;
 }
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 94359261..ef7e0f59 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -32,6 +32,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
         }
 
         f.await;
+
+        finish_dma(T::regs());
+
         Ok(())
     }
 
@@ -78,17 +81,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
-
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
+        finish_dma(T::regs());
 
         Ok(())
     }
@@ -138,17 +131,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
-
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
+        finish_dma(T::regs());
 
         Ok(())
     }
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index d9f5b46f..f2ba3ac6 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -37,16 +37,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         f.await;
 
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
 
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
         Ok(())
     }
 
@@ -93,17 +85,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
-
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
+        finish_dma(T::regs());
 
         Ok(())
     }
@@ -158,17 +140,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
-
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
+        finish_dma(T::regs());
 
         Ok(())
     }
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index a3e39b21..b42eeed8 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -39,14 +39,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
         }
 
         f.await;
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
+
+        finish_dma(T::regs());
 
         Ok(())
     }
@@ -97,17 +91,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
 
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
-                reg.set_rxdmaen(false);
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
         Ok(())
     }
 
@@ -164,17 +149,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
 
         join(tx_f, rx_f).await;
 
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
 
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
-                reg.set_rxdmaen(false);
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
         Ok(())
     }
 }