fix set_handler context
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61a7cf5c3d
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66622de82a
@ -88,9 +88,9 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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let (usart, _) = serial.release();
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let (usart, _) = serial.release();
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// Register ISR
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// Register ISR
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tx_int.set_handler(Self::on_tx_irq);
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tx_int.set_handler(Self::on_tx_irq, core::ptr::null_mut());
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rx_int.set_handler(Self::on_rx_irq);
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rx_int.set_handler(Self::on_rx_irq, core::ptr::null_mut());
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usart_int.set_handler(Self::on_rx_irq);
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usart_int.set_handler(Self::on_rx_irq, core::ptr::null_mut());
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// usart_int.unpend();
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// usart_int.unpend();
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// usart_int.enable();
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// usart_int.enable();
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@ -106,7 +106,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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}
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}
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}
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}
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unsafe fn on_tx_irq() {
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unsafe fn on_tx_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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let s = &(*INSTANCE);
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s.tx_int.disable();
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s.tx_int.disable();
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@ -114,7 +114,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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STATE.tx_int.signal(());
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STATE.tx_int.signal(());
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}
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}
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unsafe fn on_rx_irq() {
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unsafe fn on_rx_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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let s = &(*INSTANCE);
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atomic::compiler_fence(Ordering::Acquire);
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atomic::compiler_fence(Ordering::Acquire);
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@ -125,7 +125,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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STATE.rx_int.signal(());
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STATE.rx_int.signal(());
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}
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}
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unsafe fn on_usart_irq() {
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unsafe fn on_usart_irq(_ctx: *mut ()) {
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let s = &(*INSTANCE);
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let s = &(*INSTANCE);
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atomic::compiler_fence(Ordering::Acquire);
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atomic::compiler_fence(Ordering::Acquire);
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