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fix set_handler context

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This commit is contained in:
xoviat
2021-01-06 10:49:08 -06:00
parent 61a7cf5c3d
commit 66622de82a
1 changed files with 6 additions and 6 deletions
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12
embassy-stm32f4/src/serial.rs
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@@ -88,9 +88,9 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
let (usart, _) = serial.release();
// Register ISR
tx_int.set_handler(Self::on_tx_irq);
rx_int.set_handler(Self::on_rx_irq);
usart_int.set_handler(Self::on_rx_irq);
tx_int.set_handler(Self::on_tx_irq, core::ptr::null_mut());
rx_int.set_handler(Self::on_rx_irq, core::ptr::null_mut());
usart_int.set_handler(Self::on_rx_irq, core::ptr::null_mut());
// usart_int.unpend();
// usart_int.enable();
@@ -106,7 +106,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
}
}
unsafe fn on_tx_irq() {
unsafe fn on_tx_irq(_ctx: *mut ()) {
let s = &(*INSTANCE);
s.tx_int.disable();
@@ -114,7 +114,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
STATE.tx_int.signal(());
}
unsafe fn on_rx_irq() {
unsafe fn on_rx_irq(_ctx: *mut ()) {
let s = &(*INSTANCE);
atomic::compiler_fence(Ordering::Acquire);
@@ -125,7 +125,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
STATE.rx_int.signal(());
}
unsafe fn on_usart_irq() {
unsafe fn on_usart_irq(_ctx: *mut ()) {
let s = &(*INSTANCE);
atomic::compiler_fence(Ordering::Acquire);