Fix clippy
This commit is contained in:
		@@ -39,6 +39,12 @@ pub struct State<'a> {
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    shared: ControlShared,
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					    shared: ControlShared,
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}
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					}
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					impl<'a> Default for State<'a> {
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					    fn default() -> Self {
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					        Self::new()
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					    }
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					}
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impl<'a> State<'a> {
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					impl<'a> State<'a> {
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    /// Create a new `State`.
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					    /// Create a new `State`.
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    pub fn new() -> Self {
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					    pub fn new() -> Self {
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@@ -242,7 +248,7 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> {
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            &[
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					            &[
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                CDC_TYPE_UNION, // bDescriptorSubtype
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					                CDC_TYPE_UNION, // bDescriptorSubtype
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                comm_if.into(), // bControlInterface
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					                comm_if.into(), // bControlInterface
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                data_if.into(), // bSubordinateInterface
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					                data_if,        // bSubordinateInterface
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            ],
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					            ],
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        );
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					        );
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@@ -121,6 +121,12 @@ pub struct State<'a> {
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    shared: ControlShared,
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					    shared: ControlShared,
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}
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					}
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					impl<'a> Default for State<'a> {
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					    fn default() -> Self {
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					        Self::new()
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					    }
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					}
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impl<'a> State<'a> {
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					impl<'a> State<'a> {
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    /// Create a new `State`.
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					    /// Create a new `State`.
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    pub fn new() -> Self {
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					    pub fn new() -> Self {
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@@ -132,16 +138,11 @@ impl<'a> State<'a> {
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}
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					}
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/// Shared data between Control and CdcAcmClass
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					/// Shared data between Control and CdcAcmClass
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					#[derive(Default)]
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struct ControlShared {
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					struct ControlShared {
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    mac_addr: [u8; 6],
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					    mac_addr: [u8; 6],
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}
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					}
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impl Default for ControlShared {
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    fn default() -> Self {
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        ControlShared { mac_addr: [0; 6] }
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    }
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}
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struct Control<'a> {
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					struct Control<'a> {
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    mac_addr_string: StringIndex,
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					    mac_addr_string: StringIndex,
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    shared: &'a ControlShared,
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					    shared: &'a ControlShared,
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@@ -416,7 +417,7 @@ impl<'d, D: Driver<'d>> Sender<'d, D> {
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            self.write_ep.write(&buf[..self.max_packet_size]).await?;
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					            self.write_ep.write(&buf[..self.max_packet_size]).await?;
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            for chunk in d2.chunks(self.max_packet_size) {
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					            for chunk in d2.chunks(self.max_packet_size) {
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                self.write_ep.write(&chunk).await?;
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					                self.write_ep.write(chunk).await?;
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            }
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					            }
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            // Send ZLP if needed.
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					            // Send ZLP if needed.
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@@ -79,6 +79,12 @@ pub struct State<'d> {
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    out_report_offset: AtomicUsize,
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					    out_report_offset: AtomicUsize,
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}
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					}
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					impl<'d> Default for State<'d> {
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					    fn default() -> Self {
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					        Self::new()
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					    }
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					}
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impl<'d> State<'d> {
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					impl<'d> State<'d> {
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    /// Create a new `State`.
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					    /// Create a new `State`.
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    pub fn new() -> Self {
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					    pub fn new() -> Self {
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@@ -171,7 +177,7 @@ impl<'d, D: Driver<'d>, const READ_N: usize, const WRITE_N: usize> HidReaderWrit
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    }
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					    }
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    /// Waits for both IN and OUT endpoints to be enabled.
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					    /// Waits for both IN and OUT endpoints to be enabled.
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    pub async fn ready(&mut self) -> () {
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					    pub async fn ready(&mut self) {
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        self.reader.ready().await;
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					        self.reader.ready().await;
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        self.writer.ready().await;
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					        self.writer.ready().await;
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    }
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					    }
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@@ -251,7 +257,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> {
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    }
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					    }
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    /// Waits for the interrupt in endpoint to be enabled.
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					    /// Waits for the interrupt in endpoint to be enabled.
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    pub async fn ready(&mut self) -> () {
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					    pub async fn ready(&mut self) {
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        self.ep_in.wait_enabled().await
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					        self.ep_in.wait_enabled().await
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    }
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					    }
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@@ -286,7 +292,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> {
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impl<'d, D: Driver<'d>, const N: usize> HidReader<'d, D, N> {
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					impl<'d, D: Driver<'d>, const N: usize> HidReader<'d, D, N> {
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    /// Waits for the interrupt out endpoint to be enabled.
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					    /// Waits for the interrupt out endpoint to be enabled.
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    pub async fn ready(&mut self) -> () {
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					    pub async fn ready(&mut self) {
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        self.ep_out.wait_enabled().await
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					        self.ep_out.wait_enabled().await
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    }
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					    }
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@@ -466,7 +472,7 @@ impl<'d> Handler for Control<'d> {
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            HID_REQ_SET_IDLE => {
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					            HID_REQ_SET_IDLE => {
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                if let Some(handler) = self.request_handler {
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					                if let Some(handler) = self.request_handler {
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                    let id = req.value as u8;
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					                    let id = req.value as u8;
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                    let id = (id != 0).then(|| ReportId::In(id));
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					                    let id = (id != 0).then_some(ReportId::In(id));
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                    let dur = u32::from(req.value >> 8);
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					                    let dur = u32::from(req.value >> 8);
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                    let dur = if dur == 0 { u32::MAX } else { 4 * dur };
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					                    let dur = if dur == 0 { u32::MAX } else { 4 * dur };
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                    handler.set_idle_ms(id, dur);
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					                    handler.set_idle_ms(id, dur);
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@@ -522,7 +528,7 @@ impl<'d> Handler for Control<'d> {
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                    HID_REQ_GET_IDLE => {
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					                    HID_REQ_GET_IDLE => {
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                        if let Some(handler) = self.request_handler {
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					                        if let Some(handler) = self.request_handler {
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                            let id = req.value as u8;
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					                            let id = req.value as u8;
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                            let id = (id != 0).then(|| ReportId::In(id));
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					                            let id = (id != 0).then_some(ReportId::In(id));
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                            if let Some(dur) = handler.get_idle_ms(id) {
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					                            if let Some(dur) = handler.get_idle_ms(id) {
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                                let dur = u8::try_from(dur / 4).unwrap_or(0);
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					                                let dur = u8::try_from(dur / 4).unwrap_or(0);
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                                buf[0] = dur;
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					                                buf[0] = dur;
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@@ -281,7 +281,7 @@ pub struct BosWriter<'a> {
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impl<'a> BosWriter<'a> {
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					impl<'a> BosWriter<'a> {
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    pub(crate) fn new(writer: DescriptorWriter<'a>) -> Self {
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					    pub(crate) fn new(writer: DescriptorWriter<'a>) -> Self {
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        Self {
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					        Self {
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            writer: writer,
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					            writer,
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            num_caps_mark: None,
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					            num_caps_mark: None,
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        }
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					        }
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    }
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					    }
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@@ -294,7 +294,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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    /// After dropping the future, [`UsbDevice::disable()`] should be called
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					    /// After dropping the future, [`UsbDevice::disable()`] should be called
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    /// before calling any other `UsbDevice` methods to fully reset the
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					    /// before calling any other `UsbDevice` methods to fully reset the
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    /// peripheral.
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					    /// peripheral.
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    pub async fn run_until_suspend(&mut self) -> () {
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					    pub async fn run_until_suspend(&mut self) {
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        while !self.inner.suspended {
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					        while !self.inner.suspended {
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            let control_fut = self.control.setup();
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					            let control_fut = self.control.setup();
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            let bus_fut = self.inner.bus.poll();
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					            let bus_fut = self.inner.bus.poll();
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@@ -372,18 +372,15 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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        // a full-length packet is a short packet, thinking we're done sending data.
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					        // a full-length packet is a short packet, thinking we're done sending data.
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        // See https://github.com/hathach/tinyusb/issues/184
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					        // See https://github.com/hathach/tinyusb/issues/184
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        const DEVICE_DESCRIPTOR_LEN: usize = 18;
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					        const DEVICE_DESCRIPTOR_LEN: usize = 18;
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        if self.inner.address == 0
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					        if self.inner.address == 0 && max_packet_size < DEVICE_DESCRIPTOR_LEN && max_packet_size < resp_length {
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            && max_packet_size < DEVICE_DESCRIPTOR_LEN
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            && (max_packet_size as usize) < resp_length
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        {
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            trace!("received control req while not addressed: capping response to 1 packet.");
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					            trace!("received control req while not addressed: capping response to 1 packet.");
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            resp_length = max_packet_size;
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					            resp_length = max_packet_size;
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        }
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					        }
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        match self.inner.handle_control_in(req, &mut self.control_buf) {
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					        match self.inner.handle_control_in(req, self.control_buf) {
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            InResponse::Accepted(data) => {
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					            InResponse::Accepted(data) => {
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                let len = data.len().min(resp_length);
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					                let len = data.len().min(resp_length);
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                let need_zlp = len != resp_length && (len % usize::from(max_packet_size)) == 0;
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					                let need_zlp = len != resp_length && (len % max_packet_size) == 0;
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                let chunks = data[0..len]
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					                let chunks = data[0..len]
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                    .chunks(max_packet_size)
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					                    .chunks(max_packet_size)
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@@ -706,7 +703,7 @@ impl<'d, D: Driver<'d>> Inner<'d, D> {
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    }
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					    }
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    fn handle_control_in_delegated<'a>(&'a mut self, req: Request, buf: &'a mut [u8]) -> InResponse<'a> {
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					    fn handle_control_in_delegated<'a>(&'a mut self, req: Request, buf: &'a mut [u8]) -> InResponse<'a> {
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        unsafe fn extend_lifetime<'x, 'y>(r: InResponse<'x>) -> InResponse<'y> {
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					        unsafe fn extend_lifetime<'y>(r: InResponse<'_>) -> InResponse<'y> {
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            core::mem::transmute(r)
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					            core::mem::transmute(r)
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        }
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					        }
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