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Fix clippy

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This commit is contained in:
Rafael Bachmann
2023-10-15 22:25:35 +02:00
parent eeedaf2e76
commit 66e62e9994
5 changed files with 32 additions and 22 deletions
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8
embassy-usb/src/class/cdc_acm.rs
View File

@@ -39,6 +39,12 @@ pub struct State<'a> {
shared: ControlShared,
}
impl<'a> Default for State<'a> {
fn default() -> Self {
Self::new()
}
}
impl<'a> State<'a> {
/// Create a new `State`.
pub fn new() -> Self {
@@ -242,7 +248,7 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> {
&[
CDC_TYPE_UNION, // bDescriptorSubtype
comm_if.into(), // bControlInterface
data_if.into(), // bSubordinateInterface
data_if, // bSubordinateInterface
],
);

15
embassy-usb/src/class/cdc_ncm/mod.rs
View File

@@ -121,6 +121,12 @@ pub struct State<'a> {
shared: ControlShared,
}
impl<'a> Default for State<'a> {
fn default() -> Self {
Self::new()
}
}
impl<'a> State<'a> {
/// Create a new `State`.
pub fn new() -> Self {
@@ -132,16 +138,11 @@ impl<'a> State<'a> {
}
/// Shared data between Control and CdcAcmClass
#[derive(Default)]
struct ControlShared {
mac_addr: [u8; 6],
}
impl Default for ControlShared {
fn default() -> Self {
ControlShared { mac_addr: [0; 6] }
}
}
struct Control<'a> {
mac_addr_string: StringIndex,
shared: &'a ControlShared,
@@ -416,7 +417,7 @@ impl<'d, D: Driver<'d>> Sender<'d, D> {
self.write_ep.write(&buf[..self.max_packet_size]).await?;
for chunk in d2.chunks(self.max_packet_size) {
self.write_ep.write(&chunk).await?;
self.write_ep.write(chunk).await?;
}
// Send ZLP if needed.

16
embassy-usb/src/class/hid.rs
View File

@@ -79,6 +79,12 @@ pub struct State<'d> {
out_report_offset: AtomicUsize,
}
impl<'d> Default for State<'d> {
fn default() -> Self {
Self::new()
}
}
impl<'d> State<'d> {
/// Create a new `State`.
pub fn new() -> Self {
@@ -171,7 +177,7 @@ impl<'d, D: Driver<'d>, const READ_N: usize, const WRITE_N: usize> HidReaderWrit
}
/// Waits for both IN and OUT endpoints to be enabled.
pub async fn ready(&mut self) -> () {
pub async fn ready(&mut self) {
self.reader.ready().await;
self.writer.ready().await;
}
@@ -251,7 +257,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> {
}
/// Waits for the interrupt in endpoint to be enabled.
pub async fn ready(&mut self) -> () {
pub async fn ready(&mut self) {
self.ep_in.wait_enabled().await
}
@@ -286,7 +292,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> {
impl<'d, D: Driver<'d>, const N: usize> HidReader<'d, D, N> {
/// Waits for the interrupt out endpoint to be enabled.
pub async fn ready(&mut self) -> () {
pub async fn ready(&mut self) {
self.ep_out.wait_enabled().await
}
@@ -466,7 +472,7 @@ impl<'d> Handler for Control<'d> {
HID_REQ_SET_IDLE => {
if let Some(handler) = self.request_handler {
let id = req.value as u8;
let id = (id != 0).then(|| ReportId::In(id));
let id = (id != 0).then_some(ReportId::In(id));
let dur = u32::from(req.value >> 8);
let dur = if dur == 0 { u32::MAX } else { 4 * dur };
handler.set_idle_ms(id, dur);
@@ -522,7 +528,7 @@ impl<'d> Handler for Control<'d> {
HID_REQ_GET_IDLE => {
if let Some(handler) = self.request_handler {
let id = req.value as u8;
let id = (id != 0).then(|| ReportId::In(id));
let id = (id != 0).then_some(ReportId::In(id));
if let Some(dur) = handler.get_idle_ms(id) {
let dur = u8::try_from(dur / 4).unwrap_or(0);
buf[0] = dur;

2
embassy-usb/src/descriptor.rs
View File

@@ -281,7 +281,7 @@ pub struct BosWriter<'a> {
impl<'a> BosWriter<'a> {
pub(crate) fn new(writer: DescriptorWriter<'a>) -> Self {
Self {
writer: writer,
writer,
num_caps_mark: None,
}
}

13
embassy-usb/src/lib.rs
View File

@@ -294,7 +294,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
/// After dropping the future, [`UsbDevice::disable()`] should be called
/// before calling any other `UsbDevice` methods to fully reset the
/// peripheral.
pub async fn run_until_suspend(&mut self) -> () {
pub async fn run_until_suspend(&mut self) {
while !self.inner.suspended {
let control_fut = self.control.setup();
let bus_fut = self.inner.bus.poll();
@@ -372,18 +372,15 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
// a full-length packet is a short packet, thinking we're done sending data.
// See https://github.com/hathach/tinyusb/issues/184
const DEVICE_DESCRIPTOR_LEN: usize = 18;
if self.inner.address == 0
&& max_packet_size < DEVICE_DESCRIPTOR_LEN
&& (max_packet_size as usize) < resp_length
{
if self.inner.address == 0 && max_packet_size < DEVICE_DESCRIPTOR_LEN && max_packet_size < resp_length {
trace!("received control req while not addressed: capping response to 1 packet.");
resp_length = max_packet_size;
}
match self.inner.handle_control_in(req, &mut self.control_buf) {
match self.inner.handle_control_in(req, self.control_buf) {
InResponse::Accepted(data) => {
let len = data.len().min(resp_length);
let need_zlp = len != resp_length && (len % usize::from(max_packet_size)) == 0;
let need_zlp = len != resp_length && (len % max_packet_size) == 0;
let chunks = data[0..len]
.chunks(max_packet_size)
@@ -706,7 +703,7 @@ impl<'d, D: Driver<'d>> Inner<'d, D> {
}
fn handle_control_in_delegated<'a>(&'a mut self, req: Request, buf: &'a mut [u8]) -> InResponse<'a> {
unsafe fn extend_lifetime<'x, 'y>(r: InResponse<'x>) -> InResponse<'y> {
unsafe fn extend_lifetime<'y>(r: InResponse<'_>) -> InResponse<'y> {
core::mem::transmute(r)
}