stm32/rcc: refactor f7.
This commit is contained in:
Dario Nieuwenhuis
parent
361fde35cf
commit
67010d123c
@ -1,5 +1,7 @@
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllp, Pllq, Pllsrc, Ppre, Sw};
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
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Ppre as APBPrescaler, Sw as Sysclk,
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};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -7,299 +9,304 @@ use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// Clocks configuration
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub hclk: Option<Hertz>,
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL P division factor. If None, PLL P output is disabled.
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pub divp: Option<Pllp>,
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/// PLL Q division factor. If None, PLL Q output is disabled.
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pub divq: Option<Pllq>,
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/// PLL R division factor. If None, PLL R output is disabled.
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pub divr: Option<Pllr>,
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}
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/// Configuration of the core clocks
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#[non_exhaustive]
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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pub sys: Sysclk,
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pub pll_src: PllSource,
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pub pll: Option<Pll>,
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pub plli2s: Option<Pll>,
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pub pllsai: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub pll48: bool,
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pub ls: super::LsConfig,
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}
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fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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pll_src: PllSource::HSI,
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pll: None,
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plli2s: None,
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pllsai: None,
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return PllResults {
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use_pll: false,
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pllsysclk: None,
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pll48clk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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// the range from 1 to 2 MHz
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let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
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let pllm_max = pllsrcclk / 1_000_000;
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
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let vco_in = pllsrcclk / pllm;
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let plln = target_freq / vco_in;
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target_freq - vco_in * plln
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}));
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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let plln = if pll48clk {
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// try the different valid pllq according to the valid
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// main scaller values, and take the best
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let pllq = unwrap!((4..=9).min_by_key(|pllq| {
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let plln = 48_000_000 * pllq / vco_in;
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let pll48_diff = 48_000_000 - vco_in * plln / pllq;
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let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
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(pll48_diff, sysclk_diff)
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}));
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48_000_000 * pllq / vco_in
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} else {
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sysclk * sysclk_div / vco_in
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};
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let pllp = (sysclk_div / 2) - 1;
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let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
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let real_pll48clk = vco_in * plln / pllq;
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RCC.pllcfgr().modify(|w| {
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w.set_pllm(Pllm::from_bits(pllm as u8));
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w.set_plln(Plln::from_bits(plln as u16));
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w.set_pllp(Pllp::from_bits(pllp as u8));
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w.set_pllq(Pllq::from_bits(pllq as u8));
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w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
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});
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let real_pllsysclk = vco_in * plln / sysclk_div;
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PllResults {
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use_pll: true,
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pllsysclk: Some(real_pllsysclk),
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pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
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ls: Default::default(),
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}
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}
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}
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fn flash_setup(sysclk: u32) {
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pub(crate) unsafe fn init(config: Config) {
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// always enable overdrive for now. Make it configurable in the future.
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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Some(HSI_FREQ)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure PLLs.
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let pll_input = PllInput {
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hse,
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hsi,
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source: config.pll_src,
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};
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
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let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
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// Configure sysclk
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_P => unwrap!(pll.p),
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_ => unreachable!(),
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};
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let hclk = sys / config.ahb_pre;
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let (pclk1, pclk1_tim) = calc_pclk(hclk, config.apb1_pre);
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let (pclk2, pclk2_tim) = calc_pclk(hclk, config.apb2_pre);
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assert!(max::SYSCLK.contains(&sys));
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assert!(max::HCLK.contains(&hclk));
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assert!(max::PCLK1.contains(&pclk1));
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assert!(max::PCLK2.contains(&pclk2));
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let rtc = config.ls.init();
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flash_setup(hclk);
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RCC.cfgr().modify(|w| {
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w.set_sw(config.sys);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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while RCC.cfgr().read().sws() != config.sys {}
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set_freqs(Clocks {
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sys,
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hclk1: hclk,
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hclk2: hclk,
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hclk3: hclk,
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pclk1,
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pclk2,
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pclk1_tim,
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pclk2_tim,
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rtc,
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pll1_q: pll.q,
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});
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}
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struct PllInput {
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source: PllSource,
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hsi: Option<Hertz>,
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hse: Option<Hertz>,
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}
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#[derive(Default)]
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#[allow(unused)]
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struct PllOutput {
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p: Option<Hertz>,
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q: Option<Hertz>,
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r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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Plli2s,
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Pllsai,
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}
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fn pll_enable(instance: PllInstance, enabled: bool) {
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(enabled));
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while RCC.cr().read().pllrdy() != enabled {}
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}
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PllInstance::Plli2s => {
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RCC.cr().modify(|w| w.set_plli2son(enabled));
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while RCC.cr().read().plli2srdy() != enabled {}
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}
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PllInstance::Pllsai => {
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RCC.cr().modify(|w| w.set_pllsaion(enabled));
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while RCC.cr().read().pllsairdy() != enabled {}
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}
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}
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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// Disable PLL
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pll_enable(instance, false);
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let Some(pll) = config else { return PllOutput::default() };
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let pll_src = match input.source {
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PllSource::HSE => input.hse,
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PllSource::HSI => input.hsi,
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};
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let pll_src = pll_src.unwrap();
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let in_freq = pll_src / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let vco_freq = in_freq * pll.mul;
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assert!(max::PLL_VCO.contains(&vco_freq));
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let p = pll.divp.map(|div| vco_freq / div);
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let q = pll.divq.map(|div| vco_freq / div);
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let r = pll.divr.map(|div| vco_freq / div);
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macro_rules! write_fields {
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($w:ident) => {
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$w.set_plln(pll.mul);
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if let Some(divp) = pll.divp {
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$w.set_pllp(divp);
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}
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if let Some(divq) = pll.divq {
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$w.set_pllq(divq);
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}
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if let Some(divr) = pll.divr {
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$w.set_pllr(divr);
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}
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};
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}
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match instance {
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PllInstance::Pll => RCC.pllcfgr().write(|w| {
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w.set_pllm(pll.prediv);
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w.set_pllsrc(input.source);
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write_fields!(w);
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}),
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PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
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write_fields!(w);
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}),
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PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
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write_fields!(w);
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}),
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}
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// Enable PLL
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pll_enable(instance, true);
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PllOutput { p, q, r }
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}
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fn flash_setup(clk: Hertz) {
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use crate::pac::flash::vals::Latency;
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// Be conservative with voltage ranges
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const FLASH_LATENCY_STEP: u32 = 30_000_000;
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critical_section::with(|_| {
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FLASH
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.acr()
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.modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
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let latency = (clk.0 - 1) / FLASH_LATENCY_STEP;
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debug!("flash: latency={}", latency);
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let latency = Latency::from_bits(latency as u8);
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FLASH.acr().write(|w| {
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w.set_latency(latency);
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});
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while FLASH.acr().read().latency() != latency {}
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}
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pub(crate) unsafe fn init(config: Config) {
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if let Some(hse) = config.hse {
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if config.bypass_hse {
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assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
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} else {
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assert!((max::HSE_OSC_MIN..=max::HSE_OSC_MAX).contains(&hse.0));
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}
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}
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let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
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let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let sysclk_on_pll = sysclk != pllsrcclk;
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assert!((max::SYSCLK_MIN..=max::SYSCLK_MAX).contains(&sysclk));
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let plls = setup_pll(
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pllsrcclk,
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config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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config.pll48,
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);
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if config.pll48 {
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let freq = unwrap!(plls.pll48clk);
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assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
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}
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let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
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// AHB prescaler
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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assert!(hclk <= max::HCLK_MAX);
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let pclk1 = config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!((max::PCLK1_MIN..=max::PCLK1_MAX).contains(&pclk1));
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let pclk2 = config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
|
||||
3..=5 => (0b101, 4),
|
||||
6..=11 => (0b110, 8),
|
||||
_ => (0b111, 16),
|
||||
};
|
||||
let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
|
||||
|
||||
// Calculate real APB2 clock
|
||||
let pclk2 = hclk / ppre2;
|
||||
assert!((max::PCLK2_MIN..=max::PCLK2_MAX).contains(&pclk2));
|
||||
|
||||
flash_setup(sysclk);
|
||||
|
||||
if config.hse.is_some() {
|
||||
RCC.cr().modify(|w| {
|
||||
w.set_hsebyp(config.bypass_hse);
|
||||
w.set_hseon(true);
|
||||
});
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
}
|
||||
|
||||
if plls.use_pll {
|
||||
RCC.cr().modify(|w| w.set_pllon(false));
|
||||
|
||||
// setup VOSScale
|
||||
let vos_scale = if sysclk <= 144_000_000 {
|
||||
3
|
||||
} else if sysclk <= 168_000_000 {
|
||||
2
|
||||
} else {
|
||||
1
|
||||
};
|
||||
PWR.cr1().modify(|w| {
|
||||
w.set_vos(match vos_scale {
|
||||
3 => Vos::SCALE3,
|
||||
2 => Vos::SCALE2,
|
||||
1 => Vos::SCALE1,
|
||||
_ => panic!("Invalid VOS Scale."),
|
||||
})
|
||||
});
|
||||
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
|
||||
if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
|
||||
PWR.cr1().modify(|w| w.set_oden(true));
|
||||
while !PWR.csr1().read().odrdy() {}
|
||||
|
||||
PWR.cr1().modify(|w| w.set_odswen(true));
|
||||
while !PWR.csr1().read().odswrdy() {}
|
||||
}
|
||||
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
}
|
||||
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_ppre2(Ppre::from_bits(ppre2_bits));
|
||||
w.set_ppre1(Ppre::from_bits(ppre1_bits));
|
||||
w.set_hpre(hpre_bits);
|
||||
});
|
||||
|
||||
// Wait for the new prescalers to kick in
|
||||
// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
|
||||
cortex_m::asm::delay(16);
|
||||
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_sw(if sysclk_on_pll {
|
||||
Sw::PLL1_P
|
||||
} else if config.hse.is_some() {
|
||||
Sw::HSE
|
||||
} else {
|
||||
Sw::HSI
|
||||
})
|
||||
});
|
||||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
set_freqs(Clocks {
|
||||
sys: Hertz(sysclk),
|
||||
pclk1: Hertz(pclk1),
|
||||
pclk2: Hertz(pclk2),
|
||||
|
||||
pclk1_tim: Hertz(pclk1 * timer_mul1),
|
||||
pclk2_tim: Hertz(pclk2 * timer_mul2),
|
||||
|
||||
hclk1: Hertz(hclk),
|
||||
hclk2: Hertz(hclk),
|
||||
hclk3: Hertz(hclk),
|
||||
|
||||
pll1_q: plls.pll48clk.map(Hertz),
|
||||
|
||||
rtc,
|
||||
});
|
||||
}
|
||||
|
||||
struct PllResults {
|
||||
use_pll: bool,
|
||||
pllsysclk: Option<u32>,
|
||||
pll48clk: Option<u32>,
|
||||
fn calc_pclk<D>(hclk: Hertz, ppre: D) -> (Hertz, Hertz)
|
||||
where
|
||||
Hertz: core::ops::Div<D, Output = Hertz>,
|
||||
{
|
||||
let pclk = hclk / ppre;
|
||||
let pclk_tim = if hclk == pclk { pclk } else { pclk * 2u32 };
|
||||
(pclk, pclk_tim)
|
||||
}
|
||||
|
||||
mod max {
|
||||
pub(crate) const HSE_OSC_MIN: u32 = 4_000_000;
|
||||
pub(crate) const HSE_OSC_MAX: u32 = 26_000_000;
|
||||
pub(crate) const HSE_BYPASS_MIN: u32 = 1_000_000;
|
||||
pub(crate) const HSE_BYPASS_MAX: u32 = 50_000_000;
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
pub(crate) const HCLK_MAX: u32 = 216_000_000;
|
||||
pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 180_000_000;
|
||||
use crate::time::Hertz;
|
||||
|
||||
pub(crate) const SYSCLK_MIN: u32 = 12_500_000;
|
||||
pub(crate) const SYSCLK_MAX: u32 = 216_000_000;
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
|
||||
|
||||
pub(crate) const PCLK1_MIN: u32 = SYSCLK_MIN;
|
||||
pub(crate) const PCLK1_MAX: u32 = SYSCLK_MAX / 4;
|
||||
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 4);
|
||||
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 2);
|
||||
|
||||
pub(crate) const PCLK2_MIN: u32 = SYSCLK_MIN;
|
||||
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
|
||||
|
||||
// USB specification allows +-0.25%
|
||||
pub(crate) const PLL_48_CLK: u32 = 48_000_000;
|
||||
pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
|
||||
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
|
||||
}
|
||||
|
||||
@ -10,7 +10,7 @@ use embassy_stm32::eth::generic_smi::GenericSMI;
|
||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||
use embassy_stm32::peripherals::ETH;
|
||||
use embassy_stm32::rng::Rng;
|
||||
use embassy_stm32::time::mhz;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
|
||||
use embassy_time::Timer;
|
||||
use embedded_io_async::Write;
|
||||
@ -33,7 +33,25 @@ async fn net_task(stack: &'static Stack<Device>) -> ! {
|
||||
#[embassy_executor::main]
|
||||
async fn main(spawner: Spawner) -> ! {
|
||||
let mut config = Config::default();
|
||||
config.rcc.sys_ck = Some(mhz(200));
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::Bypass,
|
||||
});
|
||||
config.rcc.pll_src = PllSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
prediv: PllPreDiv::DIV4,
|
||||
mul: PllMul::MUL216,
|
||||
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
|
||||
divq: None,
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
}
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
@ -4,15 +4,13 @@
|
||||
|
||||
use defmt::info;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::Config;
|
||||
use embassy_time::Timer;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) -> ! {
|
||||
let mut config = Config::default();
|
||||
config.rcc.sys_ck = Some(Hertz(84_000_000));
|
||||
let config = Config::default();
|
||||
let _p = embassy_stm32::init(config);
|
||||
|
||||
loop {
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::sdmmc::Sdmmc;
|
||||
use embassy_stm32::time::mhz;
|
||||
use embassy_stm32::time::{mhz, Hertz};
|
||||
use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
@ -16,8 +16,25 @@ bind_interrupts!(struct Irqs {
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.rcc.sys_ck = Some(mhz(200));
|
||||
config.rcc.pll48 = true;
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::Bypass,
|
||||
});
|
||||
config.rcc.pll_src = PllSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
prediv: PllPreDiv::DIV4,
|
||||
mul: PllMul::MUL216,
|
||||
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
|
||||
divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
}
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
use defmt::{panic, *};
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::time::mhz;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::usb_otg::{Driver, Instance};
|
||||
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
|
||||
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
|
||||
@ -22,10 +22,25 @@ async fn main(_spawner: Spawner) {
|
||||
info!("Hello World!");
|
||||
|
||||
let mut config = Config::default();
|
||||
config.rcc.hse = Some(mhz(8));
|
||||
config.rcc.pll48 = true;
|
||||
config.rcc.sys_ck = Some(mhz(200));
|
||||
|
||||
{
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::Bypass,
|
||||
});
|
||||
config.rcc.pll_src = PllSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
prediv: PllPreDiv::DIV4,
|
||||
mul: PllMul::MUL216,
|
||||
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
|
||||
divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
}
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
// Create the driver, from the HAL.
|
||||
|
||||
@ -233,7 +233,23 @@ pub fn config() -> Config {
|
||||
|
||||
#[cfg(feature = "stm32f767zi")]
|
||||
{
|
||||
config.rcc.sys_ck = Some(Hertz(200_000_000));
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::Bypass,
|
||||
});
|
||||
config.rcc.pll_src = PllSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
prediv: PllPreDiv::DIV4,
|
||||
mul: PllMul::MUL216,
|
||||
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
|
||||
divq: None,
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||
config.rcc.sys = Sysclk::PLL1_P;
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32h563zi")]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user