diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 1342b2ea..861753bd 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -58,7 +58,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9330e31117668350a62572fdcd2598ec17d08042" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9330e31117668350a62572fdcd2598ec17d08042", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462", default-features = false, features = ["metadata"]}
 
 
 [features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index d118b851..f8908756 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -466,15 +466,9 @@ fn main() {
 
             let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
             let pname = format_ident!("{}", p.name);
-            let clk = format_ident!(
-                "{}",
-                rcc.clock
-                    .to_ascii_lowercase()
-                    .replace("ahb", "hclk")
-                    .replace("apb", "pclk")
-            );
-            let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
-            let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
+            let clk = format_ident!("{}", rcc.clock);
+            let en_reg = format_ident!("{}", en.register);
+            let set_en_field = format_ident!("set_{}", en.field);
 
             let (before_enable, before_disable) = if refcounted_peripherals.contains(ptype) {
                 let refcount_static =
@@ -500,11 +494,11 @@ fn main() {
                 (TokenStream::new(), TokenStream::new())
             };
 
+            let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g4", "l4"])
+                .contains(rcc_registers.version);
             let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
-                let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
-
                 // restrict mux implementation to supported versions
-                if !checked_rccs.contains(rcc_registers.version) {
+                if !mux_supported {
                     return None;
                 }
 
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index e357f067..68f029ca 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -134,6 +134,8 @@ pub(crate) unsafe fn init(config: Config) {
     };
 
     set_freqs(Clocks {
+        hsi: None,
+        lse: None,
         sys: sys_clk,
         hclk1: ahb_freq,
         pclk1: apb_freq,
diff --git a/embassy-stm32/src/rcc/l0l1.rs b/embassy-stm32/src/rcc/l0l1.rs
index 308b75ae..333e9eea 100644
--- a/embassy-stm32/src/rcc/l0l1.rs
+++ b/embassy-stm32/src/rcc/l0l1.rs
@@ -31,7 +31,7 @@ pub enum PLLSource {
 impl From<PLLSource> for Pllsrc {
     fn from(val: PLLSource) -> Pllsrc {
         match val {
-            PLLSource::HSI16 => Pllsrc::HSI16,
+            PLLSource::HSI16 => Pllsrc::HSI,
             PLLSource::HSE(_) => Pllsrc::HSE,
         }
     }
@@ -88,7 +88,7 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().write(|w| w.set_hsi16on(true));
             while !RCC.cr().read().hsi16rdy() {}
 
-            (HSI_FREQ, Sw::HSI16)
+            (HSI_FREQ, Sw::HSI)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs
index 90c8923c..d99bc45c 100644
--- a/embassy-stm32/src/rcc/l4l5.rs
+++ b/embassy-stm32/src/rcc/l4l5.rs
@@ -187,7 +187,10 @@ pub(crate) unsafe fn init(config: Config) {
 
     let sys_clk = match config.mux {
         ClockSrc::HSE => hse.unwrap(),
+        #[cfg(rcc_l5)]
         ClockSrc::HSI16 => hsi16.unwrap(),
+        #[cfg(not(rcc_l5))]
+        ClockSrc::HSI => hsi16.unwrap(),
         ClockSrc::MSI => msi.unwrap(),
         ClockSrc::PLL => pll._r.unwrap(),
     };
@@ -200,7 +203,10 @@ pub(crate) unsafe fn init(config: Config) {
         Clk48Src::HSI48 => hsi48,
         Clk48Src::MSI => msi,
         Clk48Src::PLLSAI1_Q => pllsai1._q,
+        #[cfg(rcc_l5)]
         Clk48Src::PLL_Q => pll._q,
+        #[cfg(not(rcc_l5))]
+        Clk48Src::PLL1_Q => pll._q,
     };
 
     #[cfg(rcc_l4plus)]
@@ -266,6 +272,22 @@ pub(crate) unsafe fn init(config: Config) {
         pclk2: apb2_freq,
         pclk1_tim: apb1_tim_freq,
         pclk2_tim: apb2_tim_freq,
+        #[cfg(rcc_l4)]
+        hsi: None,
+        #[cfg(rcc_l4)]
+        lse: None,
+        #[cfg(rcc_l4)]
+        pllsai1_p: None,
+        #[cfg(rcc_l4)]
+        pllsai2_p: None,
+        #[cfg(rcc_l4)]
+        pll1_p: None,
+        #[cfg(rcc_l4)]
+        pll1_q: None,
+        #[cfg(rcc_l4)]
+        sai1_extclk: None,
+        #[cfg(rcc_l4)]
+        sai2_extclk: None,
         rtc,
     });
 }
@@ -341,7 +363,10 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
     let pll_src = match pll.source {
         PLLSource::NONE => panic!("must not select PLL source as NONE"),
         PLLSource::HSE => input.hse,
+        #[cfg(rcc_l5)]
         PLLSource::HSI16 => input.hsi16,
+        #[cfg(not(rcc_l5))]
+        PLLSource::HSI => input.hsi16,
         PLLSource::MSI => input.msi,
     };
 
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 8df6deaa..d587a198 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -110,14 +110,18 @@ pub struct Clocks {
     #[cfg(all(rcc_f4, not(stm32f410)))]
     pub plli2s1_r: Option<Hertz>,
 
+    #[cfg(rcc_l4)]
+    pub pllsai1_p: Option<Hertz>,
     #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
     pub pllsai1_q: Option<Hertz>,
     #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
     pub pllsai1_r: Option<Hertz>,
+    #[cfg(rcc_l4)]
+    pub pllsai2_p: Option<Hertz>,
 
-    #[cfg(stm32g4)]
+    #[cfg(any(stm32g4, rcc_l4))]
     pub pll1_p: Option<Hertz>,
-    #[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
+    #[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_l4))]
     pub pll1_q: Option<Hertz>,
     #[cfg(any(stm32h5, stm32h7))]
     pub pll2_p: Option<Hertz>,
@@ -154,7 +158,7 @@ pub struct Clocks {
 
     pub rtc: Option<Hertz>,
 
-    #[cfg(any(stm32h5, stm32h7))]
+    #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
     pub hsi: Option<Hertz>,
     #[cfg(stm32h5)]
     pub hsi48: Option<Hertz>,
@@ -163,7 +167,7 @@ pub struct Clocks {
     #[cfg(any(stm32h5, stm32h7))]
     pub csi: Option<Hertz>,
 
-    #[cfg(any(stm32h5, stm32h7))]
+    #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
     pub lse: Option<Hertz>,
     #[cfg(any(stm32h5, stm32h7))]
     pub hse: Option<Hertz>,
@@ -175,6 +179,10 @@ pub struct Clocks {
 
     #[cfg(stm32h7)]
     pub rcc_pclk_d3: Option<Hertz>,
+    #[cfg(rcc_l4)]
+    pub sai1_extclk: Option<Hertz>,
+    #[cfg(rcc_l4)]
+    pub sai2_extclk: Option<Hertz>,
 }
 
 #[cfg(feature = "low-power")]
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 3d0c623f..a0ec5c33 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -13,7 +13,7 @@ fn main() -> ! {
     info!("Hello World!");
 
     pac::RCC.ccipr().modify(|w| {
-        w.set_adcsel(pac::rcc::vals::Adcsel::SYSCLK);
+        w.set_adcsel(pac::rcc::vals::Adcsel::SYS);
     });
     pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
 
diff --git a/examples/stm32l4/src/bin/mco.rs b/examples/stm32l4/src/bin/mco.rs
index 2833bb63..50487988 100644
--- a/examples/stm32l4/src/bin/mco.rs
+++ b/examples/stm32l4/src/bin/mco.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
-    let _mco = Mco::new(p.MCO, p.PA8, McoSource::HSI16, McoPrescaler::DIV1);
+    let _mco = Mco::new(p.MCO, p.PA8, McoSource::HSI, McoPrescaler::DIV1);
 
     let mut led = Output::new(p.PB14, Level::High, Speed::Low);
 
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index d184bcf7..49ae15e6 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL18,
         divp: None,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 3785c689..34361d11 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 6dc1b300..a802cdfc 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -290,7 +290,7 @@ pub fn config() -> Config {
         config.rcc.mux = ClockSrc::PLL;
         config.rcc.hsi16 = true;
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSI16,
+            source: PLLSource::HSI,
             prediv: PllPreDiv::DIV1,
             mul: PllMul::MUL18,
             divp: None,