feat(stm32:qspi): add support for QSPI in stm32
Implemented with help of Tomasz Grześ <tomasz.grzes@gmail.com>.
This commit is contained in:
Mateusz Butkiewicz
parent
732614579b
commit
6a802c4708
@ -427,6 +427,12 @@ fn main() {
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(("sdmmc", "D6"), quote!(crate::sdmmc::D6Pin)),
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(("sdmmc", "D6"), quote!(crate::sdmmc::D7Pin)),
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(("sdmmc", "D8"), quote!(crate::sdmmc::D8Pin)),
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(("quadspi", "BK1_IO0"), quote!(crate::qspi::D0Pin)),
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(("quadspi", "BK1_IO1"), quote!(crate::qspi::D1Pin)),
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(("quadspi", "BK1_IO2"), quote!(crate::qspi::D2Pin)),
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(("quadspi", "BK1_IO3"), quote!(crate::qspi::D3Pin)),
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(("quadspi", "CLK"), quote!(crate::qspi::SckPin)),
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(("quadspi", "BK1_NCS"), quote!(crate::qspi::NSSPin)),
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].into();
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for p in METADATA.peripherals {
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@ -507,6 +513,7 @@ fn main() {
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(("dcmi", "PSSI"), quote!(crate::dcmi::FrameDma)),
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// SDMMCv1 uses the same channel for both directions, so just implement for RX
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(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
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(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
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]
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.into();
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@ -48,6 +48,8 @@ pub mod crc;
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))]
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pub mod flash;
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pub mod pwm;
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#[cfg(quadspi)]
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pub mod qspi;
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#[cfg(rng)]
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pub mod rng;
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#[cfg(sdmmc)]
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@ -60,7 +62,6 @@ pub mod usart;
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pub mod usb;
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#[cfg(otg)]
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pub mod usb_otg;
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#[cfg(iwdg)]
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pub mod wdg;
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342
embassy-stm32/src/qspi/mod.rs
Normal file
342
embassy-stm32/src/qspi/mod.rs
Normal file
@ -0,0 +1,342 @@
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#![macro_use]
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::TransferOptions;
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use crate::gpio::sealed::AFType;
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use crate::gpio::AnyPin;
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use crate::pac::quadspi::Quadspi as Regs;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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pub struct QspiWidth;
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#[allow(dead_code)]
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impl QspiWidth {
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pub const NONE: u8 = 0b00;
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pub const SING: u8 = 0b01;
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pub const DUAL: u8 = 0b10;
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pub const QUAD: u8 = 0b11;
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}
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struct QspiMode;
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#[allow(dead_code)]
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impl QspiMode {
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pub const INDIRECT_WRITE: u8 = 0b00;
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pub const INDIRECT_READ: u8 = 0b01;
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pub const AUTO_POLLING: u8 = 0b10;
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pub const MEMORY_MAPPED: u8 = 0b11;
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}
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pub struct QspiTransaction {
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pub iwidth: u8,
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pub awidth: u8,
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pub dwidth: u8,
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pub instruction: u8,
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pub address: Option<u32>,
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pub dummy: u8,
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pub data_len: Option<usize>,
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}
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impl Default for QspiTransaction {
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fn default() -> Self {
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Self {
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iwidth: QspiWidth::NONE,
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awidth: QspiWidth::NONE,
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dwidth: QspiWidth::NONE,
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instruction: 0,
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address: None,
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dummy: 0,
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data_len: None,
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}
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}
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}
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pub struct Config {
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pub memory_size: u8,
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pub address_size: u8,
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pub prescaler: u8,
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pub fifo_threshold: u8,
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pub cs_high_time: u8,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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memory_size: 0,
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address_size: 2,
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prescaler: 128,
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fifo_threshold: 16,
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cs_high_time: 4,
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}
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}
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}
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#[allow(dead_code)]
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pub struct Qspi<'d, T: Instance, Dma> {
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_peri: PeripheralRef<'d, T>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: PeripheralRef<'d, Dma>,
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config: Config,
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}
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impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, d0, d1, d2, d3, sck, nss);
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unsafe {
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
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nss.set_speed(crate::gpio::Speed::VeryHigh);
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d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
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d0.set_speed(crate::gpio::Speed::VeryHigh);
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d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
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d1.set_speed(crate::gpio::Speed::VeryHigh);
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d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
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d2.set_speed(crate::gpio::Speed::VeryHigh);
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d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
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d3.set_speed(crate::gpio::Speed::VeryHigh);
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}
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Self::new_inner(
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peri,
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Some(d0.map_into()),
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Some(d1.map_into()),
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Some(d2.map_into()),
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Some(d3.map_into()),
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Some(sck.map_into()),
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Some(nss.map_into()),
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dma,
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config,
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)
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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T::enable();
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unsafe {
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T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold));
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while T::REGS.sr().read().busy() {}
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T::REGS.cr().write(|w| {
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w.set_prescaler(config.prescaler);
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w.set_en(true);
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});
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T::REGS.dcr().write(|w| {
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w.set_fsize(config.memory_size);
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w.set_csht(config.cs_high_time);
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w.set_ckmode(false);
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});
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}
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Self {
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_peri: peri,
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sck,
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d0,
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d1,
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d2,
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d3,
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nss,
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dma,
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config,
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}
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}
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pub fn command(&mut self, transaction: QspiTransaction) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction);
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn read(&mut self, buf: &mut [u8], transaction: QspiTransaction) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction);
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if let Some(len) = transaction.data_len {
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::INDIRECT_READ);
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});
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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for idx in 0..len {
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while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
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buf[idx] = *(T::REGS.dr().ptr() as *mut u8);
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}
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn write(&mut self, buf: &[u8], transaction: QspiTransaction) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction);
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if let Some(len) = transaction.data_len {
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::INDIRECT_WRITE);
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});
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for idx in 0..len {
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while !T::REGS.sr().read().ftf() {}
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*(T::REGS.dr().ptr() as *mut u8) = buf[idx];
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}
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn read_dma(&mut self, buf: &mut [u8], transaction: QspiTransaction)
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where
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Dma: QuadDma<T>,
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{
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unsafe {
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self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction);
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let request = self.dma.request();
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let options = TransferOptions::default();
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::INDIRECT_READ);
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});
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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self.dma
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.start_read(request, T::REGS.dr().ptr() as *mut u8, buf, options);
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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while self.dma.is_running() {}
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}
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}
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pub fn write_dma(&mut self, buf: &[u8], transaction: QspiTransaction)
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where
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Dma: QuadDma<T>,
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{
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unsafe {
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self.setup_transaction(QspiMode::INDIRECT_WRITE, &transaction);
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let request = self.dma.request();
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let options = TransferOptions::default();
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::INDIRECT_WRITE);
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});
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self.dma
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.start_write(request, buf, T::REGS.dr().ptr() as *mut u8, options);
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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while self.dma.is_running() {}
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}
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}
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fn setup_transaction(&mut self, fmode: u8, transaction: &QspiTransaction) {
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unsafe {
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T::REGS.fcr().modify(|v| {
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v.set_csmf(true);
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v.set_ctcf(true);
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v.set_ctef(true);
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v.set_ctof(true);
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});
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while T::REGS.sr().read().busy() {}
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if let Some(len) = transaction.data_len {
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T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
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}
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T::REGS.ccr().write(|v| {
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v.set_fmode(fmode);
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v.set_imode(transaction.iwidth);
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v.set_instruction(transaction.instruction);
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v.set_admode(transaction.awidth);
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v.set_adsize(self.config.address_size);
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v.set_dmode(transaction.dwidth);
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v.set_abmode(QspiWidth::NONE);
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v.set_dcyc(transaction.dummy);
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});
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if let Some(addr) = transaction.address {
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T::REGS.ar().write(|v| {
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v.set_address(addr);
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});
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}
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}
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub trait Instance {
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const REGS: Regs;
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}
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}
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
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pin_trait!(SckPin, Instance);
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pin_trait!(D0Pin, Instance);
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pin_trait!(D1Pin, Instance);
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pin_trait!(D2Pin, Instance);
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pin_trait!(D3Pin, Instance);
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pin_trait!(NSSPin, Instance);
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dma_trait!(QuadDma, Instance);
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foreach_peripheral!(
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(quadspi, $inst:ident) => {
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impl sealed::Instance for peripherals::$inst {
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const REGS: Regs = crate::pac::$inst;
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}
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impl Instance for peripherals::$inst {}
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};
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);
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