Tweak identifiers and comments

embassy-executor/src/arch/riscv32.rs

@@ -17,27 +17,22 @@ mod thread {
     static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
 
     #[export_name = "__thread_mode_pender"]
-    fn __thread_mode_pender(_core_id: OpaqueThreadContext) {
+    fn __thread_mode_pender(_context: OpaqueThreadContext) {
         SIGNAL_WORK_THREAD_MODE.store(true, Ordering::SeqCst);
     }
 
     /// TODO
     // Name pending
     #[derive(Default)] // Default enables Executor::new
-    pub struct RiscVThreadContext;
+    pub struct Context;
 
-    impl ThreadContext for RiscVThreadContext {
+    impl ThreadContext for Context {
         #[cfg(feature = "thread-context")]
         fn context(&self) -> OpaqueThreadContext {
             // Enabling thread-context is not incorrect, just wasteful.
             OpaqueThreadContext(0)
         }
 
-        #[cfg(not(feature = "thread-context"))]
-        fn context(&self) -> OpaqueThreadContext {
-            OpaqueThreadContext(())
-        }
-
         fn wait(&mut self) {
             // We do not care about race conditions between the load and store operations,
             // interrupts will only set this value to true.
@@ -60,5 +55,5 @@ mod thread {
 
     /// TODO
     // Type alias for backwards compatibility
-    pub type Executor = crate::thread::ThreadModeExecutor<RiscVThreadContext>;
+    pub type Executor = crate::thread::ThreadModeExecutor<Context>;
 }