From 28bf4b7b6da0e0f6ce0878580363f135c7e7a879 Mon Sep 17 00:00:00 2001 From: Daniel Bevenius Date: Fri, 23 Sep 2022 09:35:54 +0200 Subject: [PATCH] Add const for IOCTL ANTDIV --- src/lib.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index a6b26188..f543f75e 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -131,6 +131,7 @@ const IRQ_F3_INTR: u16 = 0x8000; const IOCTL_CMD_UP: u32 = 2; const IOCTL_CMD_SET_SSID: u32 = 26; +const IOCTL_CMD_ANTDIV: u32 = 64; const IOCTL_CMD_SET_VAR: u32 = 263; const IOCTL_CMD_GET_VAR: u32 = 262; const IOCTL_CMD_SET_PASSPHRASE: u32 = 268; @@ -310,7 +311,8 @@ impl<'a> Control<'a> { // set country takes some time, next ioctls fail if we don't wait. Timer::after(Duration::from_millis(100)).await; - self.ioctl_set_u32(64, 0, 0).await; // WLC_SET_ANTDIV + // Set antenna to chip antenna + self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await; self.set_iovar_u32("bus:txglom", 0).await; Timer::after(Duration::from_millis(100)).await;