stm32/wpan: convert to new ipcc
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xoviat
@ -1,7 +1,77 @@
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use core::future::poll_fn;
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use core::task::Poll;
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use atomic_polyfill::{compiler_fence, Ordering};
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use self::sealed::Instance;
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use crate::interrupt;
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use crate::interrupt::typelevel::Interrupt;
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use crate::peripherals::IPCC;
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use crate::rcc::sealed::RccPeripheral;
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/// Interrupt handler.
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pub struct ReceiveInterruptHandler {}
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impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for ReceiveInterruptHandler {
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unsafe fn on_interrupt() {
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let regs = IPCC::regs();
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let channels = [
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IpccChannel::Channel1,
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IpccChannel::Channel2,
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IpccChannel::Channel3,
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IpccChannel::Channel4,
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IpccChannel::Channel5,
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IpccChannel::Channel6,
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];
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// Status register gives channel occupied status. For rx, use cpu1.
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let sr = unsafe { regs.cpu(1).sr().read() };
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regs.cpu(0).mr().modify(|w| {
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for channel in channels {
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if sr.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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w.set_chom(channel as usize, true);
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// There shouldn't be a race because the channel is masked only if the interrupt has fired
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IPCC::state().rx_waker_for(channel).wake();
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}
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}
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})
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}
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}
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pub struct TransmitInterruptHandler {}
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impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for TransmitInterruptHandler {
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unsafe fn on_interrupt() {
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let regs = IPCC::regs();
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let channels = [
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IpccChannel::Channel1,
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IpccChannel::Channel2,
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IpccChannel::Channel3,
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IpccChannel::Channel4,
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IpccChannel::Channel5,
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IpccChannel::Channel6,
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];
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// Status register gives channel occupied status. For tx, use cpu0.
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let sr = unsafe { regs.cpu(0).sr().read() };
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regs.cpu(0).mr().modify(|w| {
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for channel in channels {
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if !sr.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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w.set_chfm(channel as usize, true);
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// There shouldn't be a race because the channel is masked only if the interrupt has fired
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IPCC::state().tx_waker_for(channel).wake();
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}
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}
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});
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}
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}
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#[non_exhaustive]
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#[derive(Clone, Copy, Default)]
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pub struct Config {
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@ -20,13 +90,6 @@ pub enum IpccChannel {
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Channel6 = 5,
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}
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pub mod sealed {
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pub trait Instance: crate::rcc::RccPeripheral {
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fn regs() -> crate::pac::ipcc::Ipcc;
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fn set_cpu2(enabled: bool);
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}
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}
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pub struct Ipcc;
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impl Ipcc {
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@ -45,115 +108,99 @@ impl Ipcc {
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w.set_txfie(true);
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})
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}
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// enable interrupts
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crate::interrupt::typelevel::IPCC_C1_RX::unpend();
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crate::interrupt::typelevel::IPCC_C1_TX::unpend();
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unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
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unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
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}
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pub fn c1_set_rx_channel(channel: IpccChannel, enabled: bool) {
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/// Send data to an IPCC channel. The closure is called to write the data when appropriate.
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pub async fn send(channel: IpccChannel, f: impl FnOnce()) {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
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}
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Self::flush(channel).await;
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compiler_fence(Ordering::SeqCst);
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pub fn c1_get_rx_channel(channel: IpccChannel) -> bool {
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let regs = IPCC::regs();
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f();
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// If bit is set to 1 then interrupt is disabled
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unsafe { !regs.cpu(0).mr().read().chom(channel as usize) }
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}
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#[allow(dead_code)]
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pub fn c2_set_rx_channel(channel: IpccChannel, enabled: bool) {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { regs.cpu(1).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
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}
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#[allow(dead_code)]
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pub fn c2_get_rx_channel(channel: IpccChannel) -> bool {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { !regs.cpu(1).mr().read().chom(channel as usize) }
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}
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pub fn c1_set_tx_channel(channel: IpccChannel, enabled: bool) {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
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}
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pub fn c1_get_tx_channel(channel: IpccChannel) -> bool {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { !regs.cpu(0).mr().read().chfm(channel as usize) }
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}
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#[allow(dead_code)]
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pub fn c2_set_tx_channel(channel: IpccChannel, enabled: bool) {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { regs.cpu(1).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
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}
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#[allow(dead_code)]
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pub fn c2_get_tx_channel(channel: IpccChannel) -> bool {
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let regs = IPCC::regs();
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// If bit is set to 1 then interrupt is disabled
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unsafe { !regs.cpu(1).mr().read().chfm(channel as usize) }
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}
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/// clears IPCC receive channel status for CPU1
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pub fn c1_clear_flag_channel(channel: IpccChannel) {
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let regs = IPCC::regs();
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trace!("ipcc: ch {}: clear rx", channel as u8);
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unsafe { regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true)) }
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}
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#[allow(dead_code)]
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/// clears IPCC receive channel status for CPU2
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pub fn c2_clear_flag_channel(channel: IpccChannel) {
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let regs = IPCC::regs();
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unsafe { regs.cpu(1).scr().write(|w| w.set_chc(channel as usize, true)) }
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}
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pub fn c1_set_flag_channel(channel: IpccChannel) {
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let regs = IPCC::regs();
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compiler_fence(Ordering::SeqCst);
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trace!("ipcc: ch {}: send data", channel as u8);
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unsafe { regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true)) }
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}
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#[allow(dead_code)]
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pub fn c2_set_flag_channel(channel: IpccChannel) {
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/// Wait for the tx channel to become clear
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pub async fn flush(channel: IpccChannel) {
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let regs = IPCC::regs();
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unsafe { regs.cpu(1).scr().write(|w| w.set_chs(channel as usize, true)) }
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// This is a race, but is nice for debugging
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if unsafe { regs.cpu(0).sr().read() }.chf(channel as usize) {
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trace!("ipcc: ch {}: wait for tx free", channel as u8);
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}
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poll_fn(|cx| {
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IPCC::state().tx_waker_for(channel).register(cx.waker());
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// If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, false)) }
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compiler_fence(Ordering::SeqCst);
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if !unsafe { regs.cpu(0).sr().read() }.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true)) }
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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}
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pub fn c1_is_active_flag(channel: IpccChannel) -> bool {
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/// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
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pub async fn receive<R>(channel: IpccChannel, mut f: impl FnMut() -> Option<R>) -> R {
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let regs = IPCC::regs();
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unsafe { regs.cpu(0).sr().read().chf(channel as usize) }
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}
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loop {
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// This is a race, but is nice for debugging
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if !unsafe { regs.cpu(1).sr().read() }.chf(channel as usize) {
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trace!("ipcc: ch {}: wait for rx occupied", channel as u8);
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}
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pub fn c2_is_active_flag(channel: IpccChannel) -> bool {
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let regs = IPCC::regs();
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poll_fn(|cx| {
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IPCC::state().rx_waker_for(channel).register(cx.waker());
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// If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, false)) }
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unsafe { regs.cpu(1).sr().read().chf(channel as usize) }
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}
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compiler_fence(Ordering::SeqCst);
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pub fn is_tx_pending(channel: IpccChannel) -> bool {
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!Self::c1_is_active_flag(channel) && Self::c1_get_tx_channel(channel)
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}
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if unsafe { regs.cpu(1).sr().read() }.chf(channel as usize) {
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// If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
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unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true)) }
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pub fn is_rx_pending(channel: IpccChannel) -> bool {
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Self::c2_is_active_flag(channel) && Self::c1_get_rx_channel(channel)
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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trace!("ipcc: ch {}: read data", channel as u8);
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compiler_fence(Ordering::SeqCst);
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match f() {
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Some(ret) => return ret,
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None => {}
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}
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trace!("ipcc: ch {}: clear rx", channel as u8);
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compiler_fence(Ordering::SeqCst);
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// If the channel is clear and the read function returns none, fetch more data
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unsafe { regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true)) }
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}
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}
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}
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@ -165,9 +212,66 @@ impl sealed::Instance for crate::peripherals::IPCC {
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fn set_cpu2(enabled: bool) {
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unsafe { crate::pac::PWR.cr4().modify(|w| w.set_c2boot(enabled)) }
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}
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fn state() -> &'static self::sealed::State {
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static STATE: self::sealed::State = self::sealed::State::new();
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&STATE
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}
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}
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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use super::*;
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pub struct State {
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rx_wakers: [AtomicWaker; 6],
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tx_wakers: [AtomicWaker; 6],
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}
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impl State {
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pub const fn new() -> Self {
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const WAKER: AtomicWaker = AtomicWaker::new();
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Self {
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rx_wakers: [WAKER; 6],
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tx_wakers: [WAKER; 6],
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}
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}
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pub fn rx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
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match channel {
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IpccChannel::Channel1 => &self.rx_wakers[0],
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IpccChannel::Channel2 => &self.rx_wakers[1],
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IpccChannel::Channel3 => &self.rx_wakers[2],
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IpccChannel::Channel4 => &self.rx_wakers[3],
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IpccChannel::Channel5 => &self.rx_wakers[4],
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IpccChannel::Channel6 => &self.rx_wakers[5],
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}
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}
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pub fn tx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
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match channel {
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IpccChannel::Channel1 => &self.tx_wakers[0],
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IpccChannel::Channel2 => &self.tx_wakers[1],
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IpccChannel::Channel3 => &self.tx_wakers[2],
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IpccChannel::Channel4 => &self.tx_wakers[3],
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IpccChannel::Channel5 => &self.tx_wakers[4],
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IpccChannel::Channel6 => &self.tx_wakers[5],
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}
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}
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}
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pub trait Instance: crate::rcc::RccPeripheral {
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fn regs() -> crate::pac::ipcc::Ipcc;
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fn set_cpu2(enabled: bool);
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fn state() -> &'static State;
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}
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}
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unsafe fn _configure_pwr() {
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// TODO: move this to RCC
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let pwr = crate::pac::PWR;
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let rcc = crate::pac::RCC;
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