Add missing parts and Cleanup
This commit is contained in:
Christian Perez Llamas
parent
1ed260b105
commit
6b88057aef
@ -1,27 +1,27 @@
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#![macro_use]
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//! I2S
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//! Support for I2S audio
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_cortex_m::interrupt::{InterruptExt, Priority};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::interrupt::Interrupt;
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use crate::pac::i2s::{RegisterBlock, CONFIG, PSEL};
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use crate::pac::i2s::RegisterBlock;
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use crate::Peripheral;
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// TODO: Define those in lib.rs somewhere else
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//
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// I2S EasyDMA MAXCNT bit length = 14
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/// I2S EasyDMA MAXCNT bit length = 14
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const MAX_DMA_MAXCNT: u32 = 1 << 14;
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// Limits for Easy DMA - it can only read from data ram
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/// Limits for Easy DMA - it can only read from data ram
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pub const SRAM_LOWER: usize = 0x2000_0000;
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pub const SRAM_UPPER: usize = 0x3000_0000;
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@ -36,35 +36,144 @@ pub enum Error {
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BufferLengthMisaligned,
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}
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pub const MODE_MASTER_8000: Mode = Mode::Master {
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freq: MckFreq::_32MDiv125,
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ratio: Ratio::_32x,
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}; // error = 0
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pub const MODE_MASTER_11025: Mode = Mode::Master {
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/// Approximate sample rates.
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///
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/// Those are common sample rates that can not be configured without an small error.
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///
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/// For custom master clock configuration, please refer to [Mode].
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#[derive(Clone, Copy)]
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pub enum ApproxSampleRate {
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_11025,
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_16000,
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_22050,
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_32000,
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_44100,
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_48000,
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}
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impl From<ApproxSampleRate> for Mode {
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fn from(value: ApproxSampleRate) -> Self {
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match value {
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// error = 86
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ApproxSampleRate::_11025 => Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_192x,
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}; // error = 86
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pub const MODE_MASTER_16000: Mode = Mode::Master {
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},
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// error = 127
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ApproxSampleRate::_16000 => Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_96x,
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}; // error = 127
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pub const MODE_MASTER_22050: Mode = Mode::Master {
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},
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// error = 172
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ApproxSampleRate::_22050 => Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_96x,
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}; // error = 172
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pub const MODE_MASTER_32000: Mode = Mode::Master {
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},
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// error = 254
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ApproxSampleRate::_32000 => Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_48x,
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}; // error = 254
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pub const MODE_MASTER_44100: Mode = Mode::Master {
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},
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// error = 344
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ApproxSampleRate::_44100 => Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_48x,
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}; // error = 344
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pub const MODE_MASTER_48000: Mode = Mode::Master {
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},
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// error = 381
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ApproxSampleRate::_48000 => Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_32x,
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}; // error = 381
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},
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}
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}
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}
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impl ApproxSampleRate {
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pub fn sample_rate(&self) -> u32 {
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// This will always provide a Master mode, so it is safe to unwrap.
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Mode::from(*self).sample_rate().unwrap()
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}
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}
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/// Exact sample rates.
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///
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/// Those are non standard sample rates that can be configured without error.
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///
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/// For custom master clock configuration, please refer to [Mode].
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#[derive(Clone, Copy)]
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pub enum ExactSampleRate {
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_8000,
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_10582,
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_12500,
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_15625,
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_15873,
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_25000,
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_31250,
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_50000,
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_62500,
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_100000,
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_125000,
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}
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impl ExactSampleRate {
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pub fn sample_rate(&self) -> u32 {
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// This will always provide a Master mode, so it is safe to unwrap.
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Mode::from(*self).sample_rate().unwrap()
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}
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}
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impl From<ExactSampleRate> for Mode {
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fn from(value: ExactSampleRate) -> Self {
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match value {
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ExactSampleRate::_8000 => Mode::Master {
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freq: MckFreq::_32MDiv125,
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ratio: Ratio::_32x,
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},
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ExactSampleRate::_10582 => Mode::Master {
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freq: MckFreq::_32MDiv63,
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ratio: Ratio::_48x,
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},
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ExactSampleRate::_12500 => Mode::Master {
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freq: MckFreq::_32MDiv10,
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ratio: Ratio::_256x,
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},
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ExactSampleRate::_15625 => Mode::Master {
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freq: MckFreq::_32MDiv32,
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ratio: Ratio::_64x,
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},
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ExactSampleRate::_15873 => Mode::Master {
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freq: MckFreq::_32MDiv63,
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ratio: Ratio::_32x,
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},
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ExactSampleRate::_25000 => Mode::Master {
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freq: MckFreq::_32MDiv10,
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ratio: Ratio::_128x,
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},
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ExactSampleRate::_31250 => Mode::Master {
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freq: MckFreq::_32MDiv32,
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ratio: Ratio::_32x,
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},
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ExactSampleRate::_50000 => Mode::Master {
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freq: MckFreq::_32MDiv10,
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ratio: Ratio::_64x,
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},
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ExactSampleRate::_62500 => Mode::Master {
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freq: MckFreq::_32MDiv16,
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ratio: Ratio::_32x,
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},
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ExactSampleRate::_100000 => Mode::Master {
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freq: MckFreq::_32MDiv10,
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ratio: Ratio::_32x,
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},
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ExactSampleRate::_125000 => Mode::Master {
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freq: MckFreq::_32MDiv8,
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ratio: Ratio::_32x,
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},
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}
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}
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}
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/// I2S configuration.
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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@ -78,7 +187,7 @@ pub struct Config {
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: MODE_MASTER_32000,
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mode: ExactSampleRate::_31250.into(),
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swidth: SampleWidth::_16bit,
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align: Align::Left,
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format: Format::I2S,
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@ -132,10 +241,12 @@ impl MckFreq {
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256000,
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];
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/// Return the value that needs to be written to the register.
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pub fn to_register_value(&self) -> u32 {
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Self::REGISTER_VALUES[usize::from(*self)]
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}
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/// Return the master clock frequency.
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pub fn to_frequency(&self) -> u32 {
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Self::FREQUENCIES[usize::from(*self)]
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}
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@ -147,7 +258,10 @@ impl From<MckFreq> for usize {
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}
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}
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/// MCK / LRCK ratio.
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/// Master clock frequency ratio
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///
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/// Sample Rate = LRCK = MCK / Ratio
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///
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Ratio {
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_32x,
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@ -175,6 +289,7 @@ impl From<Ratio> for u8 {
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}
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}
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/// Sample width.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum SampleWidth {
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_8bit,
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@ -188,7 +303,7 @@ impl From<SampleWidth> for u8 {
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}
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}
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/// Alignment of sample within a frame.
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/// Channel used for the most significant sample value in a frame.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Align {
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Left,
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@ -220,11 +335,13 @@ impl From<Format> for bool {
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}
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}
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/// Enable channels.
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/// Channels
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Channels {
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Stereo,
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/// Mono left
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Left,
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/// Mono right
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Right,
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}
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@ -235,8 +352,6 @@ impl From<Channels> for u8 {
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}
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/// Interface to the I2S peripheral using EasyDMA to offload the transmission and reception workload.
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///
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/// For more details about EasyDMA, consult the module documentation.
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pub struct I2S<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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@ -278,29 +393,32 @@ impl<'d, T: Instance> I2S<'d, T> {
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) -> Self {
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into_ref!(i2s, irq, mck, sck, lrck, sdin, sdout);
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let r = T::regs();
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Self::apply_config(&r.config, &config);
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Self::select_pins(&r.psel, mck, sck, lrck, sdin, sdout);
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Self::setup_interrupt(irq, r);
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Self::apply_config(&config);
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Self::select_pins(mck, sck, lrck, sdin, sdout);
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Self::setup_interrupt(irq);
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r.enable.write(|w| w.enable().enabled());
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T::regs().enable.write(|w| w.enable().enabled());
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Self { _p: i2s }
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}
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/// I2S output only
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pub fn output(self) -> Output<'d, T> {
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Output { _p: self._p }
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}
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/// I2S input only
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pub fn input(self) -> Input<'d, T> {
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Input { _p: self._p }
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}
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/// I2S full duplex (input and output)
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pub fn full_duplex(self) -> FullDuplex<'d, T> {
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FullDuplex { _p: self._p }
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}
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fn apply_config(c: &CONFIG, config: &Config) {
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fn apply_config(config: &Config) {
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let c = &T::regs().config;
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match config.mode {
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Mode::Master { freq, ratio } => {
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c.mode.write(|w| w.mode().master());
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@ -322,13 +440,14 @@ impl<'d, T: Instance> I2S<'d, T> {
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}
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fn select_pins(
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psel: &PSEL,
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mck: PeripheralRef<'d, AnyPin>,
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sck: PeripheralRef<'d, AnyPin>,
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lrck: PeripheralRef<'d, AnyPin>,
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sdin: PeripheralRef<'d, AnyPin>,
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sdout: PeripheralRef<'d, AnyPin>,
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) {
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let psel = &T::regs().psel;
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psel.mck.write(|w| {
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unsafe { w.bits(mck.psel_bits()) };
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w.connect().connected()
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@ -355,21 +474,23 @@ impl<'d, T: Instance> I2S<'d, T> {
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});
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}
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fn setup_interrupt(irq: PeripheralRef<'d, T::Interrupt>, r: &RegisterBlock) {
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fn setup_interrupt(irq: PeripheralRef<'d, T::Interrupt>) {
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irq.set_handler(Self::on_interrupt);
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// irq.set_priority(Priority::P1); // TODO review priorities
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irq.unpend();
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irq.enable();
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let device = Device::<T>::new();
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device.disable_tx_ptr_interrupt();
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device.disable_rx_ptr_interrupt();
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device.disable_stopped_interrupt();
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device.reset_tx_ptr_event();
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device.reset_rx_ptr_event();
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device.reset_stopped_event();
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device.enable_tx_ptr_interrupt();
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device.enable_rx_ptr_interrupt();
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device.enable_stopped_interrupt();
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}
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fn on_interrupt(_: *mut ()) {
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@ -387,41 +508,40 @@ impl<'d, T: Instance> I2S<'d, T> {
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s.rx_waker.wake();
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device.disable_rx_ptr_interrupt();
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}
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if device.is_stopped() {
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trace!("STOPPED INT");
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s.stop_waker.wake();
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device.disable_stopped_interrupt();
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}
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}
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}
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pub struct Output<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Output<'d, T> {
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/// Starts I2S transfer.
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#[inline(always)]
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pub fn start<B>(&self, buffer: B) -> Result<(), Error>
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where
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B: Buffer,
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{
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// TODO what to do if it is started already?
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async fn stop() {
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compiler_fence(Ordering::SeqCst);
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let device = Device::<T>::new();
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device.enable();
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device.set_tx_buffer(buffer)?;
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device.enable_tx();
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device.start();
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device.stop();
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Ok(())
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T::state().started.store(false, Ordering::Relaxed);
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poll_fn(|cx| {
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T::state().stop_waker.register(cx.waker());
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if device.is_stopped() {
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trace!("STOP: Ready");
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device.reset_stopped_event();
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Poll::Ready(())
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} else {
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trace!("STOP: Pending");
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Poll::Pending
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}
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})
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.await;
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device.disable();
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}
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/// Stops the I2S transfer and waits until it has stopped.
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#[inline(always)]
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pub async fn stop(&self) {
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todo!()
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}
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/// Transmits the given `buffer`.
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/// Buffer address must be 4 byte aligned and located in RAM.
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#[allow(unused_mut)]
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pub async fn send<B>(&mut self, buffer: B) -> Result<(), Error>
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async fn send<B>(buffer: B) -> Result<(), Error>
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where
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B: Buffer,
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{
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@ -454,24 +574,191 @@ impl<'d, T: Instance> Output<'d, T> {
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Ok(())
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}
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async fn receive<B>(buffer: B) -> Result<(), Error>
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where
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B: Buffer,
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{
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trace!("RECEIVE: {}", buffer.bytes_ptr() as u32);
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let device = Device::<T>::new();
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let drop = device.on_rx_drop();
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compiler_fence(Ordering::SeqCst);
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poll_fn(|cx| {
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T::state().rx_waker.register(cx.waker());
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if device.is_rx_ptr_updated() {
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trace!("RX POLL: Ready");
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device.reset_rx_ptr_event();
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device.enable_rx_ptr_interrupt();
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Poll::Ready(())
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} else {
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trace!("RX POLL: Pending");
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Poll::Pending
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}
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})
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.await;
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device.set_rx_buffer(buffer)?;
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compiler_fence(Ordering::SeqCst);
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drop.defuse();
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Ok(())
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}
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}
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/// I2S output
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pub struct Output<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Output<'d, T> {
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/// Prepare the initial buffer and start the I2S transfer.
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pub async fn start<B>(&self, buffer: B) -> Result<(), Error>
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where
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B: Buffer,
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{
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let device = Device::<T>::new();
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let s = T::state();
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if s.started.load(Ordering::Relaxed) {
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self.stop().await;
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}
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device.enable();
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device.enable_tx();
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device.set_tx_buffer(buffer)?;
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s.started.store(true, Ordering::Relaxed);
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device.start();
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Ok(())
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}
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/// Stops the I2S transfer and waits until it has stopped.
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#[inline(always)]
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pub async fn stop(&self) {
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I2S::<T>::stop().await
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}
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/// Sets the given `buffer` for transmission in the DMA.
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/// Buffer address must be 4 byte aligned and located in RAM.
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/// The buffer must not be written while being used by the DMA,
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/// which takes two other `send`s being awaited.
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#[allow(unused_mut)]
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pub async fn send<B>(&mut self, buffer: B) -> Result<(), Error>
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where
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B: Buffer,
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{
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I2S::<T>::send(buffer).await
|
||||
}
|
||||
}
|
||||
|
||||
/// I2S input
|
||||
pub struct Input<'d, T: Instance> {
|
||||
_p: PeripheralRef<'d, T>,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Input<'d, T> {
|
||||
// TODO
|
||||
/// Prepare the initial buffer and start the I2S transfer.
|
||||
pub async fn start<B>(&self, buffer: B) -> Result<(), Error>
|
||||
where
|
||||
B: Buffer,
|
||||
{
|
||||
let device = Device::<T>::new();
|
||||
|
||||
let s = T::state();
|
||||
if s.started.load(Ordering::Relaxed) {
|
||||
self.stop().await;
|
||||
}
|
||||
|
||||
device.enable();
|
||||
device.enable_rx();
|
||||
device.set_rx_buffer(buffer)?;
|
||||
|
||||
s.started.store(true, Ordering::Relaxed);
|
||||
|
||||
device.start();
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Stops the I2S transfer and waits until it has stopped.
|
||||
#[inline(always)]
|
||||
pub async fn stop(&self) {
|
||||
I2S::<T>::stop().await
|
||||
}
|
||||
|
||||
/// Sets the given `buffer` for reception from the DMA.
|
||||
/// Buffer address must be 4 byte aligned and located in RAM.
|
||||
/// The buffer must not be read while being used by the DMA,
|
||||
/// which takes two other `receive`s being awaited.
|
||||
#[allow(unused_mut)]
|
||||
pub async fn receive<B>(&mut self, buffer: B) -> Result<(), Error>
|
||||
where
|
||||
B: Buffer,
|
||||
{
|
||||
I2S::<T>::receive(buffer).await
|
||||
}
|
||||
}
|
||||
|
||||
/// I2S ful duplex (input & output)
|
||||
pub struct FullDuplex<'d, T: Instance> {
|
||||
_p: PeripheralRef<'d, T>,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> FullDuplex<'d, T> {
|
||||
// TODO
|
||||
/// Prepare the initial buffers and start the I2S transfer.
|
||||
pub async fn start<B>(&self, buffer_out: B, buffer_in: B) -> Result<(), Error>
|
||||
where
|
||||
B: Buffer,
|
||||
{
|
||||
let device = Device::<T>::new();
|
||||
|
||||
let s = T::state();
|
||||
if s.started.load(Ordering::Relaxed) {
|
||||
self.stop().await;
|
||||
}
|
||||
|
||||
device.enable();
|
||||
device.enable_tx();
|
||||
device.enable_rx();
|
||||
device.set_tx_buffer(buffer_out)?;
|
||||
device.set_rx_buffer(buffer_in)?;
|
||||
|
||||
s.started.store(true, Ordering::Relaxed);
|
||||
|
||||
device.start();
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Stops the I2S transfer and waits until it has stopped.
|
||||
#[inline(always)]
|
||||
pub async fn stop(&self) {
|
||||
I2S::<T>::stop().await
|
||||
}
|
||||
|
||||
/// Sets the given `buffer_out` and `buffer_in` for transmission/reception from the DMA.
|
||||
/// Buffer address must be 4 byte aligned and located in RAM.
|
||||
/// The buffers must not be written/read while being used by the DMA,
|
||||
/// which takes two other `send_and_receive` operations being awaited.
|
||||
#[allow(unused_mut)]
|
||||
pub async fn send_and_receive<B>(&mut self, buffer_out: B, buffer_in: B) -> Result<(), Error>
|
||||
where
|
||||
B: Buffer,
|
||||
{
|
||||
I2S::<T>::send(buffer_out).await?;
|
||||
I2S::<T>::receive(buffer_in).await?;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Helper encapsulating common I2S device operations.
|
||||
struct Device<T>(&'static RegisterBlock, PhantomData<T>);
|
||||
|
||||
impl<T: Instance> Device<T> {
|
||||
@ -521,6 +808,34 @@ impl<T: Instance> Device<T> {
|
||||
self.0.tasks_start.write(|w| unsafe { w.bits(1) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn stop(&self) {
|
||||
self.0.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn is_stopped(&self) -> bool {
|
||||
self.0.events_stopped.read().bits() != 0
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn reset_stopped_event(&self) {
|
||||
trace!("STOPPED EVENT: Reset");
|
||||
self.0.events_stopped.reset();
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn disable_stopped_interrupt(&self) {
|
||||
trace!("STOPPED INTERRUPT: Disabled");
|
||||
self.0.intenclr.write(|w| w.stopped().clear());
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn enable_stopped_interrupt(&self) {
|
||||
trace!("STOPPED INTERRUPT: Enabled");
|
||||
self.0.intenset.write(|w| w.stopped().set());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn set_tx_buffer<B>(&self, buffer: B) -> Result<(), Error>
|
||||
where
|
||||
@ -606,6 +921,23 @@ impl<T: Instance> Device<T> {
|
||||
})
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn on_rx_drop(&self) -> OnDrop<fn()> {
|
||||
OnDrop::new(move || {
|
||||
trace!("RX DROP: Stopping");
|
||||
|
||||
let device = Device::<T>::new();
|
||||
device.disable_rx_ptr_interrupt();
|
||||
device.reset_rx_ptr_event();
|
||||
device.disable_rx();
|
||||
|
||||
// TX is stopped almost instantly, spinning is fine.
|
||||
while !device.is_rx_ptr_updated() {}
|
||||
|
||||
trace!("RX DROP: Stopped");
|
||||
})
|
||||
}
|
||||
|
||||
fn validate_buffer<B>(buffer: B) -> Result<(u32, u32), Error>
|
||||
where
|
||||
B: Buffer,
|
||||
@ -632,6 +964,56 @@ impl<T: Instance> Device<T> {
|
||||
}
|
||||
}
|
||||
|
||||
/// Sample details
|
||||
pub trait Sample: Sized + Copy + Default {
|
||||
const WIDTH: usize;
|
||||
const SCALE: Self;
|
||||
}
|
||||
|
||||
impl Sample for i8 {
|
||||
const WIDTH: usize = 8;
|
||||
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
||||
}
|
||||
|
||||
impl Sample for i16 {
|
||||
const WIDTH: usize = 16;
|
||||
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
||||
}
|
||||
|
||||
impl Sample for i32 {
|
||||
const WIDTH: usize = 24;
|
||||
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
||||
}
|
||||
|
||||
/// A 4-bytes aligned [Buffer].
|
||||
#[repr(align(4))]
|
||||
pub struct AlignedBuffer<T: Sample, const N: usize>([T; N]);
|
||||
|
||||
impl<T: Sample, const N: usize> AlignedBuffer<T, N> {
|
||||
pub fn new(array: [T; N]) -> Self {
|
||||
Self(array)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Sample, const N: usize> Default for AlignedBuffer<T, N> {
|
||||
fn default() -> Self {
|
||||
Self([T::default(); N])
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Sample, const N: usize> AsRef<[T]> for AlignedBuffer<T, N> {
|
||||
fn as_ref(&self) -> &[T] {
|
||||
self.0.as_slice()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Sample, const N: usize> AsMut<[T]> for AlignedBuffer<T, N> {
|
||||
fn as_mut(&mut self) -> &mut [T] {
|
||||
self.0.as_mut_slice()
|
||||
}
|
||||
}
|
||||
|
||||
/// Common operations required for a buffer to be used by the DMA
|
||||
pub trait Buffer: Sized {
|
||||
fn bytes_ptr(&self) -> *const u8;
|
||||
fn bytes_len(&self) -> usize;
|
||||
@ -674,22 +1056,25 @@ impl Buffer for &[i32] {
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use core::sync::atomic::AtomicI32;
|
||||
use core::sync::atomic::AtomicBool;
|
||||
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
use super::*;
|
||||
|
||||
/// Peripheral static state
|
||||
pub struct State {
|
||||
pub started: AtomicBool,
|
||||
pub rx_waker: AtomicWaker,
|
||||
pub tx_waker: AtomicWaker,
|
||||
pub stop_waker: AtomicWaker,
|
||||
}
|
||||
|
||||
impl State {
|
||||
pub const fn new() -> Self {
|
||||
Self {
|
||||
started: AtomicBool::new(false),
|
||||
rx_waker: AtomicWaker::new(),
|
||||
tx_waker: AtomicWaker::new(),
|
||||
stop_waker: AtomicWaker::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -704,8 +1089,6 @@ pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
|
||||
type Interrupt: Interrupt;
|
||||
}
|
||||
|
||||
// TODO: Unsure why this macro is flagged as unused by CI when in fact it's used elsewhere?
|
||||
#[allow(unused_macros)]
|
||||
macro_rules! impl_i2s {
|
||||
($type:ident, $pac_type:ident, $irq:ident) => {
|
||||
impl crate::i2s::sealed::Instance for peripherals::$type {
|
||||
|
||||
@ -4,59 +4,41 @@
|
||||
|
||||
use core::f32::consts::PI;
|
||||
|
||||
use defmt::{error, info, trace};
|
||||
use defmt::{error, info};
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_nrf::gpio::{Input, Pin, Pull};
|
||||
use embassy_nrf::i2s::{Channels, MckFreq, Mode, Ratio, SampleWidth, MODE_MASTER_32000};
|
||||
use embassy_nrf::pac::ficr::info;
|
||||
use embassy_nrf::{i2s, interrupt};
|
||||
use embassy_nrf::i2s::{self, Sample as _};
|
||||
use embassy_nrf::interrupt;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[repr(align(4))]
|
||||
pub struct AlignedBuffer<T: ?Sized>(T);
|
||||
|
||||
impl<T> AsRef<T> for AlignedBuffer<T> {
|
||||
fn as_ref(&self) -> &T {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> AsMut<T> for AlignedBuffer<T> {
|
||||
fn as_mut(&mut self) -> &mut T {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let p = embassy_nrf::init(Default::default());
|
||||
|
||||
let mut config = i2s::Config::default();
|
||||
config.mode = MODE_MASTER_32000;
|
||||
// config.mode = Mode::Master {
|
||||
// freq: MckFreq::_32MDiv10,
|
||||
// ratio: Ratio::_256x,
|
||||
// }; // 12500 Hz
|
||||
config.channels = Channels::Left;
|
||||
config.swidth = SampleWidth::_16bit;
|
||||
config.mode = i2s::ExactSampleRate::_50000.into();
|
||||
config.channels = i2s::Channels::Left;
|
||||
config.swidth = i2s::SampleWidth::_16bit;
|
||||
let sample_rate = config.mode.sample_rate().expect("I2S Master");
|
||||
let inv_sample_rate = 1.0 / sample_rate as f32;
|
||||
|
||||
info!("Sample rate: {}", sample_rate);
|
||||
|
||||
// Wait for a button press
|
||||
// use embassy_nrf::gpio::{Input, Pin, Pull};
|
||||
// let mut btn1 = Input::new(p.P1_00.degrade(), Pull::Up);
|
||||
// btn1.wait_for_low().await;
|
||||
|
||||
let irq = interrupt::take!(I2S);
|
||||
let mut i2s = i2s::I2S::new(p.I2S, irq, p.P0_28, p.P0_29, p.P0_31, p.P0_11, p.P0_30, config).output();
|
||||
let mut i2s = i2s::I2S::new(p.I2S, irq, p.P0_28, p.P0_29, p.P0_31, p.P0_27, p.P0_30, config)
|
||||
.output();
|
||||
|
||||
type Sample = i16;
|
||||
const MAX_UNIPOLAR_VALUE: Sample = (1 << 15) as Sample;
|
||||
const NUM_SAMPLES: usize = 2000;
|
||||
let mut buffers: [AlignedBuffer<[Sample; NUM_SAMPLES]>; 3] = [
|
||||
AlignedBuffer([0; NUM_SAMPLES]),
|
||||
AlignedBuffer([0; NUM_SAMPLES]),
|
||||
AlignedBuffer([0; NUM_SAMPLES]),
|
||||
const NUM_SAMPLES: usize = 6000;
|
||||
|
||||
let mut buffers: [i2s::AlignedBuffer<Sample, NUM_SAMPLES>; 3] = [
|
||||
i2s::AlignedBuffer::default(),
|
||||
i2s::AlignedBuffer::default(),
|
||||
i2s::AlignedBuffer::default(),
|
||||
];
|
||||
|
||||
let mut carrier = SineOsc::new();
|
||||
@ -66,32 +48,29 @@ async fn main(_spawner: Spawner) {
|
||||
freq_mod.set_amplitude(1.0);
|
||||
|
||||
let mut amp_mod = SineOsc::new();
|
||||
amp_mod.set_frequency(4.0, inv_sample_rate);
|
||||
amp_mod.set_frequency(16.0, inv_sample_rate);
|
||||
amp_mod.set_amplitude(0.5);
|
||||
|
||||
let mut generate = |buf: &mut [Sample]| {
|
||||
let ptr = buf as *const [Sample] as *const Sample as u32;
|
||||
trace!("GEN: {}", ptr);
|
||||
|
||||
for sample in &mut buf.as_mut().chunks_mut(1) {
|
||||
let signal = carrier.generate();
|
||||
for sample in &mut buf.chunks_mut(1) {
|
||||
let freq_modulation = bipolar_to_unipolar(freq_mod.generate());
|
||||
carrier.set_frequency(220.0 + 220.0 * freq_modulation, inv_sample_rate);
|
||||
carrier.set_frequency(220.0 + 440.0 * freq_modulation, inv_sample_rate);
|
||||
let amp_modulation = bipolar_to_unipolar(amp_mod.generate());
|
||||
carrier.set_amplitude(amp_modulation);
|
||||
let value = (MAX_UNIPOLAR_VALUE as f32 * signal) as Sample;
|
||||
let signal = carrier.generate();
|
||||
let value = (Sample::SCALE as f32 * signal) as Sample;
|
||||
sample[0] = value;
|
||||
}
|
||||
};
|
||||
|
||||
generate(buffers[0].as_mut().as_mut_slice());
|
||||
generate(buffers[1].as_mut().as_mut_slice());
|
||||
generate(buffers[0].as_mut());
|
||||
generate(buffers[1].as_mut());
|
||||
|
||||
i2s.start(buffers[0].as_ref().as_slice()).expect("I2S Start");
|
||||
i2s.start(buffers[0].as_ref()).await.expect("I2S Start");
|
||||
|
||||
let mut index = 1;
|
||||
loop {
|
||||
if let Err(err) = i2s.send(buffers[index].as_ref().as_slice()).await {
|
||||
if let Err(err) = i2s.send(buffers[index].as_ref()).await {
|
||||
error!("{}", err);
|
||||
}
|
||||
|
||||
@ -99,7 +78,7 @@ async fn main(_spawner: Spawner) {
|
||||
if index >= 3 {
|
||||
index = 0;
|
||||
}
|
||||
generate(buffers[index].as_mut().as_mut_slice());
|
||||
generate(buffers[index].as_mut());
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user