rp/gpio: fix wait_for_* when multiple pins are in use.
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89e2e25d6f
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6c10fa44d0
@ -152,7 +152,8 @@ unsafe fn IO_IRQ_BANK0() {
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let event = (intsx.read().0 >> pin_group * 4) & 0xf as u32;
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if let Some(trigger) = InterruptTrigger::from_u32(event) {
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proc_intx.inte(pin / 8).write(|w| match trigger {
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critical_section::with(|_| {
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proc_intx.inte(pin / 8).modify(|w| match trigger {
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InterruptTrigger::AnyEdge => {
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w.set_edge_high(pin_group, false);
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w.set_edge_low(pin_group, false);
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@ -171,6 +172,7 @@ unsafe fn IO_IRQ_BANK0() {
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w.set_edge_low(pin_group, false);
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}
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});
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});
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INTERRUPT_WAKERS[pin as usize].wake();
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}
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}
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@ -193,7 +195,8 @@ impl<'d, T: Pin> InputFuture<'d, T> {
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// pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,
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// and EGDE_HIGH.
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let pin_group = (pin.pin() % 8) as usize;
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pin.int_proc().inte((pin.pin() / 8) as usize).write(|w| match level {
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critical_section::with(|_| {
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pin.int_proc().inte((pin.pin() / 8) as usize).modify(|w| match level {
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InterruptTrigger::LevelHigh => {
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debug!("InputFuture::new enable LevelHigh for pin {} \n", pin.pin());
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w.set_level_high(pin_group, true);
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@ -211,6 +214,7 @@ impl<'d, T: Pin> InputFuture<'d, T> {
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// noop
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}
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});
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});
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irq.enable();
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}
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