Wait until there's enough space in tx buffer, remove busy wait for completed send
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bbd687fcb0
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@ -123,31 +123,14 @@ impl<SPI: SpiDevice> W5500<SPI> {
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/// Write an ethernet frame to the device. Returns number of bytes written
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/// Write an ethernet frame to the device. Returns number of bytes written
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pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
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pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
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let max_size = socket::get_tx_free_size(&mut self.bus).await? as usize;
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while socket::get_tx_free_size(&mut self.bus).await? < frame.len() as u16 {}
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let write_data = if frame.len() < max_size {
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frame
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} else {
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&frame[..max_size]
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};
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let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
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let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
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self.bus
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self.bus
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.write_frame(RegisterBlock::TxBuf, write_ptr, write_data)
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.write_frame(RegisterBlock::TxBuf, write_ptr, frame)
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.await?;
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.await?;
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socket::set_tx_write_ptr(
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socket::set_tx_write_ptr(&mut self.bus, write_ptr.wrapping_add(frame.len() as u16)).await?;
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&mut self.bus,
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write_ptr.wrapping_add(write_data.len() as u16),
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)
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.await?;
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socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
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socket::command(&mut self.bus, socket::Command::Send).await?;
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socket::command(&mut self.bus, socket::Command::Send).await?;
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// Wait for TX to complete
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Ok(frame.len())
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while !socket::is_interrupt(&mut self.bus, socket::Interrupt::SendOk).await? {}
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socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
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Ok(write_data.len())
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}
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}
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pub async fn is_link_up(&mut self) -> bool {
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pub async fn is_link_up(&mut self) -> bool {
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@ -22,7 +22,6 @@ pub enum Command {
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pub const INTR: u16 = 0x02;
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pub const INTR: u16 = 0x02;
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#[repr(u8)]
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#[repr(u8)]
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pub enum Interrupt {
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pub enum Interrupt {
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SendOk = 0b010000_u8,
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Receive = 0b00100_u8,
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Receive = 0b00100_u8,
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}
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}
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@ -34,16 +33,6 @@ pub async fn reset_interrupt<SPI: SpiDevice>(
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bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
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bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
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}
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}
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pub async fn is_interrupt<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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code: Interrupt,
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) -> Result<bool, SPI::Error> {
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let mut data = [0u8];
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bus.read_frame(RegisterBlock::Socket0, INTR, &mut data)
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.await?;
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Ok(data[0] & code as u8 != 0)
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}
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pub async fn get_tx_write_ptr<SPI: SpiDevice>(
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pub async fn get_tx_write_ptr<SPI: SpiDevice>(
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bus: &mut SpiInterface<SPI>,
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bus: &mut SpiInterface<SPI>,
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) -> Result<u16, SPI::Error> {
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) -> Result<u16, SPI::Error> {
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