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issue 2059 merge with embassy main

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This commit is contained in:
Tyler Gilbert
2023-12-17 18:22:29 -06:00
parent 376eb101f7 c0cfd68c0c
commit 6c2ad332e8
335 changed files with 5869 additions and 5268 deletions
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45
embassy-stm32/Cargo.toml
View File

@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-stm32-v$VERSION/embassy-stm32/src/"
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-stm32/src/"
features = ["nightly", "defmt", "unstable-pac", "unstable-traits", "exti", "time-driver-any", "time"]
features = ["defmt", "unstable-pac", "exti", "time-driver-any", "time"]
flavors = [
{ regex_feature = "stm32f0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32f1.*", target = "thumbv7m-none-eabi" },
@ -32,22 +32,22 @@ flavors = [
]
[dependencies]
embassy-sync = { version = "0.4.0", path = "../embassy-sync" }
embassy-time = { version = "0.1.5", path = "../embassy-time", optional = true }
embassy-sync = { version = "0.5.0", path = "../embassy-sync" }
embassy-time = { version = "0.2", path = "../embassy-time", optional = true }
embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
embassy-hal-internal = {version = "0.1.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
embassy-executor = { version = "0.3.3", path = "../embassy-executor", optional = true }
embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver" }
embassy-executor = { version = "0.4.0", path = "../embassy-executor", optional = true }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
embedded-hal-nb = { version = "=1.0.0-rc.1", optional = true}
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.3" }
embedded-hal-async = { version = "=1.0.0-rc.3" }
embedded-hal-nb = { version = "=1.0.0-rc.3" }
embedded-storage = "0.3.0"
embedded-storage-async = { version = "0.4.0", optional = true }
embedded-storage = "0.3.1"
embedded-storage-async = { version = "0.4.1" }
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
@ -58,15 +58,14 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
stm32-metapac = { path = "../../stm32-data/build/stm32-metapac" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-91cee0d1fdcb4e447b65a09756b506f4af91b7e2" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
stm32-fmc = "0.3.0"
cfg-if = "1.0.0"
embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.0", optional = true }
embedded-io-async = { version = "0.6.1" }
chrono = { version = "^0.4", default-features = false, optional = true}
bit_field = "0.10.2"
document-features = "0.2.7"
@ -77,8 +76,8 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { path = "../../stm32-data/build/stm32-metapac", default-features = false, features = ["metadata"]}
#stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e6e51db6cdd7d533e52ca7a3237f7816a0486cd4", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-91cee0d1fdcb4e447b65a09756b506f4af91b7e2", default-features = false, features = ["metadata"]}
[features]
default = ["rt"]
@ -87,29 +86,21 @@ default = ["rt"]
rt = ["stm32-metapac/rt"]
## Use [`defmt`](https://docs.rs/defmt/latest/defmt/) for logging
defmt = ["dep:defmt", "bxcan/unstable-defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "embedded-io-async?/defmt-03", "embassy-usb-driver?/defmt", "embassy-net-driver/defmt", "embassy-time?/defmt"]
defmt = ["dep:defmt", "bxcan/unstable-defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "embedded-io-async/defmt-03", "embassy-usb-driver/defmt", "embassy-net-driver/defmt", "embassy-time?/defmt"]
exti = []
low-power = [ "dep:embassy-executor", "embassy-executor/arch-cortex-m" ]
low-power = [ "dep:embassy-executor", "embassy-executor?/arch-cortex-m" ]
low-power-debug-with-sleep = []
embassy-executor = []
## Automatically generate `memory.x` file using [`stm32-metapac`](https://docs.rs/stm32-metapac/)
memory-x = ["stm32-metapac/memory-x"]
## Enable nightly-only features
nightly = ["embedded-hal-1", "embedded-hal-async", "embedded-storage-async", "dep:embedded-io-async", "dep:embassy-usb-driver", "embassy-embedded-hal/nightly"]
## Re-export stm32-metapac at `embassy_stm32::pac`.
## This is unstable because semver-minor (non-breaking) releases of embassy-stm32 may major-bump (breaking) the stm32-metapac version.
## If this is an issue for you, you're encouraged to directly depend on a fixed version of the PAC.
## There are no plans to make this stable.
unstable-pac = []
## Implement embedded-hal 1.0 alpha traits.
## Implement embedded-hal-async traits if `nightly` is set as well.
unstable-traits = ["embedded-hal-1", "dep:embedded-hal-nb"]
#! ## Time
## Enables additional driver features that depend on embassy-time
@ -129,6 +120,10 @@ time-driver-tim3 = ["_time-driver"]
time-driver-tim4 = ["_time-driver"]
## Use TIM5 as time driver
time-driver-tim5 = ["_time-driver"]
## Use TIM9 as time driver
time-driver-tim9 = ["_time-driver"]
## Use TIM11 as time driver
time-driver-tim11 = ["_time-driver"]
## Use TIM12 as time driver
time-driver-tim12 = ["_time-driver"]
## Use TIM15 as time driver

12
embassy-stm32/build.rs
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@ -187,6 +187,8 @@ fn main() {
Some("tim3") => "TIM3",
Some("tim4") => "TIM4",
Some("tim5") => "TIM5",
Some("tim9") => "TIM9",
Some("tim11") => "TIM11",
Some("tim12") => "TIM12",
Some("tim15") => "TIM15",
Some("any") => {
@ -198,12 +200,16 @@ fn main() {
"TIM4"
} else if singletons.contains(&"TIM5".to_string()) {
"TIM5"
} else if singletons.contains(&"TIM9".to_string()) {
"TIM9"
} else if singletons.contains(&"TIM11".to_string()) {
"TIM11"
} else if singletons.contains(&"TIM12".to_string()) {
"TIM12"
} else if singletons.contains(&"TIM15".to_string()) {
"TIM15"
} else {
panic!("time-driver-any requested, but the chip doesn't have TIM2, TIM3, TIM4, TIM5, TIM12 or TIM15.")
panic!("time-driver-any requested, but the chip doesn't have TIM2, TIM3, TIM4, TIM5, TIM9, TIM11, TIM12 or TIM15.")
}
}
_ => panic!("unknown time_driver {:?}", time_driver),
@ -930,6 +936,10 @@ fn main() {
} else if pin.signal.starts_with("INN") {
// TODO handle in the future when embassy supports differential measurements
None
} else if pin.signal.starts_with("IN") && pin.signal.ends_with("b") {
// we number STM32L1 ADC bank 1 as 0..=31, bank 2 as 32..=63
let signal = pin.signal.strip_prefix("IN").unwrap().strip_suffix("b").unwrap();
Some(32u8 + signal.parse::<u8>().unwrap())
} else if pin.signal.starts_with("IN") {
Some(pin.signal.strip_prefix("IN").unwrap().parse().unwrap())
} else {

2
embassy-stm32/src/adc/f1.rs
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@ -148,7 +148,7 @@ impl<'d, T: Instance> Adc<'d, T> {
reg.set_cont(false);
reg.set_exttrig(true);
reg.set_swstart(false);
reg.set_extsel(crate::pac::adc::vals::Extsel::SWSTART);
reg.set_extsel(7); // SWSTART
});
// Configure the channel to sample

413
embassy-stm32/src/adc/f3_v1_1.rs Normal file
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@ -0,0 +1,413 @@
use core::future::poll_fn;
use core::marker::PhantomData;
use core::task::Poll;
use embassy_futures::yield_now;
use embassy_hal_internal::into_ref;
use embassy_time::Instant;
use super::Resolution;
use crate::adc::{Adc, AdcPin, Instance, SampleTime};
use crate::interrupt::typelevel::Interrupt;
use crate::time::Hertz;
use crate::{interrupt, Peripheral};
const ADC_FREQ: Hertz = crate::rcc::HSI_FREQ;
pub const VDDA_CALIB_MV: u32 = 3300;
pub const ADC_MAX: u32 = (1 << 12) - 1;
pub const VREF_INT: u32 = 1230;
pub enum AdcPowerMode {
AlwaysOn,
DelayOff,
IdleOff,
DelayIdleOff,
}
pub enum Prescaler {
Div1,
Div2,
Div3,
Div4,
}
/// Interrupt handler.
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
if T::regs().sr().read().eoc() {
T::regs().cr1().modify(|w| w.set_eocie(false));
} else {
return;
}
T::state().waker.wake();
}
}
fn update_vref<T: Instance>(op: i8) {
static VREF_STATUS: core::sync::atomic::AtomicU8 = core::sync::atomic::AtomicU8::new(0);
if op > 0 {
if VREF_STATUS.fetch_add(1, core::sync::atomic::Ordering::SeqCst) == 0 {
T::regs().ccr().modify(|w| w.set_tsvrefe(true));
}
} else {
if VREF_STATUS.fetch_sub(1, core::sync::atomic::Ordering::SeqCst) == 1 {
T::regs().ccr().modify(|w| w.set_tsvrefe(false));
}
}
}
pub struct Vref<T: Instance>(core::marker::PhantomData<T>);
impl<T: Instance> AdcPin<T> for Vref<T> {}
impl<T: Instance> super::sealed::AdcPin<T> for Vref<T> {
fn channel(&self) -> u8 {
17
}
}
impl<T: Instance> Vref<T> {
/// The value that vref would be if vdda was at 3000mv
pub fn calibrated_value(&self) -> u16 {
crate::pac::VREFINTCAL.data().read().value()
}
pub async fn calibrate(&mut self, adc: &mut Adc<'_, T>) -> Calibration {
let vref_val = adc.read(self).await;
Calibration {
vref_cal: self.calibrated_value(),
vref_val,
}
}
}
pub struct Calibration {
vref_cal: u16,
vref_val: u16,
}
impl Calibration {
/// The millivolts that the calibration value was measured at
pub const CALIBRATION_UV: u32 = 3_000_000;
/// Returns the measured VddA in microvolts (uV)
pub fn vdda_uv(&self) -> u32 {
(Self::CALIBRATION_UV * self.vref_cal as u32) / self.vref_val as u32
}
/// Returns the measured VddA as an f32
pub fn vdda_f32(&self) -> f32 {
(Self::CALIBRATION_UV as f32 / 1_000.0) * (self.vref_cal as f32 / self.vref_val as f32)
}
/// Returns a calibrated voltage value as in microvolts (uV)
pub fn cal_uv(&self, raw: u16, resolution: super::Resolution) -> u32 {
(self.vdda_uv() / resolution.to_max_count()) * raw as u32
}
/// Returns a calibrated voltage value as an f32
pub fn cal_f32(&self, raw: u16, resolution: super::Resolution) -> f32 {
raw as f32 * self.vdda_f32() / resolution.to_max_count() as f32
}
}
impl<T: Instance> Drop for Vref<T> {
fn drop(&mut self) {
update_vref::<T>(-1)
}
}
pub struct Temperature<T: Instance>(core::marker::PhantomData<T>);
impl<T: Instance> AdcPin<T> for Temperature<T> {}
impl<T: Instance> super::sealed::AdcPin<T> for Temperature<T> {
fn channel(&self) -> u8 {
16
}
}
impl<T: Instance> Drop for Temperature<T> {
fn drop(&mut self) {
update_vref::<T>(-1)
}
}
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(
adc: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
into_ref!(adc);
T::enable_and_reset();
//let r = T::regs();
//r.cr2().write(|w| w.set_align(true));
T::Interrupt::unpend();
unsafe {
T::Interrupt::enable();
}
Self { adc }
}
fn freq() -> Hertz {
let div = T::regs().ccr().read().adcpre() + 1;
ADC_FREQ / div as u32
}
pub async fn set_resolution(&mut self, res: Resolution) {
let was_on = Self::is_on();
if was_on {
self.stop_adc().await;
}
T::regs().cr1().modify(|w| w.set_res(res.into()));
if was_on {
self.start_adc().await;
}
}
pub fn resolution(&self) -> Resolution {
match T::regs().cr1().read().res() {
crate::pac::adc::vals::Res::TWELVEBIT => Resolution::TwelveBit,
crate::pac::adc::vals::Res::TENBIT => Resolution::TenBit,
crate::pac::adc::vals::Res::EIGHTBIT => Resolution::EightBit,
crate::pac::adc::vals::Res::SIXBIT => Resolution::SixBit,
}
}
pub fn enable_vref(&self) -> Vref<T> {
update_vref::<T>(1);
Vref(core::marker::PhantomData)
}
pub fn enable_temperature(&self) -> Temperature<T> {
T::regs().ccr().modify(|w| w.set_tsvrefe(true));
Temperature::<T>(core::marker::PhantomData)
}
/// Perform a single conversion.
async fn convert(&mut self) -> u16 {
let was_on = Self::is_on();
if !was_on {
self.start_adc().await;
}
self.wait_sample_ready().await;
T::regs().sr().write(|_| {});
T::regs().cr1().modify(|w| {
w.set_eocie(true);
w.set_scan(false);
});
T::regs().cr2().modify(|w| {
w.set_swstart(true);
w.set_cont(false);
}); // swstart cleared by HW
let res = poll_fn(|cx| {
T::state().waker.register(cx.waker());
if T::regs().sr().read().eoc() {
let res = T::regs().dr().read().rdata();
Poll::Ready(res)
} else {
Poll::Pending
}
})
.await;
if !was_on {
self.stop_adc().await;
}
res
}
#[inline(always)]
fn is_on() -> bool {
T::regs().sr().read().adons() || T::regs().cr2().read().adon()
}
pub async fn start_adc(&self) {
//defmt::trace!("Turn ADC on");
T::regs().cr2().modify(|w| w.set_adon(true));
//defmt::trace!("Waiting for ADC to turn on");
let mut t = Instant::now();
while !T::regs().sr().read().adons() {
yield_now().await;
if t.elapsed() > embassy_time::Duration::from_millis(1000) {
t = Instant::now();
//defmt::trace!("ADC still not on");
}
}
//defmt::trace!("ADC on");
}
pub async fn stop_adc(&self) {
if T::regs().cr2().read().adon() {
//defmt::trace!("ADC should be on, wait for it to start");
while !T::regs().csr().read().adons1() {
yield_now().await;
}
}
//defmt::trace!("Turn ADC off");
T::regs().cr2().modify(|w| w.set_adon(false));
//defmt::trace!("Waiting for ADC to turn off");
while T::regs().csr().read().adons1() {
yield_now().await;
}
}
pub async fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
self.set_sample_sequence(&[pin.channel()]).await;
self.convert().await
}
async fn wait_sample_ready(&self) {
//trace!("Waiting for sample channel to be ready");
while T::regs().sr().read().rcnr() {
yield_now().await;
}
}
pub async fn set_sample_time(&mut self, pin: &mut impl AdcPin<T>, sample_time: SampleTime) {
if Self::get_channel_sample_time(pin.channel()) != sample_time {
self.stop_adc().await;
unsafe {
Self::set_channel_sample_time(pin.channel(), sample_time);
}
self.start_adc().await;
}
}
pub fn get_sample_time(&self, pin: &impl AdcPin<T>) -> SampleTime {
Self::get_channel_sample_time(pin.channel())
}
/// Sets the channel sample time
///
/// ## SAFETY:
/// - ADON == 0 i.e ADC must not be enabled when this is called.
unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
let sample_time = sample_time.into();
match ch {
0..=9 => T::regs().smpr3().modify(|reg| reg.set_smp(ch as _, sample_time)),
10..=19 => T::regs()
.smpr2()
.modify(|reg| reg.set_smp(ch as usize - 10, sample_time)),
20..=29 => T::regs()
.smpr1()
.modify(|reg| reg.set_smp(ch as usize - 20, sample_time)),
30..=31 => T::regs()
.smpr0()
.modify(|reg| reg.set_smp(ch as usize - 30, sample_time)),
_ => panic!("Invalid channel to sample"),
}
}
fn get_channel_sample_time(ch: u8) -> SampleTime {
match ch {
0..=9 => T::regs().smpr3().read().smp(ch as _),
10..=19 => T::regs().smpr2().read().smp(ch as usize - 10),
20..=29 => T::regs().smpr1().read().smp(ch as usize - 20),
30..=31 => T::regs().smpr0().read().smp(ch as usize - 30),
_ => panic!("Invalid channel to sample"),
}
.into()
}
/// Sets the sequence to sample the ADC. Must be less than 28 elements.
async fn set_sample_sequence(&self, sequence: &[u8]) {
assert!(sequence.len() <= 28);
let mut iter = sequence.iter();
T::regs().sqr1().modify(|w| w.set_l((sequence.len() - 1) as _));
for (idx, ch) in iter.by_ref().take(6).enumerate() {
T::regs().sqr5().modify(|w| w.set_sq(idx, *ch));
}
for (idx, ch) in iter.by_ref().take(6).enumerate() {
T::regs().sqr4().modify(|w| w.set_sq(idx, *ch));
}
for (idx, ch) in iter.by_ref().take(6).enumerate() {
T::regs().sqr3().modify(|w| w.set_sq(idx, *ch));
}
for (idx, ch) in iter.by_ref().take(6).enumerate() {
T::regs().sqr2().modify(|w| w.set_sq(idx, *ch));
}
for (idx, ch) in iter.by_ref().take(4).enumerate() {
T::regs().sqr1().modify(|w| w.set_sq(idx, *ch));
}
}
fn get_res_clks(res: Resolution) -> u32 {
match res {
Resolution::TwelveBit => 12,
Resolution::TenBit => 11,
Resolution::EightBit => 9,
Resolution::SixBit => 7,
}
}
fn get_sample_time_clks(sample_time: SampleTime) -> u32 {
match sample_time {
SampleTime::Cycles4 => 4,
SampleTime::Cycles9 => 9,
SampleTime::Cycles16 => 16,
SampleTime::Cycles24 => 24,
SampleTime::Cycles48 => 48,
SampleTime::Cycles96 => 96,
SampleTime::Cycles192 => 192,
SampleTime::Cycles384 => 384,
}
}
pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
let res_clks = Self::get_res_clks(self.resolution());
let us_clks = us * Self::freq().0 / 1_000_000;
let clks = us_clks.saturating_sub(res_clks);
match clks {
0..=4 => SampleTime::Cycles4,
5..=9 => SampleTime::Cycles9,
10..=16 => SampleTime::Cycles16,
17..=24 => SampleTime::Cycles24,
25..=48 => SampleTime::Cycles48,
49..=96 => SampleTime::Cycles96,
97..=192 => SampleTime::Cycles192,
193.. => SampleTime::Cycles384,
}
}
pub fn us_for_cfg(&self, res: Resolution, sample_time: SampleTime) -> u32 {
let res_clks = Self::get_res_clks(res);
let sample_clks = Self::get_sample_time_clks(sample_time);
(res_clks + sample_clks) * 1_000_000 / Self::freq().0
}
}
impl<'d, T: Instance> Drop for Adc<'d, T> {
fn drop(&mut self) {
while !T::regs().sr().read().adons() {}
T::regs().cr2().modify(|w| w.set_adon(false));
T::disable();
}
}

27
embassy-stm32/src/adc/mod.rs
View File

@ -1,8 +1,10 @@
//! Analog to Digital (ADC) converter driver.
#![macro_use]
#[cfg(not(adc_f3_v2))]
#[cfg_attr(adc_f1, path = "f1.rs")]
#[cfg_attr(adc_f3, path = "f3.rs")]
#[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
#[cfg_attr(adc_v1, path = "v1.rs")]
#[cfg_attr(adc_v2, path = "v2.rs")]
#[cfg_attr(any(adc_v3, adc_g0), path = "v3.rs")]
@ -23,23 +25,24 @@ pub use sample_time::SampleTime;
use crate::peripherals;
/// Analog to Digital driver.
pub struct Adc<'d, T: Instance> {
#[allow(unused)]
adc: crate::PeripheralRef<'d, T>,
#[cfg(not(adc_f3_v2))]
#[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
sample_time: SampleTime,
}
pub(crate) mod sealed {
#[cfg(any(adc_f1, adc_f3, adc_v1))]
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
use embassy_sync::waitqueue::AtomicWaker;
#[cfg(any(adc_f1, adc_f3, adc_v1))]
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
pub struct State {
pub waker: AtomicWaker,
}
#[cfg(any(adc_f1, adc_f3, adc_v1))]
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
impl State {
pub const fn new() -> Self {
Self {
@ -54,11 +57,11 @@ pub(crate) mod sealed {
pub trait Instance: InterruptableInstance {
fn regs() -> crate::pac::adc::Adc;
#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_g0)))]
#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
fn common_regs() -> crate::pac::adccommon::AdcCommon;
#[cfg(adc_f3)]
fn frequency() -> crate::time::Hertz;
#[cfg(any(adc_f1, adc_f3, adc_v1))]
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
fn state() -> &'static State;
}
@ -74,12 +77,16 @@ pub(crate) mod sealed {
}
}
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0)))]
/// ADC instance.
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0))]
/// ADC instance.
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
/// ADC pin.
pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}
/// ADC internal channel.
pub trait InternalChannel<T>: sealed::InternalChannel<T> {}
foreach_adc!(
@ -89,7 +96,7 @@ foreach_adc!(
crate::pac::$inst
}
#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_g0)))]
#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
fn common_regs() -> crate::pac::adccommon::AdcCommon {
return crate::pac::$common_inst
}
@ -99,7 +106,7 @@ foreach_adc!(
unsafe { crate::rcc::get_freqs() }.$clock.unwrap()
}
#[cfg(any(adc_f1, adc_f3, adc_v1))]
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
&STATE

17
embassy-stm32/src/adc/resolution.rs
View File

@ -1,5 +1,8 @@
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
/// ADC resolution
#[allow(missing_docs)]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Resolution {
TwelveBit,
TenBit,
@ -7,8 +10,11 @@ pub enum Resolution {
SixBit,
}
/// ADC resolution
#[allow(missing_docs)]
#[cfg(adc_v4)]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Resolution {
SixteenBit,
FourteenBit,
@ -19,7 +25,7 @@ pub enum Resolution {
impl Default for Resolution {
fn default() -> Self {
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
{
Self::TwelveBit
}
@ -40,13 +46,16 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
}
}
}
impl Resolution {
/// Get the maximum reading value for this resolution.
///
/// This is `2**n - 1`.
pub fn to_max_count(&self) -> u32 {
match self {
#[cfg(adc_v4)]
@ -56,7 +65,7 @@ impl Resolution {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
Resolution::SixBit => (1 << 6) - 1,
}
}

25
embassy-stm32/src/adc/sample_time.rs
View File

@ -3,6 +3,7 @@ macro_rules! impl_sample_time {
($default_doc:expr, $default:ident, ($(($doc:expr, $variant:ident, $pac_variant:ident)),*)) => {
#[doc = concat!("ADC sample time\n\nThe default setting is ", $default_doc, " ADC clock cycles.")]
#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum SampleTime {
$(
#[doc = concat!($doc, " ADC clock cycles.")]
@ -18,6 +19,14 @@ macro_rules! impl_sample_time {
}
}
impl From<crate::pac::adc::vals::SampleTime> for SampleTime {
fn from(sample_time: crate::pac::adc::vals::SampleTime) -> SampleTime {
match sample_time {
$(crate::pac::adc::vals::SampleTime::$pac_variant => SampleTime::$variant),*
}
}
}
impl Default for SampleTime {
fn default() -> Self {
Self::$default
@ -121,3 +130,19 @@ impl_sample_time!(
("601.5", Cycles601_5, CYCLES601_5)
)
);
#[cfg(any(adc_f3_v1_1))]
impl_sample_time!(
"4",
Cycles4,
(
("4", Cycles4, CYCLES4),
("9", Cycles9, CYCLES9),
("16", Cycles16, CYCLES16),
("24", Cycles24, CYCLES24),
("48", Cycles48, CYCLES48),
("96", Cycles96, CYCLES96),
("192", Cycles192, CYCLES192),
("384", Cycles384, CYCLES384)
)
);

11
embassy-stm32/src/adc/v4.rs
View File

@ -32,6 +32,7 @@ const TEMP_CHANNEL: u8 = 18;
const VBAT_CHANNEL: u8 = 17;
// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
/// Internal voltage reference channel.
pub struct VrefInt;
impl<T: Instance> InternalChannel<T> for VrefInt {}
impl<T: Instance> super::sealed::InternalChannel<T> for VrefInt {
@ -40,6 +41,7 @@ impl<T: Instance> super::sealed::InternalChannel<T> for VrefInt {
}
}
/// Internal temperature channel.
pub struct Temperature;
impl<T: Instance> InternalChannel<T> for Temperature {}
impl<T: Instance> super::sealed::InternalChannel<T> for Temperature {
@ -48,6 +50,7 @@ impl<T: Instance> super::sealed::InternalChannel<T> for Temperature {
}
}
/// Internal battery voltage channel.
pub struct Vbat;
impl<T: Instance> InternalChannel<T> for Vbat {}
impl<T: Instance> super::sealed::InternalChannel<T> for Vbat {
@ -125,6 +128,7 @@ impl Prescaler {
}
impl<'d, T: Instance> Adc<'d, T> {
/// Create a new ADC driver.
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u16>) -> Self {
embassy_hal_internal::into_ref!(adc);
T::enable_and_reset();
@ -212,6 +216,7 @@ impl<'d, T: Instance> Adc<'d, T> {
});
}
/// Enable reading the voltage reference internal channel.
pub fn enable_vrefint(&self) -> VrefInt {
T::common_regs().ccr().modify(|reg| {
reg.set_vrefen(true);
@ -220,6 +225,7 @@ impl<'d, T: Instance> Adc<'d, T> {
VrefInt {}
}
/// Enable reading the temperature internal channel.
pub fn enable_temperature(&self) -> Temperature {
T::common_regs().ccr().modify(|reg| {
reg.set_vsenseen(true);
@ -228,6 +234,7 @@ impl<'d, T: Instance> Adc<'d, T> {
Temperature {}
}
/// Enable reading the vbat internal channel.
pub fn enable_vbat(&self) -> Vbat {
T::common_regs().ccr().modify(|reg| {
reg.set_vbaten(true);
@ -236,10 +243,12 @@ impl<'d, T: Instance> Adc<'d, T> {
Vbat {}
}
/// Set the ADC sample time.
pub fn set_sample_time(&mut self, sample_time: SampleTime) {
self.sample_time = sample_time;
}
/// Set the ADC resolution.
pub fn set_resolution(&mut self, resolution: Resolution) {
T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
}
@ -263,6 +272,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().dr().read().0 as u16
}
/// Read an ADC pin.
pub fn read<P>(&mut self, pin: &mut P) -> u16
where
P: AdcPin<T>,
@ -273,6 +283,7 @@ impl<'d, T: Instance> Adc<'d, T> {
self.read_channel(pin.channel())
}
/// Read an ADC internal channel.
pub fn read_internal(&mut self, channel: &mut impl InternalChannel<T>) -> u16 {
self.read_channel(channel.channel())
}

15
embassy-stm32/src/can/fdcan.rs
View File

@ -1,6 +1,3 @@
pub use bxcan;
use embassy_hal_internal::PeripheralRef;
use crate::peripherals;
pub(crate) mod sealed {
@ -25,27 +22,19 @@ pub(crate) mod sealed {
}
pub trait Instance {
const REGISTERS: *mut bxcan::RegisterBlock;
fn regs() -> &'static crate::pac::can::Fdcan;
fn state() -> &'static State;
}
}
/// Interruptable FDCAN instance.
pub trait InterruptableInstance {}
/// FDCAN instance.
pub trait Instance: sealed::Instance + InterruptableInstance + 'static {}
pub struct BxcanInstance<'a, T>(PeripheralRef<'a, T>);
unsafe impl<'d, T: Instance> bxcan::Instance for BxcanInstance<'d, T> {
const REGISTERS: *mut bxcan::RegisterBlock = T::REGISTERS;
}
foreach_peripheral!(
(can, $inst:ident) => {
impl sealed::Instance for peripherals::$inst {
const REGISTERS: *mut bxcan::RegisterBlock = crate::pac::$inst.as_ptr() as *mut _;
fn regs() -> &'static crate::pac::can::Fdcan {
&crate::pac::$inst
}

2
embassy-stm32/src/can/mod.rs
View File

@ -1,6 +1,6 @@
#![macro_use]
#[cfg_attr(can_bxcan, path = "bxcan.rs")]
#[cfg_attr(can_fdcan, path = "fdcan.rs")]
#[cfg_attr(any(can_fdcan_v1, can_fdcan_h7), path = "fdcan.rs")]
mod _version;
pub use _version::*;

13
embassy-stm32/src/crc/v2v3.rs
View File

@ -6,15 +6,19 @@ use crate::peripherals::CRC;
use crate::rcc::sealed::RccPeripheral;
use crate::Peripheral;
/// CRC driver.
pub struct Crc<'d> {
_peripheral: PeripheralRef<'d, CRC>,
_config: Config,
}
/// CRC configuration errlr
pub enum ConfigError {
/// The selected polynomial is invalid.
InvalidPolynomial,
}
/// CRC configuration
pub struct Config {
reverse_in: InputReverseConfig,
reverse_out: bool,
@ -25,14 +29,20 @@ pub struct Config {
crc_poly: u32,
}
/// Input reverse configuration.
pub enum InputReverseConfig {
/// Don't reverse anything
None,
/// Reverse bytes
Byte,
/// Reverse 16-bit halfwords.
Halfword,
/// Reverse 32-bit words.
Word,
}
impl Config {
/// Create a new CRC config.
pub fn new(
reverse_in: InputReverseConfig,
reverse_out: bool,
@ -57,7 +67,9 @@ impl Config {
}
}
/// Polynomial size
#[cfg(crc_v3)]
#[allow(missing_docs)]
pub enum PolySize {
Width7,
Width8,
@ -81,6 +93,7 @@ impl<'d> Crc<'d> {
instance
}
/// Reset the CRC engine.
pub fn reset(&mut self) {
PAC_CRC.cr().modify(|w| w.set_reset(true));
}

21
embassy-stm32/src/dac/mod.rs
View File

@ -62,11 +62,11 @@ impl Mode {
///
/// 12-bit values outside the permitted range are silently truncated.
pub enum Value {
// 8 bit value
/// 8 bit value
Bit8(u8),
// 12 bit value stored in a u16, left-aligned
/// 12 bit value stored in a u16, left-aligned
Bit12Left(u16),
// 12 bit value stored in a u16, right-aligned
/// 12 bit value stored in a u16, right-aligned
Bit12Right(u16),
}
@ -76,11 +76,11 @@ pub enum Value {
///
/// 12-bit values outside the permitted range are silently truncated.
pub enum DualValue {
// 8 bit value
/// 8 bit value
Bit8(u8, u8),
// 12 bit value stored in a u16, left-aligned
/// 12 bit value stored in a u16, left-aligned
Bit12Left(u16, u16),
// 12 bit value stored in a u16, right-aligned
/// 12 bit value stored in a u16, right-aligned
Bit12Right(u16, u16),
}
@ -88,11 +88,11 @@ pub enum DualValue {
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
/// Array variant of [`Value`].
pub enum ValueArray<'a> {
// 8 bit values
/// 8 bit values
Bit8(&'a [u8]),
// 12 bit value stored in a u16, left-aligned
/// 12 bit value stored in a u16, left-aligned
Bit12Left(&'a [u16]),
// 12 bit values stored in a u16, right-aligned
/// 12 bit values stored in a u16, right-aligned
Bit12Right(&'a [u16]),
}
@ -106,7 +106,9 @@ pub struct DacChannel<'d, T: Instance, const N: u8, DMA = NoDma> {
dma: PeripheralRef<'d, DMA>,
}
/// DAC channel 1 type alias.
pub type DacCh1<'d, T, DMA = NoDma> = DacChannel<'d, T, 1, DMA>;
/// DAC channel 2 type alias.
pub type DacCh2<'d, T, DMA = NoDma> = DacChannel<'d, T, 2, DMA>;
impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
@ -492,6 +494,7 @@ pub(crate) mod sealed {
}
}
/// DAC instance.
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
dma_trait!(DacDma1, Instance);
dma_trait!(DacDma2, Instance);

2
embassy-stm32/src/dac/tsel.rs
View File

@ -1,3 +1,5 @@
#![allow(missing_docs)]
/// Trigger selection for STM32F0.
#[cfg(stm32f0)]
#[derive(Debug, Copy, Clone, Eq, PartialEq)]

24
embassy-stm32/src/dcmi.rs
View File

@ -36,6 +36,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
}
/// The level on the VSync pin when the data is not valid on the parallel interface.
#[allow(missing_docs)]
#[derive(Clone, Copy, PartialEq)]
pub enum VSyncDataInvalidLevel {
Low,
@ -43,6 +44,7 @@ pub enum VSyncDataInvalidLevel {
}
/// The level on the VSync pin when the data is not valid on the parallel interface.
#[allow(missing_docs)]
#[derive(Clone, Copy, PartialEq)]
pub enum HSyncDataInvalidLevel {
Low,
@ -50,14 +52,16 @@ pub enum HSyncDataInvalidLevel {
}
#[derive(Clone, Copy, PartialEq)]
#[allow(missing_docs)]
pub enum PixelClockPolarity {
RisingEdge,
FallingEdge,
}
pub struct State {
struct State {
waker: AtomicWaker,
}
impl State {
const fn new() -> State {
State {
@ -68,18 +72,25 @@ impl State {
static STATE: State = State::new();
/// DCMI error.
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub enum Error {
/// Overrun error: the hardware generated data faster than we could read it.
Overrun,
/// Internal peripheral error.
PeripheralError,
}
/// DCMI configuration.
#[non_exhaustive]
pub struct Config {
/// VSYNC level.
pub vsync_level: VSyncDataInvalidLevel,
/// HSYNC level.
pub hsync_level: HSyncDataInvalidLevel,
/// PIXCLK polarity.
pub pixclk_polarity: PixelClockPolarity,
}
@ -105,6 +116,7 @@ macro_rules! config_pins {
};
}
/// DCMI driver.
pub struct Dcmi<'d, T: Instance, Dma: FrameDma<T>> {
inner: PeripheralRef<'d, T>,
dma: PeripheralRef<'d, Dma>,
@ -115,6 +127,7 @@ where
T: Instance,
Dma: FrameDma<T>,
{
/// Create a new DCMI driver with 8 data bits.
pub fn new_8bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -139,6 +152,7 @@ where
Self::new_inner(peri, dma, config, false, 0b00)
}
/// Create a new DCMI driver with 10 data bits.
pub fn new_10bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -165,6 +179,7 @@ where
Self::new_inner(peri, dma, config, false, 0b01)
}
/// Create a new DCMI driver with 12 data bits.
pub fn new_12bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -193,6 +208,7 @@ where
Self::new_inner(peri, dma, config, false, 0b10)
}
/// Create a new DCMI driver with 14 data bits.
pub fn new_14bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -223,6 +239,7 @@ where
Self::new_inner(peri, dma, config, false, 0b11)
}
/// Create a new DCMI driver with 8 data bits, with embedded synchronization.
pub fn new_es_8bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -245,6 +262,7 @@ where
Self::new_inner(peri, dma, config, true, 0b00)
}
/// Create a new DCMI driver with 10 data bits, with embedded synchronization.
pub fn new_es_10bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -269,6 +287,7 @@ where
Self::new_inner(peri, dma, config, true, 0b01)
}
/// Create a new DCMI driver with 12 data bits, with embedded synchronization.
pub fn new_es_12bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -295,6 +314,7 @@ where
Self::new_inner(peri, dma, config, true, 0b10)
}
/// Create a new DCMI driver with 14 data bits, with embedded synchronization.
pub fn new_es_14bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
@ -538,7 +558,9 @@ mod sealed {
}
}
/// DCMI instance.
pub trait Instance: sealed::Instance + 'static {
/// Interrupt for this instance.
type Interrupt: interrupt::typelevel::Interrupt;
}

62
embassy-stm32/src/dma/bdma.rs
View File

@ -1,4 +1,4 @@
#![macro_use]
//! Basic Direct Memory Acccess (BDMA)
use core::future::Future;
use core::pin::Pin;
@ -17,6 +17,7 @@ use crate::interrupt::Priority;
use crate::pac;
use crate::pac::bdma::{regs, vals};
/// BDMA transfer options.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
@ -140,13 +141,17 @@ pub(crate) unsafe fn on_irq_inner(dma: pac::bdma::Dma, channel_num: usize, index
STATE.ch_wakers[index].wake();
}
/// DMA request type alias.
#[cfg(any(bdma_v2, dmamux))]
pub type Request = u8;
/// DMA request type alias.
#[cfg(not(any(bdma_v2, dmamux)))]
pub type Request = ();
/// DMA channel.
#[cfg(dmamux)]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
/// DMA channel.
#[cfg(not(dmamux))]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
@ -161,12 +166,14 @@ pub(crate) mod sealed {
}
}
/// DMA transfer.
#[must_use = "futures do nothing unless you `.await` or poll them"]
pub struct Transfer<'a, C: Channel> {
channel: PeripheralRef<'a, C>,
}
impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new read DMA transfer (peripheral to memory).
pub unsafe fn new_read<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -177,6 +184,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
Self::new_read_raw(channel, request, peri_addr, buf, options)
}
/// Create a new read DMA transfer (peripheral to memory), using raw pointers.
pub unsafe fn new_read_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -202,6 +210,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
)
}
/// Create a new write DMA transfer (memory to peripheral).
pub unsafe fn new_write<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -212,6 +221,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
Self::new_write_raw(channel, request, buf, peri_addr, options)
}
/// Create a new write DMA transfer (memory to peripheral), using raw pointers.
pub unsafe fn new_write_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -237,6 +247,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
)
}
/// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
pub unsafe fn new_write_repeated<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -321,6 +332,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
}
/// Request the transfer to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
@ -331,6 +345,10 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
}
/// Return whether this transfer is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
let en = ch.cr().read().en();
@ -339,13 +357,15 @@ impl<'a, C: Channel> Transfer<'a, C> {
en && (circular || !tcif)
}
/// Gets the total remaining transfers for the channel
/// Note: this will be zero for transfers that completed without cancellation.
/// Get the total remaining transfers for the channel.
///
/// This will be zero for transfers that completed instead of being canceled with [`request_stop`](Self::request_stop).
pub fn get_remaining_transfers(&self) -> u16 {
let ch = self.channel.regs().ch(self.channel.num());
ch.ndtr().read().ndt()
}
/// Blocking wait until the transfer finishes.
pub fn blocking_wait(mut self) {
while self.is_running() {}
self.request_stop();
@ -411,6 +431,7 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
}
}
/// Ringbuffer for reading data using DMA circular mode.
pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
cr: regs::Cr,
channel: PeripheralRef<'a, C>,
@ -418,7 +439,8 @@ pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
}
impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
pub unsafe fn new_read(
/// Create a new ring buffer.
pub unsafe fn new(
channel: impl Peripheral<P = C> + 'a,
_request: Request,
peri_addr: *mut W,
@ -473,11 +495,15 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
this
}
/// Start the ring buffer operation.
///
/// You must call this after creating it for it to work.
pub fn start(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
ch.cr().write_value(self.cr)
}
/// Clear all data in the ring buffer.
pub fn clear(&mut self) {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
@ -509,10 +535,11 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
}
/// The capacity of the ringbuffer.
pub const fn cap(&self) -> usize {
pub const fn capacity(&self) -> usize {
self.ringbuf.cap()
}
/// Set a waker to be woken when at least one byte is received.
pub fn set_waker(&mut self, waker: &Waker) {
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
}
@ -526,6 +553,9 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
});
}
/// Request DMA to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
@ -539,6 +569,10 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
});
}
/// Return whether DMA is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
ch.cr().read().en()
@ -555,6 +589,7 @@ impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
}
}
/// Ringbuffer for writing data using DMA circular mode.
pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
cr: regs::Cr,
channel: PeripheralRef<'a, C>,
@ -562,7 +597,8 @@ pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
}
impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
pub unsafe fn new_write(
/// Create a new ring buffer.
pub unsafe fn new(
channel: impl Peripheral<P = C> + 'a,
_request: Request,
peri_addr: *mut W,
@ -617,11 +653,15 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
this
}
/// Start the ring buffer operation.
///
/// You must call this after creating it for it to work.
pub fn start(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
ch.cr().write_value(self.cr)
}
/// Clear all data in the ring buffer.
pub fn clear(&mut self) {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
@ -640,10 +680,11 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
}
/// The capacity of the ringbuffer.
pub const fn cap(&self) -> usize {
pub const fn capacity(&self) -> usize {
self.ringbuf.cap()
}
/// Set a waker to be woken when at least one byte is sent.
pub fn set_waker(&mut self, waker: &Waker) {
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
}
@ -657,6 +698,9 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
});
}
/// Request DMA to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
@ -670,6 +714,10 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
});
}
/// Return whether DMA is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
ch.cr().read().en()

79
embassy-stm32/src/dma/dma.rs
View File

@ -16,6 +16,7 @@ use crate::interrupt::Priority;
use crate::pac::dma::{regs, vals};
use crate::{interrupt, pac};
/// DMA transfer options.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
@ -69,6 +70,7 @@ impl From<Dir> for vals::Dir {
}
}
/// DMA transfer burst setting.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Burst {
@ -93,6 +95,7 @@ impl From<Burst> for vals::Burst {
}
}
/// DMA flow control setting.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FlowControl {
@ -111,6 +114,7 @@ impl From<FlowControl> for vals::Pfctrl {
}
}
/// DMA FIFO threshold.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FifoThreshold {
@ -208,13 +212,17 @@ pub(crate) unsafe fn on_irq_inner(dma: pac::dma::Dma, channel_num: usize, index:
STATE.ch_wakers[index].wake();
}
/// DMA request type alias. (also known as DMA channel number in some chips)
#[cfg(any(dma_v2, dmamux))]
pub type Request = u8;
/// DMA request type alias. (also known as DMA channel number in some chips)
#[cfg(not(any(dma_v2, dmamux)))]
pub type Request = ();
/// DMA channel.
#[cfg(dmamux)]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
/// DMA channel.
#[cfg(not(dmamux))]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
@ -229,12 +237,14 @@ pub(crate) mod sealed {
}
}
/// DMA transfer.
#[must_use = "futures do nothing unless you `.await` or poll them"]
pub struct Transfer<'a, C: Channel> {
channel: PeripheralRef<'a, C>,
}
impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new read DMA transfer (peripheral to memory).
pub unsafe fn new_read<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -245,6 +255,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
Self::new_read_raw(channel, request, peri_addr, buf, options)
}
/// Create a new read DMA transfer (peripheral to memory), using raw pointers.
pub unsafe fn new_read_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -270,6 +281,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
)
}
/// Create a new write DMA transfer (memory to peripheral).
pub unsafe fn new_write<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -280,6 +292,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
Self::new_write_raw(channel, request, buf, peri_addr, options)
}
/// Create a new write DMA transfer (memory to peripheral), using raw pointers.
pub unsafe fn new_write_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -305,6 +318,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
)
}
/// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
pub unsafe fn new_write_repeated<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
@ -407,6 +421,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
}
/// Request the transfer to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
@ -417,6 +434,10 @@ impl<'a, C: Channel> Transfer<'a, C> {
});
}
/// Return whether this transfer is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().read().en()
@ -429,6 +450,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
ch.ndtr().read().ndt()
}
/// Blocking wait until the transfer finishes.
pub fn blocking_wait(mut self) {
while self.is_running() {}
@ -465,12 +487,14 @@ impl<'a, C: Channel> Future for Transfer<'a, C> {
// ==================================
/// Double-buffered DMA transfer.
pub struct DoubleBuffered<'a, C: Channel, W: Word> {
channel: PeripheralRef<'a, C>,
_phantom: PhantomData<W>,
}
impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
/// Create a new read DMA transfer (peripheral to memory).
pub unsafe fn new_read(
channel: impl Peripheral<P = C> + 'a,
_request: Request,
@ -554,25 +578,36 @@ impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
});
}
/// Set the first buffer address.
///
/// You may call this while DMA is transferring the other buffer.
pub unsafe fn set_buffer0(&mut self, buffer: *mut W) {
let ch = self.channel.regs().st(self.channel.num());
ch.m0ar().write_value(buffer as _);
}
/// Set the second buffer address.
///
/// You may call this while DMA is transferring the other buffer.
pub unsafe fn set_buffer1(&mut self, buffer: *mut W) {
let ch = self.channel.regs().st(self.channel.num());
ch.m1ar().write_value(buffer as _);
}
/// Returh whether buffer0 is accessible (i.e. whether DMA is transferring buffer1 now)
pub fn is_buffer0_accessible(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().read().ct() == vals::Ct::MEMORY1
}
/// Set a waker to be woken when one of the buffers is being transferred.
pub fn set_waker(&mut self, waker: &Waker) {
STATE.ch_wakers[self.channel.index()].register(waker);
}
/// Request the transfer to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
@ -583,6 +618,10 @@ impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
});
}
/// Return whether this transfer is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().read().en()
@ -629,6 +668,7 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
}
}
/// Ringbuffer for receiving data using DMA circular mode.
pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
cr: regs::Cr,
channel: PeripheralRef<'a, C>,
@ -636,7 +676,8 @@ pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
}
impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
pub unsafe fn new_read(
/// Create a new ring buffer.
pub unsafe fn new(
channel: impl Peripheral<P = C> + 'a,
_request: Request,
peri_addr: *mut W,
@ -706,11 +747,15 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
this
}
/// Start the ring buffer operation.
///
/// You must call this after creating it for it to work.
pub fn start(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().write_value(self.cr);
}
/// Clear all data in the ring buffer.
pub fn clear(&mut self) {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
@ -741,11 +786,12 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
.await
}
// The capacity of the ringbuffer
pub const fn cap(&self) -> usize {
/// The capacity of the ringbuffer
pub const fn capacity(&self) -> usize {
self.ringbuf.cap()
}
/// Set a waker to be woken when at least one byte is received.
pub fn set_waker(&mut self, waker: &Waker) {
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
}
@ -763,6 +809,9 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
});
}
/// Request DMA to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
@ -774,6 +823,10 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
});
}
/// Return whether DMA is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().read().en()
@ -790,6 +843,7 @@ impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
}
}
/// Ringbuffer for writing data using DMA circular mode.
pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
cr: regs::Cr,
channel: PeripheralRef<'a, C>,
@ -797,7 +851,8 @@ pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
}
impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
pub unsafe fn new_write(
/// Create a new ring buffer.
pub unsafe fn new(
channel: impl Peripheral<P = C> + 'a,
_request: Request,
peri_addr: *mut W,
@ -867,11 +922,15 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
this
}
/// Start the ring buffer operation.
///
/// You must call this after creating it for it to work.
pub fn start(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().write_value(self.cr);
}
/// Clear all data in the ring buffer.
pub fn clear(&mut self) {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
@ -901,11 +960,12 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
.await
}
// The capacity of the ringbuffer
pub const fn cap(&self) -> usize {
/// The capacity of the ringbuffer
pub const fn capacity(&self) -> usize {
self.ringbuf.cap()
}
/// Set a waker to be woken when at least one byte is received.
pub fn set_waker(&mut self, waker: &Waker) {
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
}
@ -923,6 +983,9 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
});
}
/// Request DMA to stop.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
let ch = self.channel.regs().st(self.channel.num());
@ -934,6 +997,10 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
});
}
/// Return whether DMA is still running.
///
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().st(self.channel.num());
ch.cr().read().en()

4
embassy-stm32/src/dma/dmamux.rs
View File

@ -22,11 +22,15 @@ pub(crate) mod dmamux_sealed {
}
}
/// DMAMUX1 instance.
pub struct DMAMUX1;
/// DMAMUX2 instance.
#[cfg(stm32h7)]
pub struct DMAMUX2;
/// DMAMUX channel trait.
pub trait MuxChannel: dmamux_sealed::MuxChannel {
/// DMAMUX instance this channel is on.
type Mux;
}

7
embassy-stm32/src/dma/mod.rs
View File

@ -39,6 +39,13 @@ enum Dir {
PeripheralToMemory,
}
/// "No DMA" placeholder.
///
/// You may pass this in place of a real DMA channel when creating a driver
/// to indicate it should not use DMA.
///
/// This often causes async functionality to not be available on the instance,
/// leaving only blocking functionality.
pub struct NoDma;
impl_peripheral!(NoDma);

10
embassy-stm32/src/dma/word.rs
View File

@ -1,3 +1,6 @@
//! DMA word sizes.
#[allow(missing_docs)]
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum WordSize {
@ -7,6 +10,7 @@ pub enum WordSize {
}
impl WordSize {
/// Amount of bytes of this word size.
pub fn bytes(&self) -> usize {
match self {
Self::OneByte => 1,
@ -20,8 +24,13 @@ mod sealed {
pub trait Word {}
}
/// DMA word trait.
///
/// This is implemented for u8, u16, u32, etc.
pub trait Word: sealed::Word + Default + Copy + 'static {
/// Word size
fn size() -> WordSize;
/// Amount of bits of this word size.
fn bits() -> usize;
}
@ -40,6 +49,7 @@ macro_rules! impl_word {
($T:ident, $uX:ident, $bits:literal, $size:ident) => {
#[repr(transparent)]
#[derive(Copy, Clone, Default)]
#[doc = concat!(stringify!($T), " word size")]
pub struct $T(pub $uX);
impl_word!(_, $T, $bits, $size);
};

1
embassy-stm32/src/eth/generic_smi.rs
View File

@ -102,6 +102,7 @@ unsafe impl PHY for GenericSMI {
/// Public functions for the PHY
impl GenericSMI {
/// Set the SMI polling interval.
#[cfg(feature = "time")]
pub fn set_poll_interval(&mut self, poll_interval: Duration) {
self.poll_interval = poll_interval

25
embassy-stm32/src/eth/mod.rs
View File

@ -22,6 +22,14 @@ const RX_BUFFER_SIZE: usize = 1536;
#[derive(Copy, Clone)]
pub(crate) struct Packet<const N: usize>([u8; N]);
/// Ethernet packet queue.
///
/// This struct owns the memory used for reading and writing packets.
///
/// `TX` is the number of packets in the transmit queue, `RX` in the receive
/// queue. A bigger queue allows the hardware to receive more packets while the
/// CPU is busy doing other things, which may increase performance (especially for RX)
/// at the cost of more RAM usage.
pub struct PacketQueue<const TX: usize, const RX: usize> {
tx_desc: [TDes; TX],
rx_desc: [RDes; RX],
@ -30,6 +38,7 @@ pub struct PacketQueue<const TX: usize, const RX: usize> {
}
impl<const TX: usize, const RX: usize> PacketQueue<TX, RX> {
/// Create a new packet queue.
pub const fn new() -> Self {
const NEW_TDES: TDes = TDes::new();
const NEW_RDES: RDes = RDes::new();
@ -41,7 +50,18 @@ impl<const TX: usize, const RX: usize> PacketQueue<TX, RX> {
}
}
// Allow to initialize a Self without requiring it to go on the stack
/// Initialize a packet queue in-place.
///
/// This can be helpful to avoid accidentally stack-allocating the packet queue in the stack. The
/// Rust compiler can sometimes be a bit dumb when working with large owned values: if you call `new()`
/// and then store the returned PacketQueue in its final place (like a `static`), the compiler might
/// place it temporarily on the stack then move it. Since this struct is quite big, it may result
/// in a stack overflow.
///
/// With this function, you can create an uninitialized `static` with type `MaybeUninit<PacketQueue<...>>`
/// and initialize it in-place, guaranteeing no stack usage.
///
/// After calling this function, calling `assume_init` on the MaybeUninit is guaranteed safe.
pub fn init(this: &mut MaybeUninit<Self>) {
unsafe {
this.as_mut_ptr().write_bytes(0u8, 1);
@ -93,6 +113,7 @@ impl<'d, T: Instance, P: PHY> embassy_net_driver::Driver for Ethernet<'d, T, P>
}
}
/// `embassy-net` RX token.
pub struct RxToken<'a, 'd> {
rx: &'a mut RDesRing<'d>,
}
@ -110,6 +131,7 @@ impl<'a, 'd> embassy_net_driver::RxToken for RxToken<'a, 'd> {
}
}
/// `embassy-net` TX token.
pub struct TxToken<'a, 'd> {
tx: &'a mut TDesRing<'d>,
}
@ -159,6 +181,7 @@ pub(crate) mod sealed {
}
}
/// Ethernet instance.
pub trait Instance: sealed::Instance + Send + 'static {}
impl sealed::Instance for crate::peripherals::ETH {

3
embassy-stm32/src/eth/v2/mod.rs
View File

@ -34,6 +34,7 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandl
}
}
/// Ethernet driver.
pub struct Ethernet<'d, T: Instance, P: PHY> {
_peri: PeripheralRef<'d, T>,
pub(crate) tx: TDesRing<'d>,
@ -56,6 +57,7 @@ macro_rules! config_pins {
}
impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
/// Create a new Ethernet driver.
pub fn new<const TX: usize, const RX: usize>(
queue: &'d mut PacketQueue<TX, RX>,
peri: impl Peripheral<P = T> + 'd,
@ -237,6 +239,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
}
}
/// Ethernet SMI driver.
pub struct EthernetStationManagement<T: Instance> {
peri: PhantomData<T>,
clock_range: u8,

145
embassy-stm32/src/exti.rs
View File

@ -1,3 +1,4 @@
use core::convert::Infallible;
use core::future::Future;
use core::marker::PhantomData;
use core::pin::Pin;
@ -38,7 +39,7 @@ fn exticr_regs() -> pac::afio::Afio {
pac::AFIO
}
pub unsafe fn on_irq() {
unsafe fn on_irq() {
#[cfg(feature = "low-power")]
crate::low_power::on_wakeup_irq();
@ -84,7 +85,13 @@ impl Iterator for BitIter {
}
}
/// EXTI input driver
/// EXTI input driver.
///
/// This driver augments a GPIO `Input` with EXTI functionality. EXTI is not
/// built into `Input` itself because it needs to take ownership of the corresponding
/// EXTI channel, which is a limited resource.
///
/// Pins PA5, PB5, PC5... all use EXTI channel 5, so you can't use EXTI on, say, PA5 and PC5 at the same time.
pub struct ExtiInput<'d, T: GpioPin> {
pin: Input<'d, T>,
}
@ -92,23 +99,30 @@ pub struct ExtiInput<'d, T: GpioPin> {
impl<'d, T: GpioPin> Unpin for ExtiInput<'d, T> {}
impl<'d, T: GpioPin> ExtiInput<'d, T> {
/// Create an EXTI input.
pub fn new(pin: Input<'d, T>, _ch: impl Peripheral<P = T::ExtiChannel> + 'd) -> Self {
Self { pin }
}
pub fn is_high(&self) -> bool {
/// Get whether the pin is high.
pub fn is_high(&mut self) -> bool {
self.pin.is_high()
}
pub fn is_low(&self) -> bool {
/// Get whether the pin is low.
pub fn is_low(&mut self) -> bool {
self.pin.is_low()
}
pub fn get_level(&self) -> Level {
/// Get the pin level.
pub fn get_level(&mut self) -> Level {
self.pin.get_level()
}
pub async fn wait_for_high<'a>(&'a mut self) {
/// Asynchronously wait until the pin is high.
///
/// This returns immediately if the pin is already high.
pub async fn wait_for_high(&mut self) {
let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false);
if self.is_high() {
return;
@ -116,7 +130,10 @@ impl<'d, T: GpioPin> ExtiInput<'d, T> {
fut.await
}
pub async fn wait_for_low<'a>(&'a mut self) {
/// Asynchronously wait until the pin is low.
///
/// This returns immediately if the pin is already low.
pub async fn wait_for_low(&mut self) {
let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true);
if self.is_low() {
return;
@ -124,87 +141,76 @@ impl<'d, T: GpioPin> ExtiInput<'d, T> {
fut.await
}
pub async fn wait_for_rising_edge<'a>(&'a mut self) {
/// Asynchronously wait until the pin sees a rising edge.
///
/// If the pin is already high, it will wait for it to go low then back high.
pub async fn wait_for_rising_edge(&mut self) {
ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false).await
}
pub async fn wait_for_falling_edge<'a>(&'a mut self) {
/// Asynchronously wait until the pin sees a falling edge.
///
/// If the pin is already low, it will wait for it to go high then back low.
pub async fn wait_for_falling_edge(&mut self) {
ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true).await
}
pub async fn wait_for_any_edge<'a>(&'a mut self) {
/// Asynchronously wait until the pin sees any edge (either rising or falling).
pub async fn wait_for_any_edge(&mut self) {
ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true).await
}
}
mod eh02 {
use core::convert::Infallible;
impl<'d, T: GpioPin> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d, T> {
type Error = Infallible;
use super::*;
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(!self.pin.pin.ref_is_low())
}
impl<'d, T: GpioPin> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d, T> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.pin.pin.ref_is_low())
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use core::convert::Infallible;
impl<'d, T: GpioPin> embedded_hal_1::digital::ErrorType for ExtiInput<'d, T> {
type Error = Infallible;
}
use super::*;
impl<'d, T: GpioPin> embedded_hal_1::digital::ErrorType for ExtiInput<'d, T> {
type Error = Infallible;
impl<'d, T: GpioPin> embedded_hal_1::digital::InputPin for ExtiInput<'d, T> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
impl<'d, T: GpioPin> embedded_hal_1::digital::InputPin for ExtiInput<'d, T> {
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
mod eha {
use super::*;
impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for ExtiInput<'d, T> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
}
impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for ExtiInput<'d, T> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
}
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
self.wait_for_low().await;
Ok(())
}
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
self.wait_for_low().await;
Ok(())
}
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_rising_edge().await;
Ok(())
}
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_rising_edge().await;
Ok(())
}
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_falling_edge().await;
Ok(())
}
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_falling_edge().await;
Ok(())
}
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_any_edge().await;
Ok(())
}
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_any_edge().await;
Ok(())
}
}
@ -301,6 +307,7 @@ macro_rules! foreach_exti_irq {
macro_rules! impl_irq {
($e:ident) => {
#[allow(non_snake_case)]
#[cfg(feature = "rt")]
#[interrupt]
unsafe fn $e() {
@ -315,8 +322,16 @@ pub(crate) mod sealed {
pub trait Channel {}
}
/// EXTI channel trait.
pub trait Channel: sealed::Channel + Sized {
/// Get the EXTI channel number.
fn number(&self) -> usize;
/// Type-erase (degrade) this channel into an `AnyChannel`.
///
/// This converts EXTI channel singletons (`EXTI0`, `EXTI1`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of channels, or avoiding generics.
fn degrade(self) -> AnyChannel {
AnyChannel {
number: self.number() as u8,
@ -324,9 +339,13 @@ pub trait Channel: sealed::Channel + Sized {
}
}
/// Type-erased (degraded) EXTI channel.
///
/// This represents ownership over any EXTI channel, known at runtime.
pub struct AnyChannel {
number: u8,
}
impl_peripheral!(AnyChannel);
impl sealed::Channel for AnyChannel {}
impl Channel for AnyChannel {

10
embassy-stm32/src/flash/asynch.rs
View File

@ -55,12 +55,11 @@ impl interrupt::typelevel::Handler<crate::interrupt::typelevel::FLASH> for Inter
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::ReadNorFlash for Flash<'_, Async> {
const READ_SIZE: usize = super::READ_SIZE;
async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
self.read(offset, bytes)
self.blocking_read(offset, bytes)
}
fn capacity(&self) -> usize {
@ -68,7 +67,6 @@ impl embedded_storage_async::nor_flash::ReadNorFlash for Flash<'_, Async> {
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::NorFlash for Flash<'_, Async> {
const WRITE_SIZE: usize = WRITE_SIZE;
const ERASE_SIZE: usize = super::MAX_ERASE_SIZE;
@ -158,8 +156,7 @@ foreach_flash_region! {
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::ReadNorFlash for crate::_generated::flash_regions::$type_name<'_, Async> {
impl embedded_storage_async::nor_flash::ReadNorFlash for crate::_generated::flash_regions::$type_name<'_, Async> {
const READ_SIZE: usize = super::READ_SIZE;
async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
@ -171,8 +168,7 @@ foreach_flash_region! {
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::NorFlash for crate::_generated::flash_regions::$type_name<'_, Async> {
impl embedded_storage_async::nor_flash::NorFlash for crate::_generated::flash_regions::$type_name<'_, Async> {
const WRITE_SIZE: usize = $write_size;
const ERASE_SIZE: usize = $erase_size;

33
embassy-stm32/src/flash/common.rs
View File

@ -12,12 +12,14 @@ use super::{
use crate::peripherals::FLASH;
use crate::Peripheral;
/// Internal flash memory driver.
pub struct Flash<'d, MODE = Async> {
pub(crate) inner: PeripheralRef<'d, FLASH>,
pub(crate) _mode: PhantomData<MODE>,
}
impl<'d> Flash<'d, Blocking> {
/// Create a new flash driver, usable in blocking mode.
pub fn new_blocking(p: impl Peripheral<P = FLASH> + 'd) -> Self {
into_ref!(p);
@ -29,15 +31,26 @@ impl<'d> Flash<'d, Blocking> {
}
impl<'d, MODE> Flash<'d, MODE> {
/// Split this flash driver into one instance per flash memory region.
///
/// See module-level documentation for details on how memory regions work.
pub fn into_blocking_regions(self) -> FlashLayout<'d, Blocking> {
assert!(family::is_default_layout());
FlashLayout::new(self.inner)
}
pub fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
/// Blocking read.
///
/// NOTE: `offset` is an offset from the flash start, NOT an absolute address.
/// For example, to read address `0x0800_1234` you have to use offset `0x1234`.
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
blocking_read(FLASH_BASE as u32, FLASH_SIZE as u32, offset, bytes)
}
/// Blocking write.
///
/// NOTE: `offset` is an offset from the flash start, NOT an absolute address.
/// For example, to write address `0x0800_1234` you have to use offset `0x1234`.
pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
unsafe {
blocking_write(
@ -50,6 +63,10 @@ impl<'d, MODE> Flash<'d, MODE> {
}
}
/// Blocking erase.
///
/// NOTE: `from` and `to` are offsets from the flash start, NOT an absolute address.
/// For example, to erase address `0x0801_0000` you have to use offset `0x1_0000`.
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
unsafe { blocking_erase(FLASH_BASE as u32, from, to, erase_sector_unlocked) }
}
@ -206,7 +223,7 @@ impl<MODE> embedded_storage::nor_flash::ReadNorFlash for Flash<'_, MODE> {
const READ_SIZE: usize = READ_SIZE;
fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
self.read(offset, bytes)
self.blocking_read(offset, bytes)
}
fn capacity(&self) -> usize {
@ -230,16 +247,28 @@ impl<MODE> embedded_storage::nor_flash::NorFlash for Flash<'_, MODE> {
foreach_flash_region! {
($type_name:ident, $write_size:literal, $erase_size:literal) => {
impl<MODE> crate::_generated::flash_regions::$type_name<'_, MODE> {
/// Blocking read.
///
/// NOTE: `offset` is an offset from the flash start, NOT an absolute address.
/// For example, to read address `0x0800_1234` you have to use offset `0x1234`.
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
blocking_read(self.0.base, self.0.size, offset, bytes)
}
}
impl crate::_generated::flash_regions::$type_name<'_, Blocking> {
/// Blocking write.
///
/// NOTE: `offset` is an offset from the flash start, NOT an absolute address.
/// For example, to write address `0x0800_1234` you have to use offset `0x1234`.
pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
unsafe { blocking_write(self.0.base, self.0.size, offset, bytes, write_chunk_with_critical_section) }
}
/// Blocking erase.
///
/// NOTE: `from` and `to` are offsets from the flash start, NOT an absolute address.
/// For example, to erase address `0x0801_0000` you have to use offset `0x1_0000`.
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
unsafe { blocking_erase(self.0.base, from, to, erase_sector_with_critical_section) }
}

6
embassy-stm32/src/flash/f0.rs
View File

@ -6,11 +6,11 @@ use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -79,7 +79,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

6
embassy-stm32/src/flash/f3.rs
View File

@ -6,11 +6,11 @@ use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -79,7 +79,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

4
embassy-stm32/src/flash/f4.rs
View File

@ -142,7 +142,6 @@ mod alt_regions {
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::ReadNorFlash for $type_name<'_, Async> {
const READ_SIZE: usize = crate::flash::READ_SIZE;
@ -155,7 +154,6 @@ mod alt_regions {
}
}
#[cfg(feature = "nightly")]
impl embedded_storage_async::nor_flash::NorFlash for $type_name<'_, Async> {
const WRITE_SIZE: usize = $region.write_size as usize;
const ERASE_SIZE: usize = $region.erase_size as usize;
@ -339,7 +337,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
pub(crate) fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

6
embassy-stm32/src/flash/f7.rs
View File

@ -6,11 +6,11 @@ use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -69,7 +69,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

6
embassy-stm32/src/flash/g0.rs → embassy-stm32/src/flash/g.rs
View File

@ -8,11 +8,11 @@ use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -92,6 +92,6 @@ pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

6
embassy-stm32/src/flash/h7.rs
View File

@ -6,7 +6,7 @@ use super::{FlashRegion, FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
@ -14,7 +14,7 @@ const fn is_dual_bank() -> bool {
FLASH_REGIONS.len() >= 2
}
pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -113,7 +113,7 @@ pub(crate) unsafe fn clear_all_err() {
unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
bank.sr().modify(|_| {});
}

6
embassy-stm32/src/flash/l.rs
View File

@ -5,11 +5,11 @@ use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
@ -120,7 +120,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
pub(crate) unsafe fn clear_all_err() {
// read and write back the same value.
// This clears all "write 0 to clear" bits.
// This clears all "write 1 to clear" bits.
pac::FLASH.sr().modify(|_| {});
}

82
embassy-stm32/src/flash/mod.rs
View File

@ -14,62 +14,96 @@ pub use crate::_generated::flash_regions::*;
pub use crate::_generated::MAX_ERASE_SIZE;
pub use crate::pac::{FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
/// Get whether the default flash layout is being used.
///
/// In some chips, dual-bank is not default. This will then return `false`
/// when dual-bank is enabled.
pub fn is_default_layout() -> bool {
family::is_default_layout()
}
/// Get all flash regions.
pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
family::get_flash_regions()
}
/// Read size (always 1)
pub const READ_SIZE: usize = 1;
pub struct Blocking;
pub struct Async;
/// Blocking flash mode typestate.
pub enum Blocking {}
/// Async flash mode typestate.
pub enum Async {}
/// Flash memory region
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct FlashRegion {
/// Bank number.
pub bank: FlashBank,
/// Absolute base address.
pub base: u32,
/// Size in bytes.
pub size: u32,
/// Erase size (sector size).
pub erase_size: u32,
/// Minimum write size.
pub write_size: u32,
/// Erase value (usually `0xFF`, but is `0x00` in some chips)
pub erase_value: u8,
pub(crate) _ensure_internal: (),
}
#[derive(Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct FlashSector {
pub bank: FlashBank,
pub index_in_bank: u8,
pub start: u32,
pub size: u32,
}
#[derive(Clone, Copy, Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FlashBank {
Bank1 = 0,
Bank2 = 1,
Otp,
}
impl FlashRegion {
/// Absolute end address.
pub const fn end(&self) -> u32 {
self.base + self.size
}
/// Number of sectors in the region.
pub const fn sectors(&self) -> u8 {
(self.size / self.erase_size) as u8
}
}
/// Flash sector.
#[derive(Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct FlashSector {
/// Bank number.
pub bank: FlashBank,
/// Sector number within the bank.
pub index_in_bank: u8,
/// Absolute start address.
pub start: u32,
/// Size in bytes.
pub size: u32,
}
/// Flash bank.
#[derive(Clone, Copy, Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FlashBank {
/// Bank 1
Bank1 = 0,
/// Bank 2
Bank2 = 1,
/// OTP region
Otp,
}
#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_wl, flash_wb), path = "l.rs")]
#[cfg_attr(flash_f0, path = "f0.rs")]
#[cfg_attr(flash_f3, path = "f3.rs")]
#[cfg_attr(flash_f4, path = "f4.rs")]
#[cfg_attr(flash_f7, path = "f7.rs")]
#[cfg_attr(flash_g0, path = "g0.rs")]
#[cfg_attr(any(flash_g0, flash_g4), path = "g.rs")]
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(flash_h7ab, path = "h7.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_h7,
flash_h7ab
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f3, flash_f4, flash_f7, flash_g0, flash_g4,
flash_h7, flash_h7ab
)),
path = "other.rs"
)]
@ -78,6 +112,10 @@ mod family;
#[allow(unused_imports)]
pub use family::*;
/// Flash error
///
/// See STM32 Reference Manual for your chip for details.
#[allow(missing_docs)]
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {

4
embassy-stm32/src/flash/other.rs
View File

@ -2,11 +2,11 @@
use super::{Error, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
pub const fn is_default_layout() -> bool {
pub(crate) const fn is_default_layout() -> bool {
true
}
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}

700
embassy-stm32/src/gpio.rs
View File

@ -29,6 +29,11 @@ impl<'d, T: Pin> Flex<'d, T> {
Self { pin }
}
/// Type-erase (degrade) this pin into an `AnyPin`.
///
/// This converts pin singletons (`PA5`, `PB6`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of pins, or avoiding generics.
#[inline]
pub fn degrade(self) -> Flex<'d, AnyPin> {
// Safety: We are about to drop the other copy of this pin, so
@ -141,40 +146,55 @@ impl<'d, T: Pin> Flex<'d, T> {
});
}
/// Get whether the pin input level is high.
#[inline]
pub fn is_high(&self) -> bool {
!self.is_low()
pub fn is_high(&mut self) -> bool {
!self.ref_is_low()
}
/// Get whether the pin input level is low.
#[inline]
pub fn is_low(&mut self) -> bool {
self.ref_is_low()
}
#[inline]
pub fn is_low(&self) -> bool {
pub(crate) fn ref_is_low(&self) -> bool {
let state = self.pin.block().idr().read().idr(self.pin.pin() as _);
state == vals::Idr::LOW
}
/// Get the current pin input level.
#[inline]
pub fn get_level(&self) -> Level {
pub fn get_level(&mut self) -> Level {
self.is_high().into()
}
/// Get whether the output level is set to high.
#[inline]
pub fn is_set_high(&self) -> bool {
!self.is_set_low()
pub fn is_set_high(&mut self) -> bool {
!self.ref_is_set_low()
}
/// Is the output pin set as low?
/// Get whether the output level is set to low.
#[inline]
pub fn is_set_low(&self) -> bool {
pub fn is_set_low(&mut self) -> bool {
self.ref_is_set_low()
}
#[inline]
pub(crate) fn ref_is_set_low(&self) -> bool {
let state = self.pin.block().odr().read().odr(self.pin.pin() as _);
state == vals::Odr::LOW
}
/// What level output is set to
/// Get the current output level.
#[inline]
pub fn get_output_level(&self) -> Level {
pub fn get_output_level(&mut self) -> Level {
self.is_set_high().into()
}
/// Set the output as high.
#[inline]
pub fn set_high(&mut self) {
self.pin.set_high();
@ -186,6 +206,7 @@ impl<'d, T: Pin> Flex<'d, T> {
self.pin.set_low();
}
/// Set the output level.
#[inline]
pub fn set_level(&mut self, level: Level) {
match level {
@ -194,7 +215,7 @@ impl<'d, T: Pin> Flex<'d, T> {
}
}
/// Toggle pin output
/// Toggle the output level.
#[inline]
pub fn toggle(&mut self) {
if self.is_set_low() {
@ -232,8 +253,11 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pull {
/// No pull
None,
/// Pull up
Up,
/// Pull down
Down,
}
@ -251,6 +275,9 @@ impl From<Pull> for vals::Pupdr {
}
/// Speed settings
///
/// These vary dpeending on the chip, ceck the reference manual or datasheet for details.
#[allow(missing_docs)]
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Speed {
@ -295,6 +322,7 @@ pub struct Input<'d, T: Pin> {
}
impl<'d, T: Pin> Input<'d, T> {
/// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
#[inline]
pub fn new(pin: impl Peripheral<P = T> + 'd, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
@ -302,6 +330,11 @@ impl<'d, T: Pin> Input<'d, T> {
Self { pin }
}
/// Type-erase (degrade) this pin into an `AnyPin`.
///
/// This converts pin singletons (`PA5`, `PB6`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of pins, or avoiding generics.
#[inline]
pub fn degrade(self) -> Input<'d, AnyPin> {
Input {
@ -309,18 +342,21 @@ impl<'d, T: Pin> Input<'d, T> {
}
}
/// Get whether the pin input level is high.
#[inline]
pub fn is_high(&self) -> bool {
pub fn is_high(&mut self) -> bool {
self.pin.is_high()
}
/// Get whether the pin input level is low.
#[inline]
pub fn is_low(&self) -> bool {
pub fn is_low(&mut self) -> bool {
self.pin.is_low()
}
/// Get the current pin input level.
#[inline]
pub fn get_level(&self) -> Level {
pub fn get_level(&mut self) -> Level {
self.pin.get_level()
}
}
@ -329,7 +365,9 @@ impl<'d, T: Pin> Input<'d, T> {
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Level {
/// Low
Low,
/// High
High,
}
@ -361,6 +399,7 @@ pub struct Output<'d, T: Pin> {
}
impl<'d, T: Pin> Output<'d, T> {
/// Create GPIO output driver for a [Pin] with the provided [Level] and [Speed] configuration.
#[inline]
pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level, speed: Speed) -> Self {
let mut pin = Flex::new(pin);
@ -372,6 +411,11 @@ impl<'d, T: Pin> Output<'d, T> {
Self { pin }
}
/// Type-erase (degrade) this pin into an `AnyPin`.
///
/// This converts pin singletons (`PA5`, `PB6`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of pins, or avoiding generics.
#[inline]
pub fn degrade(self) -> Output<'d, AnyPin> {
Output {
@ -399,19 +443,19 @@ impl<'d, T: Pin> Output<'d, T> {
/// Is the output pin set as high?
#[inline]
pub fn is_set_high(&self) -> bool {
pub fn is_set_high(&mut self) -> bool {
self.pin.is_set_high()
}
/// Is the output pin set as low?
#[inline]
pub fn is_set_low(&self) -> bool {
pub fn is_set_low(&mut self) -> bool {
self.pin.is_set_low()
}
/// What level output is set to
#[inline]
pub fn get_output_level(&self) -> Level {
pub fn get_output_level(&mut self) -> Level {
self.pin.get_output_level()
}
@ -432,6 +476,7 @@ pub struct OutputOpenDrain<'d, T: Pin> {
}
impl<'d, T: Pin> OutputOpenDrain<'d, T> {
/// Create a new GPIO open drain output driver for a [Pin] with the provided [Level] and [Speed], [Pull] configuration.
#[inline]
pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
@ -445,6 +490,11 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
Self { pin }
}
/// Type-erase (degrade) this pin into an `AnyPin`.
///
/// This converts pin singletons (`PA5`, `PB6`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of pins, or avoiding generics.
#[inline]
pub fn degrade(self) -> Output<'d, AnyPin> {
Output {
@ -452,19 +502,21 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
}
}
/// Get whether the pin input level is high.
#[inline]
pub fn is_high(&self) -> bool {
pub fn is_high(&mut self) -> bool {
!self.pin.is_low()
}
/// Get whether the pin input level is low.
#[inline]
pub fn is_low(&self) -> bool {
pub fn is_low(&mut self) -> bool {
self.pin.is_low()
}
/// Returns current pin level
/// Get the current pin input level.
#[inline]
pub fn get_level(&self) -> Level {
pub fn get_level(&mut self) -> Level {
self.pin.get_level()
}
@ -486,21 +538,21 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
self.pin.set_level(level);
}
/// Is the output pin set as high?
/// Get whether the output level is set to high.
#[inline]
pub fn is_set_high(&self) -> bool {
pub fn is_set_high(&mut self) -> bool {
self.pin.is_set_high()
}
/// Is the output pin set as low?
/// Get whether the output level is set to low.
#[inline]
pub fn is_set_low(&self) -> bool {
pub fn is_set_low(&mut self) -> bool {
self.pin.is_set_low()
}
/// What level output is set to
/// Get the current output level.
#[inline]
pub fn get_output_level(&self) -> Level {
pub fn get_output_level(&mut self) -> Level {
self.pin.get_output_level()
}
@ -511,8 +563,11 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
}
}
/// GPIO output type
pub enum OutputType {
/// Drive the pin both high or low.
PushPull,
/// Drive the pin low, or don't drive it at all if the output level is high.
OpenDrain,
}
@ -525,6 +580,7 @@ impl From<OutputType> for sealed::AFType {
}
}
#[allow(missing_docs)]
pub(crate) mod sealed {
use super::*;
@ -532,8 +588,11 @@ pub(crate) mod sealed {
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AFType {
/// Input
Input,
/// Output, drive the pin both high or low.
OutputPushPull,
/// Output, drive the pin low, or don't drive it at all if the output level is high.
OutputOpenDrain,
}
@ -676,7 +735,11 @@ pub(crate) mod sealed {
}
}
/// GPIO pin trait.
pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + sealed::Pin + Sized + 'static {
/// EXTI channel assigned to this pin.
///
/// For example, PC4 uses EXTI4.
#[cfg(feature = "exti")]
type ExtiChannel: crate::exti::Channel;
@ -692,7 +755,11 @@ pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + sealed::Pin + Sized + 'stat
self._port()
}
/// Convert from concrete pin type PX_XX to type erased `AnyPin`.
/// Type-erase (degrade) this pin into an `AnyPin`.
///
/// This converts pin singletons (`PA5`, `PB6`, ...), which
/// are all different types, into the same type. It is useful for
/// creating arrays of pins, or avoiding generics.
#[inline]
fn degrade(self) -> AnyPin {
AnyPin {
@ -701,12 +768,15 @@ pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + sealed::Pin + Sized + 'stat
}
}
// Type-erased GPIO pin
/// Type-erased GPIO pin
pub struct AnyPin {
pin_port: u8,
}
impl AnyPin {
/// Unsafely create an `AnyPin` from a pin+port number.
///
/// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
#[inline]
pub unsafe fn steal(pin_port: u8) -> Self {
Self { pin_port }
@ -717,6 +787,8 @@ impl AnyPin {
self.pin_port / 16
}
/// Get the GPIO register block for this pin.
#[cfg(feature = "unstable-pac")]
#[inline]
pub fn block(&self) -> gpio::Gpio {
pac::GPIO(self._port() as _)
@ -772,309 +844,297 @@ pub(crate) unsafe fn init(_cs: CriticalSection) {
});
}
mod eh02 {
use embedded_hal_02::digital::v2::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
type Error = Infallible;
use super::*;
impl<'d, T: Pin> InputPin for Input<'d, T> {
type Error = Infallible;
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(!self.pin.ref_is_low())
}
impl<'d, T: Pin> OutputPin for Output<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for Output<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
}
impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> StatefulOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
}
impl<'d, T: Pin> InputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> OutputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> StatefulOutputPin for Flex<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.pin.ref_is_low())
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use embedded_hal_1::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
type Error = Infallible;
use super::*;
impl<'d, T: Pin> ErrorType for Input<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
impl<'d, T: Pin> InputPin for Input<'d, T> {
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> ErrorType for Output<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> OutputPin for Output<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for Output<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> ErrorType for OutputOpenDrain<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> InputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> StatefulOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> InputPin for Flex<'d, T> {
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> OutputPin for Flex<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> ToggleableOutputPin for Flex<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> ErrorType for Flex<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> StatefulOutputPin for Flex<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(!self.pin.ref_is_set_low())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.pin.ref_is_set_low())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(!self.pin.ref_is_set_low())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.pin.ref_is_set_low())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(!self.ref_is_low())
}
#[inline]
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(self.ref_is_low())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
self.set_high();
Ok(())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
self.set_low();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(!self.ref_is_set_low())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(self.ref_is_set_low())
}
}
impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d, T> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
self.toggle();
Ok(())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Output<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for Output<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for OutputOpenDrain<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_high())
}
#[inline]
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
#[inline]
fn set_low(&mut self) -> Result<(), Self::Error> {
Ok(self.set_low())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ToggleableOutputPin for Flex<'d, T> {
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
Ok(self.toggle())
}
}
impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Flex<'d, T> {
type Error = Infallible;
}
impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
/// Is the output pin set as low?
#[inline]
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
Ok(self.is_set_low())
}
}
/// Low-level GPIO manipulation.
#[cfg(feature = "unstable-pac")]
pub mod low_level {
pub use super::sealed::*;

176
embassy-stm32/src/i2c/mod.rs
View File

@ -2,6 +2,7 @@
use core::marker::PhantomData;
use crate::dma::NoDma;
use crate::interrupt;
#[cfg_attr(i2c_v1, path = "v1.rs")]
@ -12,15 +13,23 @@ use embassy_sync::waitqueue::AtomicWaker;
use crate::peripherals;
/// I2C error.
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
/// Bus error
Bus,
/// Arbitration lost
Arbitration,
/// ACK not received (either to the address or to a data byte)
Nack,
/// Timeout
Timeout,
/// CRC error
Crc,
/// Overrun error
Overrun,
/// Zero-length transfers are not allowed.
ZeroLengthTransfer,
}
@ -46,8 +55,11 @@ pub(crate) mod sealed {
}
}
/// I2C peripheral instance
pub trait Instance: sealed::Instance + 'static {
/// Event interrupt for this instance
type EventInterrupt: interrupt::typelevel::Interrupt;
/// Error interrupt for this instance
type ErrorInterrupt: interrupt::typelevel::Interrupt;
}
@ -56,7 +68,7 @@ pin_trait!(SdaPin, Instance);
dma_trait!(RxDma, Instance);
dma_trait!(TxDma, Instance);
/// Interrupt handler.
/// Event interrupt handler.
pub struct EventInterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
@ -67,6 +79,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::EventInterrupt> for EventInte
}
}
/// Error interrupt handler.
pub struct ErrorInterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
@ -97,107 +110,92 @@ foreach_peripheral!(
};
);
mod eh02 {
use super::*;
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
type Error = Error;
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
type Error = Error;
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
type Error = Error;
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
type Error = Error;
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
use crate::dma::NoDma;
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
type Error = Error;
impl embedded_hal_1::i2c::Error for Error {
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
match *self {
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
Self::Nack => {
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
}
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
type Error = Error;
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
}
impl embedded_hal_1::i2c::Error for Error {
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
match *self {
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
Self::Nack => {
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
}
}
}
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
}
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, NoDma, NoDma> {
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
}
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
mod eha {
use super::*;
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
}
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.read(address, read).await
}
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, NoDma, NoDma> {
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.write(address, write).await
}
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.write_read(address, write, read).await
}
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
async fn transaction(
&mut self,
address: u8,
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
}
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.read(address, read).await
}
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.write(address, write).await
}
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.write_read(address, write, read).await
}
async fn transaction(
&mut self,
address: u8,
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
}

28
embassy-stm32/src/lib.rs
View File

@ -1,6 +1,5 @@
#![cfg_attr(not(test), no_std)]
#![cfg_attr(feature = "nightly", feature(async_fn_in_trait, impl_trait_projections))]
#![cfg_attr(feature = "nightly", allow(stable_features, unknown_lints, async_fn_in_trait))]
#![allow(async_fn_in_trait)]
//! ## Feature flags
#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
@ -64,6 +63,8 @@ pub mod sai;
pub mod sdmmc;
#[cfg(spi)]
pub mod spi;
#[cfg(uid)]
pub mod uid;
#[cfg(usart)]
pub mod usart;
#[cfg(usb)]
@ -89,6 +90,29 @@ pub use crate::_generated::interrupt;
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
///
/// Example of how to bind one interrupt:
///
/// ```rust,ignore
/// use embassy_stm32::{bind_interrupts, usb_otg, peripherals};
///
/// bind_interrupts!(struct Irqs {
/// OTG_FS => usb_otg::InterruptHandler<peripherals::USB_OTG_FS>;
/// });
/// ```
///
/// Example of how to bind multiple interrupts, and multiple handlers to each interrupt, in a single macro invocation:
///
/// ```rust,ignore
/// use embassy_stm32::{bind_interrupts, i2c, peripherals};
///
/// bind_interrupts!(struct Irqs {
/// I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
/// I2C2_3 => i2c::EventInterruptHandler<peripherals::I2C2>, i2c::ErrorInterruptHandler<peripherals::I2C2>,
/// i2c::EventInterruptHandler<peripherals::I2C3>, i2c::ErrorInterruptHandler<peripherals::I2C3>;
/// });
/// ```
// developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {

41
embassy-stm32/src/qspi/enums.rs
View File

@ -18,12 +18,17 @@ impl Into<u8> for QspiMode {
}
}
/// QSPI lane width
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum QspiWidth {
/// None
NONE,
/// Single lane
SING,
/// Dual lanes
DUAL,
/// Quad lanes
QUAD,
}
@ -38,10 +43,13 @@ impl Into<u8> for QspiWidth {
}
}
/// Flash bank selection
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum FlashSelection {
/// Bank 1
Flash1,
/// Bank 2
Flash2,
}
@ -54,6 +62,8 @@ impl Into<bool> for FlashSelection {
}
}
/// QSPI memory size.
#[allow(missing_docs)]
#[derive(Copy, Clone)]
pub enum MemorySize {
_1KiB,
@ -113,11 +123,16 @@ impl Into<u8> for MemorySize {
}
}
/// QSPI Address size
#[derive(Copy, Clone)]
pub enum AddressSize {
/// 8-bit address
_8Bit,
/// 16-bit address
_16Bit,
/// 24-bit address
_24bit,
/// 32-bit address
_32bit,
}
@ -132,8 +147,10 @@ impl Into<u8> for AddressSize {
}
}
/// Time the Chip Select line stays high.
#[allow(missing_docs)]
#[derive(Copy, Clone)]
pub enum ChipSelectHightTime {
pub enum ChipSelectHighTime {
_1Cycle,
_2Cycle,
_3Cycle,
@ -144,21 +161,23 @@ pub enum ChipSelectHightTime {
_8Cycle,
}
impl Into<u8> for ChipSelectHightTime {
impl Into<u8> for ChipSelectHighTime {
fn into(self) -> u8 {
match self {
ChipSelectHightTime::_1Cycle => 0,
ChipSelectHightTime::_2Cycle => 1,
ChipSelectHightTime::_3Cycle => 2,
ChipSelectHightTime::_4Cycle => 3,
ChipSelectHightTime::_5Cycle => 4,
ChipSelectHightTime::_6Cycle => 5,
ChipSelectHightTime::_7Cycle => 6,
ChipSelectHightTime::_8Cycle => 7,
ChipSelectHighTime::_1Cycle => 0,
ChipSelectHighTime::_2Cycle => 1,
ChipSelectHighTime::_3Cycle => 2,
ChipSelectHighTime::_4Cycle => 3,
ChipSelectHighTime::_5Cycle => 4,
ChipSelectHighTime::_6Cycle => 5,
ChipSelectHighTime::_7Cycle => 6,
ChipSelectHighTime::_8Cycle => 7,
}
}
}
/// FIFO threshold.
#[allow(missing_docs)]
#[derive(Copy, Clone)]
pub enum FIFOThresholdLevel {
_1Bytes,
@ -234,6 +253,8 @@ impl Into<u8> for FIFOThresholdLevel {
}
}
/// Dummy cycle count
#[allow(missing_docs)]
#[derive(Copy, Clone)]
pub enum DummyCycles {
_0,

6
embassy-stm32/src/qspi/mod.rs
View File

@ -54,7 +54,7 @@ pub struct Config {
/// Number of bytes to trigger FIFO threshold flag.
pub fifo_threshold: FIFOThresholdLevel,
/// Minimum number of cycles that chip select must be high between issued commands
pub cs_high_time: ChipSelectHightTime,
pub cs_high_time: ChipSelectHighTime,
}
impl Default for Config {
@ -64,7 +64,7 @@ impl Default for Config {
address_size: AddressSize::_24bit,
prescaler: 128,
fifo_threshold: FIFOThresholdLevel::_17Bytes,
cs_high_time: ChipSelectHightTime::_5Cycle,
cs_high_time: ChipSelectHighTime::_5Cycle,
}
}
}
@ -119,7 +119,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
Some(nss.map_into()),
dma,
config,
FlashSelection::Flash2,
FlashSelection::Flash1,
)
}

28
embassy-stm32/src/rcc/g0.rs
View File

@ -10,10 +10,18 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
Oscillator,
/// external analog clock (low swing) (HSEBYP=1)
Bypass,
}
/// System clock mux source
#[derive(Clone, Copy)]
pub enum ClockSrc {
HSE(Hertz),
HSE(Hertz, HseMode),
HSI(HSIPrescaler),
PLL(PllConfig),
LSI,
@ -61,7 +69,7 @@ impl Default for PllConfig {
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum PllSource {
HSI,
HSE(Hertz),
HSE(Hertz, HseMode),
}
/// Clocks configutation
@ -90,7 +98,7 @@ impl PllConfig {
pub(crate) fn init(self) -> Hertz {
let (src, input_freq) = match self.source {
PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
PllSource::HSE(freq) => (vals::Pllsrc::HSE, freq),
PllSource::HSE(freq, _) => (vals::Pllsrc::HSE, freq),
};
let m_freq = input_freq / self.m;
@ -125,8 +133,11 @@ impl PllConfig {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
PllSource::HSE(_) => {
RCC.cr().write(|w| w.set_hseon(true));
PllSource::HSE(_, mode) => {
RCC.cr().write(|w| {
w.set_hsebyp(mode != HseMode::Oscillator);
w.set_hseon(true);
});
while !RCC.cr().read().hserdy() {}
}
}
@ -177,9 +188,12 @@ pub(crate) unsafe fn init(config: Config) {
(HSI_FREQ / div, Sw::HSI)
}
ClockSrc::HSE(freq) => {
ClockSrc::HSE(freq, mode) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
RCC.cr().write(|w| {
w.set_hseon(true);
w.set_hsebyp(mode != HseMode::Oscillator);
});
while !RCC.cr().read().hserdy() {}
(freq, Sw::HSE)

3
embassy-stm32/src/rcc/g4.rs
View File

@ -308,6 +308,7 @@ pub(crate) unsafe fn init(config: Config) {
sys: sys_clk,
hclk1: ahb_freq,
hclk2: ahb_freq,
hclk3: ahb_freq,
pclk1: apb1_freq,
pclk1_tim: apb1_tim_freq,
pclk2: apb2_freq,
@ -315,6 +316,8 @@ pub(crate) unsafe fn init(config: Config) {
adc: adc12_ck,
adc34: adc345_ck,
pll1_p: None,
pll1_q: None, // TODO
hse: None, // TODO
rtc,
});
}

177
embassy-stm32/src/rcc/h.rs
View File

@ -70,7 +70,9 @@ pub struct Pll {
pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled.
/// On PLL1, it must be even (in particular, it cannot be 1.)
/// On PLL1, it must be even for most series (in particular,
/// it cannot be 1 in series other than STM32H723/733,
/// STM32H725/735 and STM32H730.)
pub divp: Option<PllDiv>,
/// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<PllDiv>,
@ -117,6 +119,75 @@ impl From<TimerPrescaler> for Timpre {
}
}
/// Power supply configuration
/// See RM0433 Rev 4 7.4
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
#[derive(PartialEq)]
pub enum SupplyConfig {
/// Default power supply configuration.
/// V CORE Power Domains are supplied from the LDO according to VOS.
/// SMPS step-down converter enabled at 1.2V, may be used to supply the LDO.
Default,
/// Power supply configuration using the LDO.
/// V CORE Power Domains are supplied from the LDO according to VOS.
/// LDO power mode (Main, LP, Off) will follow system low-power modes.
/// SMPS step-down converter disabled.
LDO,
/// Power supply configuration directly from the SMPS step-down converter.
/// V CORE Power Domains are supplied from SMPS step-down converter according to VOS.
/// LDO bypassed.
/// SMPS step-down converter power mode (MR, LP, Off) will follow system low-power modes.
DirectSMPS,
/// Power supply configuration from the SMPS step-down converter, that supplies the LDO.
/// V CORE Power Domains are supplied from the LDO according to VOS
/// LDO power mode (Main, LP, Off) will follow system low-power modes.
/// SMPS step-down converter enabled according to SDLEVEL, and supplies the LDO.
/// SMPS step-down converter power mode (MR, LP, Off) will follow system low-power modes.
SMPSLDO(SMPSSupplyVoltage),
/// Power supply configuration from SMPS supplying external circuits and potentially the LDO.
/// V CORE Power Domains are supplied from voltage regulator according to VOS
/// LDO power mode (Main, LP, Off) will follow system low-power modes.
/// SMPS step-down converter enabled according to SDLEVEL used to supply external circuits and may supply the LDO.
/// SMPS step-down converter forced ON in MR mode.
SMPSExternalLDO(SMPSSupplyVoltage),
/// Power supply configuration from SMPS supplying external circuits and bypassing the LDO.
/// V CORE supplied from external source
/// SMPS step-down converter enabled according to SDLEVEL used to supply external circuits and may supply the external source for V CORE .
/// SMPS step-down converter forced ON in MR mode.
SMPSExternalLDOBypass(SMPSSupplyVoltage),
/// Power supply configuration from an external source, SMPS disabled and the LDO bypassed.
/// V CORE supplied from external source
/// SMPS step-down converter disabled and LDO bypassed, voltage monitoring still active.
SMPSDisabledLDOBypass,
}
/// SMPS step-down converter voltage output level.
/// This is only used in certain power supply configurations:
/// SMPSLDO, SMPSExternalLDO, SMPSExternalLDOBypass.
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
#[derive(PartialEq)]
pub enum SMPSSupplyVoltage {
V1_8,
V2_5,
}
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
impl SMPSSupplyVoltage {
/// Convert SMPSSupplyVoltage to u8 representation.
fn to_u8(&self) -> u8 {
match self {
SMPSSupplyVoltage::V1_8 => 0b01,
SMPSSupplyVoltage::V2_5 => 0b10,
}
}
}
/// Configuration of the core clocks
#[non_exhaustive]
pub struct Config {
@ -144,6 +215,9 @@ pub struct Config {
pub timer_prescaler: TimerPrescaler,
pub voltage_scale: VoltageScale,
pub ls: super::LsConfig,
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
pub supply_config: SupplyConfig,
}
impl Default for Config {
@ -177,6 +251,9 @@ impl Default for Config {
timer_prescaler: TimerPrescaler::DefaultX2,
voltage_scale: VoltageScale::Scale0,
ls: Default::default(),
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
supply_config: SupplyConfig::Default,
}
}
}
@ -195,12 +272,58 @@ pub(crate) unsafe fn init(config: Config) {
});
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
PWR.cr3().modify(|w| {
// hardcode "Direct SPMS" for now, this is what works on nucleos with the
// default solderbridge configuration.
w.set_sden(true);
w.set_ldoen(false);
});
{
match config.supply_config {
SupplyConfig::Default => {
PWR.cr3().modify(|w| {
w.set_sdlevel(0b00);
w.set_sdexthp(false);
w.set_sden(true);
w.set_ldoen(true);
w.set_bypass(false);
});
}
SupplyConfig::LDO => {
PWR.cr3().modify(|w| {
w.set_sden(false);
w.set_ldoen(true);
w.set_bypass(false);
});
}
SupplyConfig::DirectSMPS => {
PWR.cr3().modify(|w| {
w.set_sdexthp(false);
w.set_sden(true);
w.set_ldoen(false);
w.set_bypass(false);
});
}
SupplyConfig::SMPSLDO(ref smps_supply_voltage)
| SupplyConfig::SMPSExternalLDO(ref smps_supply_voltage)
| SupplyConfig::SMPSExternalLDOBypass(ref smps_supply_voltage) => {
PWR.cr3().modify(|w| {
w.set_sdlevel(smps_supply_voltage.to_u8());
w.set_sdexthp(matches!(
config.supply_config,
SupplyConfig::SMPSExternalLDO(_) | SupplyConfig::SMPSExternalLDOBypass(_)
));
w.set_sden(true);
w.set_ldoen(matches!(
config.supply_config,
SupplyConfig::SMPSLDO(_) | SupplyConfig::SMPSExternalLDO(_)
));
w.set_bypass(matches!(config.supply_config, SupplyConfig::SMPSExternalLDOBypass(_)));
});
}
SupplyConfig::SMPSDisabledLDOBypass => {
PWR.cr3().modify(|w| {
w.set_sden(false);
w.set_ldoen(false);
w.set_bypass(true);
});
}
}
}
// Validate the supply configuration. If you are stuck here, it is
// because the voltages on your board do not match those specified
@ -355,7 +478,14 @@ pub(crate) unsafe fn init(config: Config) {
VoltageScale::Scale2 => (Hertz(160_000_000), Hertz(160_000_000), Hertz(80_000_000)),
VoltageScale::Scale3 => (Hertz(88_000_000), Hertz(88_000_000), Hertz(44_000_000)),
};
#[cfg(all(stm32h7, not(pwr_h7rm0455)))]
#[cfg(pwr_h7rm0468)]
let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
VoltageScale::Scale0 => (Hertz(520_000_000), Hertz(275_000_000), Hertz(137_500_000)),
VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
VoltageScale::Scale2 => (Hertz(300_000_000), Hertz(150_000_000), Hertz(75_000_000)),
VoltageScale::Scale3 => (Hertz(170_000_000), Hertz(85_000_000), Hertz(42_500_000)),
};
#[cfg(all(stm32h7, not(any(pwr_h7rm0455, pwr_h7rm0468))))]
let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
VoltageScale::Scale0 => (Hertz(480_000_000), Hertz(240_000_000), Hertz(120_000_000)),
VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
@ -608,9 +738,12 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
let p = config.divp.map(|div| {
if num == 0 {
// on PLL1, DIVP must be even.
// on PLL1, DIVP must be even for most series.
// The enum value is 1 less than the divider, so check it's odd.
#[cfg(not(pwr_h7rm0468))]
assert!(div.to_bits() % 2 == 1);
#[cfg(pwr_h7rm0468)]
assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0);
}
vco_clk / div
@ -699,7 +832,7 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
_ => unreachable!(),
};
#[cfg(flash_h7)]
#[cfg(all(flash_h7, not(pwr_h7rm0468)))]
let (latency, wrhighfreq) = match (vos, clk.0) {
// VOS 0 range VCORE 1.26V - 1.40V
(VoltageScale::Scale0, ..=70_000_000) => (0, 0),
@ -728,6 +861,30 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
_ => unreachable!(),
};
// See RM0468 Rev 3 Table 16. FLASH recommended number of wait
// states and programming delay
#[cfg(all(flash_h7, pwr_h7rm0468))]
let (latency, wrhighfreq) = match (vos, clk.0) {
// VOS 0 range VCORE 1.26V - 1.40V
(VoltageScale::Scale0, ..=70_000_000) => (0, 0),
(VoltageScale::Scale0, ..=140_000_000) => (1, 1),
(VoltageScale::Scale0, ..=210_000_000) => (2, 2),
(VoltageScale::Scale0, ..=275_000_000) => (3, 3),
// VOS 1 range VCORE 1.15V - 1.26V
(VoltageScale::Scale1, ..=67_000_000) => (0, 0),
(VoltageScale::Scale1, ..=133_000_000) => (1, 1),
(VoltageScale::Scale1, ..=200_000_000) => (2, 2),
// VOS 2 range VCORE 1.05V - 1.15V
(VoltageScale::Scale2, ..=50_000_000) => (0, 0),
(VoltageScale::Scale2, ..=100_000_000) => (1, 1),
(VoltageScale::Scale2, ..=150_000_000) => (2, 2),
// VOS 3 range VCORE 0.95V - 1.05V
(VoltageScale::Scale3, ..=35_000_000) => (0, 0),
(VoltageScale::Scale3, ..=70_000_000) => (1, 1),
(VoltageScale::Scale3, ..=85_000_000) => (2, 2),
_ => unreachable!(),
};
// See RM0455 Rev 10 Table 16. FLASH recommended number of wait
// states and programming delay
#[cfg(flash_h7ab)]

5
embassy-stm32/src/rcc/mod.rs
View File

@ -95,6 +95,7 @@ pub struct Clocks {
rcc_h7rm0433,
rcc_h7ab,
rcc_u5,
rcc_g4,
rcc_wb,
rcc_wl5,
rcc_wle
@ -119,7 +120,7 @@ pub struct Clocks {
#[cfg(any(stm32g4, rcc_l4))]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_l4))]
#[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g4))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
@ -167,7 +168,7 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
pub lse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
#[cfg(any(stm32h5, stm32h7, stm32g4))]
pub hse: Option<Hertz>,
#[cfg(stm32h5)]

2
embassy-stm32/src/rtc/datetime.rs
View File

@ -211,7 +211,7 @@ pub enum DayOfWeek {
#[cfg(feature = "chrono")]
impl From<chrono::Weekday> for DayOfWeek {
fn from(weekday: Weekday) -> Self {
day_of_week_from_u8(weekday.num_days_from_monday() as u8).unwrap()
day_of_week_from_u8(weekday.number_from_monday() as u8).unwrap()
}
}

4
embassy-stm32/src/sai/mod.rs
View File

@ -584,10 +584,10 @@ fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
};
match tx_rx {
TxRx::Transmitter => RingBuffer::Writable(unsafe {
WritableRingBuffer::new_write(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
WritableRingBuffer::new(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
}),
TxRx::Receiver => RingBuffer::Readable(unsafe {
ReadableRingBuffer::new_read(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
ReadableRingBuffer::new(dma, request, dr(T::REGS, sub_block), dma_buf, opts)
}),
}
}

8
embassy-stm32/src/sdmmc/mod.rs
View File

@ -1457,8 +1457,8 @@ cfg_if::cfg_if! {
macro_rules! kernel_clk {
($inst:ident) => {
critical_section::with(|_| unsafe {
crate::rcc::get_freqs().pll1_q
}).expect("PLL48 is required for SDIO")
unwrap!(crate::rcc::get_freqs().pll1_q)
})
}
}
} else if #[cfg(stm32f7)] {
@ -1469,7 +1469,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
unwrap!(crate::rcc::get_freqs().pll1_q)
}
})
};
@ -1479,7 +1479,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
unwrap!(crate::rcc::get_freqs().pll1_q)
}
})
};

138
embassy-stm32/src/spi/mod.rs
View File

@ -848,102 +848,88 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
Ok(rx_word)
}
mod eh02 {
use super::*;
// Note: It is not possible to impl these traits generically in embedded-hal 0.2 due to a conflict with
// some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
macro_rules! impl_blocking {
($w:ident) => {
impl<'d, T: Instance, Tx, Rx> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, T, Tx, Rx> {
type Error = Error;
// Note: It is not possible to impl these traits generically in embedded-hal 0.2 due to a conflict with
// some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
macro_rules! impl_blocking {
($w:ident) => {
impl<'d, T: Instance, Tx, Rx> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, T, Tx, Rx> {
type Error = Error;
fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
self.blocking_write(words)
}
fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
self.blocking_write(words)
}
}
impl<'d, T: Instance, Tx, Rx> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, T, Tx, Rx> {
type Error = Error;
impl<'d, T: Instance, Tx, Rx> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, T, Tx, Rx> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
self.blocking_transfer_in_place(words)?;
Ok(words)
}
fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
self.blocking_transfer_in_place(words)?;
Ok(words)
}
};
}
impl_blocking!(u8);
impl_blocking!(u16);
}
};
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
impl_blocking!(u8);
impl_blocking!(u16);
impl<'d, T: Instance, Tx, Rx> embedded_hal_1::spi::ErrorType for Spi<'d, T, Tx, Rx> {
type Error = Error;
impl<'d, T: Instance, Tx, Rx> embedded_hal_1::spi::ErrorType for Spi<'d, T, Tx, Rx> {
type Error = Error;
}
impl<'d, T: Instance, W: Word, Tx, Rx> embedded_hal_1::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> {
fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
impl<'d, T: Instance, W: Word, Tx, Rx> embedded_hal_1::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> {
fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.blocking_read(words)
}
fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
self.blocking_write(words)
}
fn transfer(&mut self, read: &mut [W], write: &[W]) -> Result<(), Self::Error> {
self.blocking_transfer(read, write)
}
fn transfer_in_place(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.blocking_transfer_in_place(words)
}
fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.blocking_read(words)
}
impl embedded_hal_1::spi::Error for Error {
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
match *self {
Self::Framing => embedded_hal_1::spi::ErrorKind::FrameFormat,
Self::Crc => embedded_hal_1::spi::ErrorKind::Other,
Self::ModeFault => embedded_hal_1::spi::ErrorKind::ModeFault,
Self::Overrun => embedded_hal_1::spi::ErrorKind::Overrun,
}
fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
self.blocking_write(words)
}
fn transfer(&mut self, read: &mut [W], write: &[W]) -> Result<(), Self::Error> {
self.blocking_transfer(read, write)
}
fn transfer_in_place(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.blocking_transfer_in_place(words)
}
}
impl embedded_hal_1::spi::Error for Error {
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
match *self {
Self::Framing => embedded_hal_1::spi::ErrorKind::FrameFormat,
Self::Crc => embedded_hal_1::spi::ErrorKind::Other,
Self::ModeFault => embedded_hal_1::spi::ErrorKind::ModeFault,
Self::Overrun => embedded_hal_1::spi::ErrorKind::Overrun,
}
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
mod eha {
use super::*;
impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> {
async fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> {
async fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
async fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
self.write(words).await
}
async fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
self.write(words).await
}
async fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.read(words).await
}
async fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.read(words).await
}
async fn transfer(&mut self, read: &mut [W], write: &[W]) -> Result<(), Self::Error> {
self.transfer(read, write).await
}
async fn transfer(&mut self, read: &mut [W], write: &[W]) -> Result<(), Self::Error> {
self.transfer(read, write).await
}
async fn transfer_in_place(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.transfer_in_place(words).await
}
async fn transfer_in_place(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
self.transfer_in_place(words).await
}
}

51
embassy-stm32/src/time_driver.rs
View File

@ -18,6 +18,17 @@ use crate::rtc::Rtc;
use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
use crate::{interrupt, peripherals};
// NOTE regarding ALARM_COUNT:
//
// As of 2023-12-04, this driver is implemented using CC1 as the halfway rollover interrupt, and any
// additional CC capabilities to provide timer alarms to embassy-time. embassy-time requires AT LEAST
// one alarm to be allocatable, which means timers that only have CC1, such as TIM16/TIM17, are not
// candidates for use as an embassy-time driver provider.
//
// The values of ALARM_COUNT below are not the TOTAL CC registers available, but rather the number
// available after reserving CC1 for regular time keeping. For example, TIM2 has four CC registers:
// CC1, CC2, CC3, and CC4, so it can provide ALARM_COUNT = 3.
#[cfg(not(any(time_driver_tim12, time_driver_tim15)))]
const ALARM_COUNT: usize = 3;
@ -32,7 +43,10 @@ type T = peripherals::TIM3;
type T = peripherals::TIM4;
#[cfg(time_driver_tim5)]
type T = peripherals::TIM5;
#[cfg(time_driver_tim9)]
type T = peripherals::TIM9;
#[cfg(time_driver_tim11)]
type T = peripherals::TIM11;
#[cfg(time_driver_tim12)]
type T = peripherals::TIM12;
#[cfg(time_driver_tim15)]
@ -71,6 +85,22 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
(TIM9, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim9)]
#[cfg(feature = "rt")]
#[interrupt]
fn $irq() {
DRIVER.on_interrupt()
}
};
(TIM11, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim11)]
#[cfg(feature = "rt")]
#[interrupt]
fn $irq() {
DRIVER.on_interrupt()
}
};
(TIM12, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim12)]
#[cfg(feature = "rt")]
@ -444,16 +474,29 @@ impl Driver for RtcDriver {
return false;
}
let safe_timestamp = timestamp.max(t + 3);
// Write the CCR value regardless of whether we're going to enable it now or not.
// This way, when we enable it later, the right value is already set.
r.ccr(n + 1).write(|w| w.set_ccr(safe_timestamp as u16));
r.ccr(n + 1).write(|w| w.set_ccr(timestamp as u16));
// Enable it if it'll happen soon. Otherwise, `next_period` will enable it.
let diff = timestamp - t;
r.dier().modify(|w| w.set_ccie(n + 1, diff < 0xc000));
// Reevaluate if the alarm timestamp is still in the future
let t = self.now();
if timestamp <= t {
// If alarm timestamp has passed since we set it, we have a race condition and
// the alarm may or may not have fired.
// Disarm the alarm and return `false` to indicate that.
// It is the caller's responsibility to handle this ambiguity.
r.dier().modify(|w| w.set_ccie(n + 1, false));
alarm.timestamp.set(u64::MAX);
return false;
}
// We're confident the alarm will ring in the future.
true
})
}

7
embassy-stm32/src/timer/mod.rs
View File

@ -46,7 +46,10 @@ pub(crate) mod sealed {
assert!(f > 0);
let pclk_ticks_per_timer_period = timer_f / f;
let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 16)).try_into());
let arr: u16 = unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into());
let divide_by = pclk_ticks_per_timer_period / (u32::from(psc) + 1);
// the timer counts `0..=arr`, we want it to count `0..divide_by`
let arr = unwrap!(u16::try_from(divide_by - 1));
let regs = Self::regs();
regs.psc().write(|r| r.set_psc(psc));
@ -74,7 +77,7 @@ pub(crate) mod sealed {
Self::regs().dier().write(|r| r.set_uie(enable));
}
fn set_autoreload_preload(&mut self, enable: vals::Arpe) {
fn set_autoreload_preload(&mut self, enable: bool) {
Self::regs().cr1().modify(|r| r.set_arpe(enable));
}

6
embassy-stm32/src/traits.rs
View File

@ -2,7 +2,9 @@
macro_rules! pin_trait {
($signal:ident, $instance:path) => {
#[doc = concat!(stringify!($signal), " pin trait")]
pub trait $signal<T: $instance>: crate::gpio::Pin {
#[doc = concat!("Get the AF number needed to use this pin as", stringify!($signal))]
fn af_num(&self) -> u8;
}
};
@ -22,7 +24,11 @@ macro_rules! pin_trait_impl {
macro_rules! dma_trait {
($signal:ident, $instance:path) => {
#[doc = concat!(stringify!($signal), " DMA request trait")]
pub trait $signal<T: $instance>: crate::dma::Channel {
#[doc = concat!("Get the DMA request number needed to use this channel as", stringify!($signal))]
/// Note: in some chips, ST calls this the "channel", and calls channels "streams".
/// `embassy-stm32` always uses the "channel" and "request number" names.
fn request(&self) -> crate::dma::Request;
}
};

29
embassy-stm32/src/uid.rs Normal file
View File

@ -0,0 +1,29 @@
/// Get this device's unique 96-bit ID.
pub fn uid() -> &'static [u8; 12] {
unsafe { &*crate::pac::UID.uid(0).as_ptr().cast::<[u8; 12]>() }
}
/// Get this device's unique 96-bit ID, encoded into a string of 24 hexadecimal ASCII digits.
pub fn uid_hex() -> &'static str {
unsafe { core::str::from_utf8_unchecked(uid_hex_bytes()) }
}
/// Get this device's unique 96-bit ID, encoded into 24 hexadecimal ASCII bytes.
pub fn uid_hex_bytes() -> &'static [u8; 24] {
const HEX: &[u8; 16] = b"0123456789ABCDEF";
static mut UID_HEX: [u8; 24] = [0; 24];
static mut LOADED: bool = false;
critical_section::with(|_| unsafe {
if !LOADED {
let uid = uid();
for (idx, v) in uid.iter().enumerate() {
let lo = v & 0x0f;
let hi = (v & 0xf0) >> 4;
UID_HEX[idx * 2] = HEX[hi as usize];
UID_HEX[idx * 2 + 1] = HEX[lo as usize];
}
LOADED = true;
}
});
unsafe { &UID_HEX }
}

256
embassy-stm32/src/usart/buffered.rs
View File

@ -560,172 +560,120 @@ impl<'d, T: BasicInstance> embedded_io::Write for BufferedUartTx<'d, T> {
}
}
mod eh02 {
use super::*;
impl<'d, T: BasicInstance> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d, T> {
type Error = Error;
impl<'d, T: BasicInstance> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d, T> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
let r = T::regs();
unsafe {
let sr = sr(r).read();
if sr.pe() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Parity))
} else if sr.fe() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Framing))
} else if sr.ne() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Noise))
} else if sr.ore() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Overrun))
} else if sr.rxne() {
Ok(rdr(r).read_volatile())
} else {
Err(nb::Error::WouldBlock)
}
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
let r = T::regs();
unsafe {
let sr = sr(r).read();
if sr.pe() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Parity))
} else if sr.fe() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Framing))
} else if sr.ne() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Noise))
} else if sr.ore() {
rdr(r).read_volatile();
Err(nb::Error::Other(Error::Overrun))
} else if sr.rxne() {
Ok(rdr(r).read_volatile())
} else {
Err(nb::Error::WouldBlock)
}
}
}
impl<'d, T: BasicInstance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d, T> {
type Error = Error;
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
while !buffer.is_empty() {
match self.blocking_write(buffer) {
Ok(0) => panic!("zero-length write."),
Ok(n) => buffer = &buffer[n..],
Err(e) => return Err(e),
}
}
Ok(())
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
impl<'d, T: BasicInstance> embedded_hal_02::serial::Read<u8> for BufferedUart<'d, T> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
embedded_hal_02::serial::Read::read(&mut self.rx)
}
}
impl<'d, T: BasicInstance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d, T> {
type Error = Error;
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
while !buffer.is_empty() {
match self.tx.blocking_write(buffer) {
Ok(0) => panic!("zero-length write."),
Ok(n) => buffer = &buffer[n..],
Err(e) => return Err(e),
}
}
Ok(())
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.tx.blocking_flush()
}
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
impl<'d, T: BasicInstance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d, T> {
type Error = Error;
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUart<'d, T> {
type Error = Error;
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
while !buffer.is_empty() {
match self.blocking_write(buffer) {
Ok(0) => panic!("zero-length write."),
Ok(n) => buffer = &buffer[n..],
Err(e) => return Err(e),
}
}
Ok(())
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d, T> {
type Error = Error;
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d, T> {
type Error = Error;
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Read for BufferedUartRx<'d, T> {
fn read(&mut self) -> nb::Result<u8, Self::Error> {
embedded_hal_02::serial::Read::read(self)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Write for BufferedUartTx<'d, T> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Read for BufferedUart<'d, T> {
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
embedded_hal_02::serial::Read::read(&mut self.rx)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Write for BufferedUart<'d, T> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.tx.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.tx.blocking_flush().map_err(nb::Error::Other)
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
#[cfg(all(
feature = "unstable-traits",
feature = "nightly",
feature = "_todo_embedded_hal_serial"
))]
mod eha {
use core::future::Future;
impl<'d, T: BasicInstance> embedded_hal_02::serial::Read<u8> for BufferedUart<'d, T> {
type Error = Error;
use super::*;
impl<'d, T: BasicInstance> embedded_hal_async::serial::Write for BufferedUartTx<'d, T> {
async fn write(&mut self, buf: &[u8]) -> Result<(), Self::Error> {
Self::write(buf)
}
async fn flush(&mut self) -> Result<(), Self::Error> {
Self::flush()
}
}
impl<'d, T: BasicInstance> embedded_hal_async::serial::Read for BufferedUartRx<'d, T> {
async fn read(&mut self, buf: &mut [u8]) -> Result<(), Self::Error> {
Self::read(buf)
}
}
impl<'d, T: BasicInstance> embedded_hal_async::serial::Write for BufferedUart<'d, T> {
async fn write(&mut self, buf: &[u8]) -> Result<(), Self::Error> {
self.tx.write(buf)
}
async fn flush(&mut self) -> Result<(), Self::Error> {
self.tx.flush()
}
}
impl<'d, T: BasicInstance> embedded_hal_async::serial::Read for BufferedUart<'d, T> {
async fn read(&mut self, buf: &mut [u8]) -> Result<(), Self::Error> {
self.rx.read(buf)
}
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
embedded_hal_02::serial::Read::read(&mut self.rx)
}
}
impl<'d, T: BasicInstance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d, T> {
type Error = Error;
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
while !buffer.is_empty() {
match self.tx.blocking_write(buffer) {
Ok(0) => panic!("zero-length write."),
Ok(n) => buffer = &buffer[n..],
Err(e) => return Err(e),
}
}
Ok(())
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.tx.blocking_flush()
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUart<'d, T> {
type Error = Error;
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d, T> {
type Error = Error;
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d, T> {
type Error = Error;
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Read for BufferedUartRx<'d, T> {
fn read(&mut self) -> nb::Result<u8, Self::Error> {
embedded_hal_02::serial::Read::read(self)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Write for BufferedUartTx<'d, T> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Read for BufferedUart<'d, T> {
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
embedded_hal_02::serial::Read::read(&mut self.rx)
}
}
impl<'d, T: BasicInstance> embedded_hal_nb::serial::Write for BufferedUart<'d, T> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.tx.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.tx.blocking_flush().map_err(nb::Error::Other)
}
}

233
embassy-stm32/src/usart/mod.rs
View File

@ -132,6 +132,14 @@ pub struct Config {
/// Set this to true to swap the RX and TX pins.
#[cfg(any(usart_v3, usart_v4))]
pub swap_rx_tx: bool,
/// Set this to true to invert TX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
#[cfg(any(usart_v3, usart_v4))]
pub invert_tx: bool,
/// Set this to true to invert RX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
#[cfg(any(usart_v3, usart_v4))]
pub invert_rx: bool,
}
impl Default for Config {
@ -147,6 +155,10 @@ impl Default for Config {
assume_noise_free: false,
#[cfg(any(usart_v3, usart_v4))]
swap_rx_tx: false,
#[cfg(any(usart_v3, usart_v4))]
invert_tx: false,
#[cfg(any(usart_v3, usart_v4))]
invert_rx: false,
}
}
}
@ -972,7 +984,11 @@ fn configure(
});
#[cfg(any(usart_v3, usart_v4))]
w.set_swap(config.swap_rx_tx);
{
w.set_txinv(config.invert_tx);
w.set_rxinv(config.invert_rx);
w.set_swap(config.swap_rx_tx);
}
});
#[cfg(not(usart_v1))]
@ -1010,102 +1026,93 @@ fn configure(
Ok(())
}
mod eh02 {
use super::*;
impl<'d, T: BasicInstance, RxDma> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, RxDma> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
impl<'d, T: BasicInstance, RxDma> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, RxDma> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, TxDma> {
type Error = Error;
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(buffer)
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_02::blocking::serial::Write<u8> for UartTx<'d, T, TxDma> {
type Error = Error;
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(buffer)
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::serial::Read<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(buffer)
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::serial::Read<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8> for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(buffer)
}
fn bflush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
impl embedded_hal_nb::serial::Error for Error {
fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
match *self {
Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise,
Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
Self::BufferTooLong => embedded_hal_nb::serial::ErrorKind::Other,
}
}
}
#[cfg(feature = "unstable-traits")]
mod eh1 {
use super::*;
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::ErrorType for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
}
impl embedded_hal_nb::serial::Error for Error {
fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
match *self {
Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise,
Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
Self::BufferTooLong => embedded_hal_nb::serial::ErrorKind::Other,
}
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_nb::serial::ErrorType for UartTx<'d, T, TxDma> {
type Error = Error;
}
impl<'d, T: BasicInstance, RxDma> embedded_hal_nb::serial::ErrorType for UartRx<'d, T, RxDma> {
type Error = Error;
}
impl<'d, T: BasicInstance, RxDma> embedded_hal_nb::serial::Read for UartRx<'d, T, RxDma> {
fn read(&mut self) -> nb::Result<u8, Self::Error> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_nb::serial::Write for UartTx<'d, T, TxDma> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map_err(nb::Error::Other)
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::ErrorType for Uart<'d, T, TxDma, RxDma> {
type Error = Error;
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Read for Uart<'d, T, TxDma, RxDma> {
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Write for Uart<'d, T, TxDma, RxDma> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map_err(nb::Error::Other)
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_nb::serial::ErrorType for UartTx<'d, T, TxDma> {
type Error = Error;
}
impl<'d, T: BasicInstance, RxDma> embedded_hal_nb::serial::ErrorType for UartRx<'d, T, RxDma> {
type Error = Error;
}
impl<'d, T: BasicInstance, RxDma> embedded_hal_nb::serial::Read for UartRx<'d, T, RxDma> {
fn read(&mut self) -> nb::Result<u8, Self::Error> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma> embedded_hal_nb::serial::Write for UartTx<'d, T, TxDma> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Read for Uart<'d, T, TxDma, RxDma> {
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
self.nb_read()
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_nb::serial::Write for Uart<'d, T, TxDma, RxDma> {
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
self.blocking_write(&[char]).map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
fn flush(&mut self) -> nb::Result<(), Self::Error> {
self.blocking_flush().map_err(nb::Error::Other)
}
}
@ -1159,47 +1166,39 @@ where
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
mod eio {
use super::*;
impl<T, TxDma, RxDma> embedded_io_async::Write for Uart<'_, T, TxDma, RxDma>
where
T: BasicInstance,
TxDma: super::TxDma<T>,
{
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.write(buf).await?;
Ok(buf.len())
}
async fn flush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
impl<T, TxDma, RxDma> embedded_io_async::Write for Uart<'_, T, TxDma, RxDma>
where
T: BasicInstance,
TxDma: self::TxDma<T>,
{
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.write(buf).await?;
Ok(buf.len())
}
impl<T, TxDma> embedded_io_async::Write for UartTx<'_, T, TxDma>
where
T: BasicInstance,
TxDma: super::TxDma<T>,
{
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.write(buf).await?;
Ok(buf.len())
}
async fn flush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
async fn flush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
impl<T, TxDma> embedded_io_async::Write for UartTx<'_, T, TxDma>
where
T: BasicInstance,
TxDma: self::TxDma<T>,
{
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.write(buf).await?;
Ok(buf.len())
}
async fn flush(&mut self) -> Result<(), Self::Error> {
self.blocking_flush()
}
}
#[cfg(feature = "nightly")]
pub use buffered::*;
#[cfg(feature = "nightly")]
pub use crate::usart::buffered::InterruptHandler as BufferedInterruptHandler;
#[cfg(feature = "nightly")]
mod buffered;
#[cfg(not(gpdma))]
@ -1284,7 +1283,6 @@ pub(crate) mod sealed {
fn regs() -> Regs;
fn state() -> &'static State;
#[cfg(feature = "nightly")]
fn buffered_state() -> &'static buffered::State;
}
@ -1322,7 +1320,6 @@ macro_rules! impl_usart {
&STATE
}
#[cfg(feature = "nightly")]
fn buffered_state() -> &'static buffered::State {
static STATE: buffered::State = buffered::State::new();
&STATE

40
embassy-stm32/src/usart/ringbuffered.rs
View File

@ -7,7 +7,7 @@ use embassy_embedded_hal::SetConfig;
use embassy_hal_internal::PeripheralRef;
use futures::future::{select, Either};
use super::{clear_interrupt_flags, rdr, reconfigure, sr, BasicInstance, Config, ConfigError, Error, UartRx};
use super::{clear_interrupt_flags, rdr, reconfigure, sr, BasicInstance, Config, ConfigError, Error, RxDma, UartRx};
use crate::dma::ReadableRingBuffer;
use crate::usart::{Regs, Sr};
@ -39,7 +39,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
let rx_dma = unsafe { self.rx_dma.clone_unchecked() };
let _peri = unsafe { self._peri.clone_unchecked() };
let ring_buf = unsafe { ReadableRingBuffer::new_read(rx_dma, request, rdr(T::regs()), dma_buf, opts) };
let ring_buf = unsafe { ReadableRingBuffer::new(rx_dma, request, rdr(T::regs()), dma_buf, opts) };
// Don't disable the clock
mem::forget(self);
@ -240,28 +240,20 @@ fn clear_idle_flag(r: Regs) -> Sr {
sr
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
mod eio {
use embedded_io_async::{ErrorType, Read};
impl<T, Rx> embedded_io_async::ErrorType for RingBufferedUartRx<'_, T, Rx>
where
T: BasicInstance,
Rx: RxDma<T>,
{
type Error = Error;
}
use super::RingBufferedUartRx;
use crate::usart::{BasicInstance, Error, RxDma};
impl<T, Rx> ErrorType for RingBufferedUartRx<'_, T, Rx>
where
T: BasicInstance,
Rx: RxDma<T>,
{
type Error = Error;
}
impl<T, Rx> Read for RingBufferedUartRx<'_, T, Rx>
where
T: BasicInstance,
Rx: RxDma<T>,
{
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
self.read(buf).await
}
impl<T, Rx> embedded_io_async::Read for RingBufferedUartRx<'_, T, Rx>
where
T: BasicInstance,
Rx: RxDma<T>,
{
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
self.read(buf).await
}
}

2
embassy-stm32/src/usb/mod.rs
View File

@ -1,9 +1,7 @@
use crate::interrupt;
use crate::rcc::RccPeripheral;
#[cfg(feature = "nightly")]
mod usb;
#[cfg(feature = "nightly")]
pub use usb::*;
pub(crate) mod sealed {

2
embassy-stm32/src/usb/usb.rs
View File

@ -263,7 +263,7 @@ impl<'d, T: Instance> Driver<'d, T> {
let regs = T::regs();
#[cfg(stm32l5)]
#[cfg(any(stm32l5, stm32wb))]
crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
#[cfg(pwr_h5)]

10
embassy-stm32/src/usb_otg/mod.rs
View File

@ -1,13 +1,10 @@
use crate::rcc::RccPeripheral;
use crate::{interrupt, peripherals};
#[cfg(feature = "nightly")]
mod usb;
#[cfg(feature = "nightly")]
pub use usb::*;
// Using Instance::ENDPOINT_COUNT requires feature(const_generic_expr) so just define maximum eps
#[cfg(feature = "nightly")]
const MAX_EP_COUNT: usize = 9;
pub(crate) mod sealed {
@ -17,7 +14,6 @@ pub(crate) mod sealed {
const ENDPOINT_COUNT: usize;
fn regs() -> crate::pac::otg::Otg;
#[cfg(feature = "nightly")]
fn state() -> &'static super::State<{ super::MAX_EP_COUNT }>;
}
}
@ -99,8 +95,7 @@ foreach_interrupt!(
crate::pac::USB_OTG_FS
}
#[cfg(feature = "nightly")]
fn state() -> &'static State<MAX_EP_COUNT> {
fn state() -> &'static State<MAX_EP_COUNT> {
static STATE: State<MAX_EP_COUNT> = State::new();
&STATE
}
@ -151,8 +146,7 @@ foreach_interrupt!(
unsafe { crate::pac::otg::Otg::from_ptr(crate::pac::USB_OTG_HS.as_ptr()) }
}
#[cfg(feature = "nightly")]
fn state() -> &'static State<MAX_EP_COUNT> {
fn state() -> &'static State<MAX_EP_COUNT> {
static STATE: State<MAX_EP_COUNT> = State::new();
&STATE
}