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Add memory barriers to H7 flash driver to mitigate PGSERR errors

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The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.
This commit is contained in:
Matous Hybl 2022-10-18 22:42:02 +02:00
parent 18453ee64c
commit 6c5d81ada5
1 changed files with 8 additions and 0 deletions
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8
embassy-stm32/src/flash/h7.rs
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@ -39,6 +39,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
w.set_psize(2); // 32 bits at once w.set_psize(2); // 32 bits at once
}); });
cortex_m::asm::isb();
cortex_m::asm::dsb();
atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
let ret = { let ret = {
let mut ret: Result<(), Error> = Ok(()); let mut ret: Result<(), Error> = Ok(());
let mut offset = offset; let mut offset = offset;
@ -64,6 +68,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
bank.cr().write(|w| w.set_pg(false)); bank.cr().write(|w| w.set_pg(false));
cortex_m::asm::isb();
cortex_m::asm::dsb();
atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
ret ret
} }