max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge pull request #1606 from JcBernack/rng-update

Browse Source 
STM32: RNG update
This commit is contained in:
Dario Nieuwenhuis
2023-07-30 23:44:11 +00:00
committed by GitHub
parent 105aa8f452 4999b045df
commit 6c6bd11c1a
16 changed files with 192 additions and 111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
embassy-stm32/Cargo.toml
View File

@ -57,7 +57,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
stm32-metapac = "13"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1f8ab493e029fc601edebc6bac105a63cc9858fe" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@ -75,7 +75,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { version = "13", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1f8ab493e029fc601edebc6bac105a63cc9858fe", default-features = false, features = ["metadata"]}
[features]
default = ["rt"]

204
embassy-stm32/src/rng.rs
View File

@ -1,15 +1,17 @@
#![macro_use]
use core::future::poll_fn;
use core::marker::PhantomData;
use core::task::Poll;
use embassy_hal_internal::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use rand_core::{CryptoRng, RngCore};
use crate::{pac, peripherals, Peripheral};
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, pac, peripherals, Peripheral};
pub(crate) static RNG_WAKER: AtomicWaker = AtomicWaker::new();
static RNG_WAKER: AtomicWaker = AtomicWaker::new();
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
@ -17,68 +19,145 @@ pub enum Error {
ClockError,
}
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let bits = T::regs().sr().read();
if bits.drdy() || bits.seis() || bits.ceis() {
T::regs().cr().modify(|reg| reg.set_ie(false));
RNG_WAKER.wake();
}
}
}
pub struct Rng<'d, T: Instance> {
_inner: PeripheralRef<'d, T>,
}
impl<'d, T: Instance> Rng<'d, T> {
pub fn new(inner: impl Peripheral<P = T> + 'd) -> Self {
pub fn new(
inner: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
T::enable();
T::reset();
into_ref!(inner);
let mut random = Self { _inner: inner };
random.reset();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
random
}
#[cfg(rng_v1)]
pub fn reset(&mut self) {
// rng_v2 locks up on seed error, needs reset
#[cfg(rng_v2)]
if T::regs().sr().read().seis() {
T::reset();
}
T::regs().cr().modify(|reg| {
reg.set_rngen(true);
reg.set_ie(true);
T::regs().cr().write(|reg| {
reg.set_rngen(false);
});
T::regs().sr().modify(|reg| {
reg.set_seis(false);
reg.set_ceis(false);
});
T::regs().cr().modify(|reg| {
reg.set_rngen(true);
});
// Reference manual says to discard the first.
let _ = self.next_u32();
}
pub async fn async_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), Error> {
#[cfg(not(rng_v1))]
pub fn reset(&mut self) {
T::regs().cr().write(|reg| {
reg.set_rngen(false);
reg.set_condrst(true);
// set RNG config "A" according to reference manual
// this has to be written within the same write access as setting the CONDRST bit
reg.set_nistc(pac::rng::vals::Nistc::DEFAULT);
reg.set_rng_config1(pac::rng::vals::RngConfig1::CONFIGA);
reg.set_rng_config2(pac::rng::vals::RngConfig2::CONFIGA_B);
reg.set_rng_config3(pac::rng::vals::RngConfig3::CONFIGA);
reg.set_clkdiv(pac::rng::vals::Clkdiv::NODIV);
});
// wait for CONDRST to be set
while !T::regs().cr().read().condrst() {}
// magic number must be written immediately before every read or write access to HTCR
T::regs().htcr().write(|w| w.set_htcfg(pac::rng::vals::Htcfg::MAGIC));
// write recommended value according to reference manual
// note: HTCR can only be written during conditioning
T::regs()
.htcr()
.write(|w| w.set_htcfg(pac::rng::vals::Htcfg::RECOMMENDED));
// finish conditioning
T::regs().cr().modify(|reg| {
reg.set_rngen(true);
reg.set_condrst(false);
});
// wait for CONDRST to be reset
while T::regs().cr().read().condrst() {}
}
pub fn recover_seed_error(&mut self) -> () {
self.reset();
// reset should also clear the SEIS flag
if T::regs().sr().read().seis() {
warn!("recovering from seed error failed");
return;
}
// wait for SECS to be cleared by RNG
while T::regs().sr().read().secs() {}
}
pub async fn async_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), Error> {
for chunk in dest.chunks_mut(4) {
poll_fn(|cx| {
RNG_WAKER.register(cx.waker());
T::regs().cr().modify(|reg| {
reg.set_ie(true);
});
let bits = T::regs().sr().read();
if bits.drdy() {
Poll::Ready(Ok(()))
} else if bits.seis() {
self.reset();
Poll::Ready(Err(Error::SeedError))
} else if bits.ceis() {
self.reset();
Poll::Ready(Err(Error::ClockError))
} else {
Poll::Pending
let bits = T::regs().sr().read();
if bits.seis() {
// in case of noise-source or seed error we try to recover here
// but we must not use the data in DR and we return an error
// to leave retry-logic to the application
self.recover_seed_error();
return Err(Error::SeedError);
} else if bits.ceis() {
// clock error detected, DR could still be used but keep it safe,
// clear the error and abort
T::regs().sr().modify(|sr| sr.set_ceis(false));
return Err(Error::ClockError);
} else if bits.drdy() {
// DR can be read up to four times until the output buffer is empty
// DRDY is cleared automatically when that happens
let random_word = T::regs().dr().read();
// reference manual: always check if DR is zero
if random_word == 0 {
return Err(Error::SeedError);
}
})
.await?;
let random_bytes = T::regs().dr().read().to_be_bytes();
for (dest, src) in chunk.iter_mut().zip(random_bytes.iter()) {
*dest = *src
// write bytes to chunk
for (dest, src) in chunk.iter_mut().zip(random_word.to_be_bytes().iter()) {
*dest = *src
}
} else {
// wait for interrupt
poll_fn(|cx| {
// quick check to avoid registration if already done.
let bits = T::regs().sr().read();
if bits.drdy() || bits.seis() || bits.ceis() {
return Poll::Ready(());
}
RNG_WAKER.register(cx.waker());
T::regs().cr().modify(|reg| reg.set_ie(true));
// Need to check condition **after** `register` to avoid a race
// condition that would result in lost notifications.
let bits = T::regs().sr().read();
if bits.drdy() || bits.seis() || bits.ceis() {
Poll::Ready(())
} else {
Poll::Pending
}
})
.await;
}
}
@ -129,57 +208,20 @@ pub(crate) mod sealed {
}
}
pub trait Instance: sealed::Instance + crate::rcc::RccPeripheral {}
pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
type Interrupt: interrupt::typelevel::Interrupt;
}
foreach_peripheral!(
(rng, $inst:ident) => {
impl Instance for peripherals::$inst {}
foreach_interrupt!(
($inst:ident, rng, RNG, GLOBAL, $irq:ident) => {
impl Instance for peripherals::$inst {
type Interrupt = crate::interrupt::typelevel::$irq;
}
impl sealed::Instance for peripherals::$inst {
fn regs() -> crate::pac::rng::Rng {
crate::pac::RNG
crate::pac::$inst
}
}
};
);
#[cfg(feature = "rt")]
macro_rules! irq {
($irq:ident) => {
mod rng_irq {
use crate::interrupt;
#[interrupt]
unsafe fn $irq() {
let bits = $crate::pac::RNG.sr().read();
if bits.drdy() || bits.seis() || bits.ceis() {
$crate::pac::RNG.cr().write(|reg| reg.set_ie(false));
$crate::rng::RNG_WAKER.wake();
}
}
}
};
}
#[cfg(feature = "rt")]
foreach_interrupt!(
(RNG) => {
irq!(RNG);
};
(RNG_LPUART1) => {
irq!(RNG_LPUART1);
};
(AES_RNG_LPUART1) => {
irq!(AES_RNG_LPUART1);
};
(AES_RNG) => {
irq!(AES_RNG);
};
(HASH_RNG) => {
irq!(HASH_RNG);
};
);