Refactor
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8dd3ddd228
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@ -268,10 +268,20 @@ pub fn gen(options: Options) {
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}
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}
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if let Some(rcc) = &rcc {
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if let Some(rcc) = &rcc {
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let mut generate_rcc_peripheral = |clock_prefix| {
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let clock_prefix: Option<&str> = if let Some(clock) = &p.clock {
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Some(clock)
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} else if name.starts_with("TIM") {
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// Not all peripherals like timers the clock hint due to insufficient information from
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// chip definition. If clock is not specified, the first matching register with the
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// expected field will be used.
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Some("")
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} else {
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None
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};
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if let Some(clock_prefix) = clock_prefix {
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// Workaround for clock registers being split on some chip families. Assume fields are
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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// named after peripheral and look for first field matching and use that register.
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let en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
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let en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
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let rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
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let rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
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@ -295,15 +305,6 @@ pub fn gen(options: Options) {
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println!("Unable to find enable and reset register for {}", name)
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println!("Unable to find enable and reset register for {}", name)
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}
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}
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}
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}
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};
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if let Some(clock) = &p.clock {
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generate_rcc_peripheral(clock);
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} else if name.starts_with("TIM") {
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// Not all peripherals like timers the clock hint due to insufficient information from
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// chip definition. If clock is not specified, the first matching register with the
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// expected field will be used.
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generate_rcc_peripheral("");
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}
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}
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}
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}
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}
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}
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