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This commit is contained in:
Ulf Lilleengen 2021-06-11 16:21:51 +02:00
parent 8dd3ddd228
commit 6c7fd3e3c4
1 changed files with 12 additions and 11 deletions
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23
stm32-metapac/gen/src/lib.rs
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@ -268,10 +268,20 @@ pub fn gen(options: Options) {
}
if let Some(rcc) = &rcc {
let mut generate_rcc_peripheral = |clock_prefix| {
let clock_prefix: Option<&str> = if let Some(clock) = &p.clock {
Some(clock)
} else if name.starts_with("TIM") {
// Not all peripherals like timers the clock hint due to insufficient information from
// chip definition. If clock is not specified, the first matching register with the
// expected field will be used.
Some("")
} else {
None
};
if let Some(clock_prefix) = clock_prefix {
// Workaround for clock registers being split on some chip families. Assume fields are
// named after peripheral and look for first field matching and use that register.
let en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
let rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
@ -295,15 +305,6 @@ pub fn gen(options: Options) {
println!("Unable to find enable and reset register for {}", name)
}
}
};
if let Some(clock) = &p.clock {
generate_rcc_peripheral(clock);
} else if name.starts_with("TIM") {
// Not all peripherals like timers the clock hint due to insufficient information from
// chip definition. If clock is not specified, the first matching register with the
// expected field will be used.
generate_rcc_peripheral("");
}
}
}