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eth-v2: Get hclk frequency from clock singleton

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This commit is contained in:
Thales Fragoso 2021-06-14 17:20:04 -03:00 committed by Dario Nieuwenhuis
parent f7e1f262af
commit 6cecc6d4b5
1 changed files with 4 additions and 3 deletions
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7
embassy-stm32/src/eth/v2/mod.rs
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@ -14,7 +14,6 @@ use crate::gpio::Pin as GpioPin;
use crate::pac::gpio::vals::Ospeedr;
use crate::pac::{ETH, RCC, SYSCFG};
use crate::peripherals;
use crate::time::Hertz;
mod descriptors;
use super::{StationManagement, PHY};
@ -44,7 +43,6 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
tx_en: impl Unborrow<Target = impl TXEnPin> + 'd,
phy: P,
mac_addr: [u8; 6],
hclk: Hertz,
phy_addr: u8,
) -> Self {
unborrow!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
@ -118,8 +116,11 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
});
}
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
let hclk = unsafe { crate::rcc::get_freqs().ahb1 };
let hclk_mhz = hclk.0 / 1_000_000;
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
let clock_range = match hclk_mhz {
0..=34 => 2, // Divide by 16
35..=59 => 3, // Divide by 26