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eth-v2: Fix setting the registers for the descriptors

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Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
This commit is contained in:
Thales Fragoso
2021-06-11 11:51:51 -03:00
committed by Dario Nieuwenhuis
parent 0b42e12604
commit 6daa55a897
2 changed files with 17 additions and 12 deletions
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13
embassy-stm32/src/eth/v2/descriptors.rs
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@ -102,10 +102,10 @@ impl<const N: usize> TDesRing<N> {
let dma = ETH.ethernet_dma();
dma.dmactx_dlar()
.write(|w| w.set_tdesla(&self.td as *const _ as u32));
.write(|w| w.0 = &self.td as *const _ as u32);
dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
dma.dmactx_dtpr()
.write(|w| w.set_tdt(&self.td[0] as *const _ as u32));
.write(|w| w.0 = &self.td[0] as *const _ as u32);
}
}
@ -148,7 +148,7 @@ impl<const N: usize> TDesRing<N> {
unsafe {
ETH.ethernet_dma()
.dmactx_dtpr()
.write(|w| w.set_tdt(&self.td[x] as *const _ as u32));
.write(|w| w.0 = &self.td[x] as *const _ as u32);
}
self.tdidx = x;
Ok(())
@ -279,8 +279,7 @@ impl<const N: usize> RDesRing<N> {
unsafe {
let dma = ETH.ethernet_dma();
dma.dmacrx_dlar()
.write(|w| w.set_rdesla(self.rd.as_ptr() as u32));
dma.dmacrx_dlar().write(|w| w.0 = self.rd.as_ptr() as u32);
dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
// We manage to allocate all buffers, set the index to the last one, that means
@ -290,7 +289,7 @@ impl<const N: usize> RDesRing<N> {
let tail_ptr = &self.rd[last_index] as *const _ as u32;
fence(Ordering::Release);
dma.dmacrx_dtpr().write(|w| w.set_rdt(tail_ptr));
dma.dmacrx_dtpr().write(|w| w.0 = tail_ptr);
}
}
@ -340,7 +339,7 @@ impl<const N: usize> RDesRing<N> {
unsafe {
ETH.ethernet_dma()
.dmacrx_dtpr()
.write(|w| w.set_rdt(&self.rd[self.tail_idx] as *const _ as u32));
.write(|w| w.0 = &self.rd[self.tail_idx] as *const _ as u32);
}
self.tail_idx = (self.tail_idx + 1) % N;