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eth-v2: Fix setting the registers for the descriptors

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Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
This commit is contained in:
Thales Fragoso
2021-06-11 11:51:51 -03:00
committed by Dario Nieuwenhuis
parent 0b42e12604
commit 6daa55a897
2 changed files with 17 additions and 12 deletions
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13
embassy-stm32/src/eth/v2/descriptors.rs
View File

@@ -102,10 +102,10 @@ impl<const N: usize> TDesRing<N> {
let dma = ETH.ethernet_dma(); let dma = ETH.ethernet_dma();
dma.dmactx_dlar() dma.dmactx_dlar()
.write(|w| w.set_tdesla(&self.td as *const _ as u32)); .write(|w| w.0 = &self.td as *const _ as u32);
dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1)); dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
dma.dmactx_dtpr() dma.dmactx_dtpr()
.write(|w| w.set_tdt(&self.td[0] as *const _ as u32)); .write(|w| w.0 = &self.td[0] as *const _ as u32);
} }
} }
@@ -148,7 +148,7 @@ impl<const N: usize> TDesRing<N> {
unsafe { unsafe {
ETH.ethernet_dma() ETH.ethernet_dma()
.dmactx_dtpr() .dmactx_dtpr()
.write(|w| w.set_tdt(&self.td[x] as *const _ as u32)); .write(|w| w.0 = &self.td[x] as *const _ as u32);
} }
self.tdidx = x; self.tdidx = x;
Ok(()) Ok(())
@@ -279,8 +279,7 @@ impl<const N: usize> RDesRing<N> {
unsafe { unsafe {
let dma = ETH.ethernet_dma(); let dma = ETH.ethernet_dma();
dma.dmacrx_dlar() dma.dmacrx_dlar().write(|w| w.0 = self.rd.as_ptr() as u32);
.write(|w| w.set_rdesla(self.rd.as_ptr() as u32));
dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1)); dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
// We manage to allocate all buffers, set the index to the last one, that means // We manage to allocate all buffers, set the index to the last one, that means
@@ -290,7 +289,7 @@ impl<const N: usize> RDesRing<N> {
let tail_ptr = &self.rd[last_index] as *const _ as u32; let tail_ptr = &self.rd[last_index] as *const _ as u32;
fence(Ordering::Release); fence(Ordering::Release);
dma.dmacrx_dtpr().write(|w| w.set_rdt(tail_ptr)); dma.dmacrx_dtpr().write(|w| w.0 = tail_ptr);
} }
} }
@@ -340,7 +339,7 @@ impl<const N: usize> RDesRing<N> {
unsafe { unsafe {
ETH.ethernet_dma() ETH.ethernet_dma()
.dmacrx_dtpr() .dmacrx_dtpr()
.write(|w| w.set_rdt(&self.rd[self.tail_idx] as *const _ as u32)); .write(|w| w.0 = &self.rd[self.tail_idx] as *const _ as u32);
} }
self.tail_idx = (self.tail_idx + 1) % N; self.tail_idx = (self.tail_idx + 1) % N;

16
embassy-stm32/src/eth/v2/mod.rs
View File

@@ -116,9 +116,13 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
mtl.mtltx_qomr().modify(|w| w.set_tsf(true)); mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
// TODO: Address aligned beats plus fixed burst ? // TODO: Address aligned beats plus fixed burst ?
dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ? dma.dmasbmr().modify(|w| {
w.set_aal(true);
w.set_fb(true);
});
dma.dmactx_cr().modify(|w| w.set_txpbl(32)); // 32 ?
dma.dmacrx_cr().modify(|w| { dma.dmacrx_cr().modify(|w| {
w.set_rxpbl(1); // 32 ? w.set_rxpbl(32); // 32 ?
w.set_rbsz(MTU as u16); w.set_rbsz(MTU as u16);
}); });
} }
@@ -162,7 +166,8 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
pub fn init(self: Pin<&mut Self>) { pub fn init(self: Pin<&mut Self>) {
// NOTE(unsafe) We won't move this // NOTE(unsafe) We won't move this
let this = unsafe { self.get_unchecked_mut() }; let this = unsafe { self.get_unchecked_mut() };
let mutex = unsafe { Pin::new_unchecked(&mut this.state) }; let mut mutex = unsafe { Pin::new_unchecked(&mut this.state) };
mutex.as_mut().register_interrupt();
mutex.with(|s, _| { mutex.with(|s, _| {
s.desc_ring.init(); s.desc_ring.init();
@@ -360,8 +365,9 @@ impl<'d, const TX: usize, const RX: usize> PeripheralState for Inner<'d, TX, RX>
let dma = ETH.ethernet_dma(); let dma = ETH.ethernet_dma();
dma.dmacsr().modify(|w| { dma.dmacsr().modify(|w| {
w.set_ti(false); w.set_ti(true);
w.set_ri(false); w.set_ri(true);
w.set_nis(true);
}); });
// Delay two peripheral's clock // Delay two peripheral's clock
dma.dmacsr().read(); dma.dmacsr().read();