From 729338875ccb1acd9f991dd2fec47ed33a66e415 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Thu, 31 Aug 2023 10:53:51 +0200 Subject: [PATCH 1/7] support QSPI BK2 --- embassy-stm32/build.rs | 16 ++++++--- embassy-stm32/src/qspi/mod.rs | 67 +++++++++++++++++++++++++++++------ 2 files changed, 67 insertions(+), 16 deletions(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 76db0a76..6fa10c7e 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -719,18 +719,24 @@ fn main() { (("sdmmc", "D6"), quote!(crate::sdmmc::D6Pin)), (("sdmmc", "D6"), quote!(crate::sdmmc::D7Pin)), (("sdmmc", "D8"), quote!(crate::sdmmc::D8Pin)), - (("quadspi", "BK1_IO0"), quote!(crate::qspi::D0Pin)), - (("quadspi", "BK1_IO1"), quote!(crate::qspi::D1Pin)), - (("quadspi", "BK1_IO2"), quote!(crate::qspi::D2Pin)), - (("quadspi", "BK1_IO3"), quote!(crate::qspi::D3Pin)), + (("quadspi", "BK1_IO0"), quote!(crate::qspi::BK1D0Pin)), + (("quadspi", "BK1_IO1"), quote!(crate::qspi::BK1D1Pin)), + (("quadspi", "BK1_IO2"), quote!(crate::qspi::BK1D2Pin)), + (("quadspi", "BK1_IO3"), quote!(crate::qspi::BK1D3Pin)), + (("quadspi", "BK1_NCS"), quote!(crate::qspi::BK1NSSPin)), + (("quadspi", "BK2_IO0"), quote!(crate::qspi::BK2D0Pin)), + (("quadspi", "BK2_IO1"), quote!(crate::qspi::BK2D1Pin)), + (("quadspi", "BK2_IO2"), quote!(crate::qspi::BK2D2Pin)), + (("quadspi", "BK2_IO3"), quote!(crate::qspi::BK2D3Pin)), + (("quadspi", "BK2_NCS"), quote!(crate::qspi::BK2NSSPin)), (("quadspi", "CLK"), quote!(crate::qspi::SckPin)), - (("quadspi", "BK1_NCS"), quote!(crate::qspi::NSSPin)), ].into(); for p in METADATA.peripherals { if let Some(regs) = &p.registers { for pin in p.pins { let key = (regs.kind, pin.signal); + eprintln!("key: {:#?}", &key); if let Some(tr) = signals.get(&key) { let mut peri = format_ident!("{}", p.name); diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 32382fb2..9ca40f8f 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -83,14 +83,53 @@ pub struct Qspi<'d, T: Instance, Dma> { } impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { - pub fn new( + pub fn new_bk1( peri: impl Peripheral

+ 'd, - d0: impl Peripheral

> + 'd, - d1: impl Peripheral

> + 'd, - d2: impl Peripheral

> + 'd, - d3: impl Peripheral

> + 'd, + d0: impl Peripheral

> + 'd, + d1: impl Peripheral

> + 'd, + d2: impl Peripheral

> + 'd, + d3: impl Peripheral

> + 'd, sck: impl Peripheral

> + 'd, - nss: impl Peripheral

> + 'd, + nss: impl Peripheral

> + 'd, + dma: impl Peripheral

+ 'd, + config: Config, + ) -> Self { + into_ref!(peri, d0, d1, d2, d3, sck, nss); + + sck.set_as_af(sck.af_num(), AFType::OutputPushPull); + sck.set_speed(crate::gpio::Speed::VeryHigh); + nss.set_as_af(nss.af_num(), AFType::OutputPushPull); + nss.set_speed(crate::gpio::Speed::VeryHigh); + d0.set_as_af(d0.af_num(), AFType::OutputPushPull); + d0.set_speed(crate::gpio::Speed::VeryHigh); + d1.set_as_af(d1.af_num(), AFType::OutputPushPull); + d1.set_speed(crate::gpio::Speed::VeryHigh); + d2.set_as_af(d2.af_num(), AFType::OutputPushPull); + d2.set_speed(crate::gpio::Speed::VeryHigh); + d3.set_as_af(d3.af_num(), AFType::OutputPushPull); + d3.set_speed(crate::gpio::Speed::VeryHigh); + + Self::new_inner( + peri, + Some(d0.map_into()), + Some(d1.map_into()), + Some(d2.map_into()), + Some(d3.map_into()), + Some(sck.map_into()), + Some(nss.map_into()), + dma, + config, + ) + } + + pub fn new_bk2( + peri: impl Peripheral

+ 'd, + d0: impl Peripheral

> + 'd, + d1: impl Peripheral

> + 'd, + d2: impl Peripheral

> + 'd, + d3: impl Peripheral

> + 'd, + sck: impl Peripheral

> + 'd, + nss: impl Peripheral

> + 'd, dma: impl Peripheral

+ 'd, config: Config, ) -> Self { @@ -313,11 +352,17 @@ pub(crate) mod sealed { pub trait Instance: Peripheral

+ sealed::Instance + RccPeripheral {} pin_trait!(SckPin, Instance); -pin_trait!(D0Pin, Instance); -pin_trait!(D1Pin, Instance); -pin_trait!(D2Pin, Instance); -pin_trait!(D3Pin, Instance); -pin_trait!(NSSPin, Instance); +pin_trait!(BK1D0Pin, Instance); +pin_trait!(BK1D1Pin, Instance); +pin_trait!(BK1D2Pin, Instance); +pin_trait!(BK1D3Pin, Instance); +pin_trait!(BK1NSSPin, Instance); + +pin_trait!(BK2D0Pin, Instance); +pin_trait!(BK2D1Pin, Instance); +pin_trait!(BK2D2Pin, Instance); +pin_trait!(BK2D3Pin, Instance); +pin_trait!(BK2NSSPin, Instance); dma_trait!(QuadDma, Instance); From 81da9ca6215ff156f1055762f47efce6fc03d004 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Tue, 5 Sep 2023 19:06:50 +0200 Subject: [PATCH 2/7] Bump stm32-metapac, add flash selection --- embassy-stm32/src/qspi/enums.rs | 16 ++++++++++++ embassy-stm32/src/qspi/mod.rs | 44 ++++++++++++++++++++++++++------- 2 files changed, 51 insertions(+), 9 deletions(-) diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs index 2dbe2b06..0412d991 100644 --- a/embassy-stm32/src/qspi/enums.rs +++ b/embassy-stm32/src/qspi/enums.rs @@ -38,6 +38,22 @@ impl Into for QspiWidth { } } +#[allow(dead_code)] +#[derive(Copy, Clone)] +pub enum FlashSelection { + Flash1, + Flash2, +} + +impl Into for FlashSelection { + fn into(self) -> bool { + match self { + FlashSelection::Flash1 => false, + FlashSelection::Flash2 => true, + } + } +} + #[derive(Copy, Clone)] pub enum MemorySize { _1KiB, diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 9ca40f8f..64131506 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -4,6 +4,7 @@ pub mod enums; use embassy_hal_internal::{into_ref, PeripheralRef}; use enums::*; +use stm32_metapac::quadspi::regs::Cr; use crate::dma::Transfer; use crate::gpio::sealed::AFType; @@ -119,6 +120,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { Some(nss.map_into()), dma, config, + FlashSelection::Flash2, ) } @@ -139,13 +141,13 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { sck.set_speed(crate::gpio::Speed::VeryHigh); nss.set_as_af(nss.af_num(), AFType::OutputPushPull); nss.set_speed(crate::gpio::Speed::VeryHigh); - d0.set_as_af(d0.af_num(), AFType::OutputPushPull); + d0.set_as_af(d0.af_num(), AFType::OutputOpenDrain); d0.set_speed(crate::gpio::Speed::VeryHigh); - d1.set_as_af(d1.af_num(), AFType::OutputPushPull); + d1.set_as_af(d1.af_num(), AFType::OutputOpenDrain); d1.set_speed(crate::gpio::Speed::VeryHigh); - d2.set_as_af(d2.af_num(), AFType::OutputPushPull); + d2.set_as_af(d2.af_num(), AFType::OutputOpenDrain); d2.set_speed(crate::gpio::Speed::VeryHigh); - d3.set_as_af(d3.af_num(), AFType::OutputPushPull); + d3.set_as_af(d3.af_num(), AFType::OutputOpenDrain); d3.set_speed(crate::gpio::Speed::VeryHigh); Self::new_inner( @@ -158,6 +160,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { Some(nss.map_into()), dma, config, + FlashSelection::Flash2, ) } @@ -171,24 +174,42 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { nss: Option>, dma: impl Peripheral

+ 'd, config: Config, + fsel: FlashSelection, ) -> Self { into_ref!(peri, dma); T::enable(); - T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into())); + T::reset(); while T::REGS.sr().read().busy() {} - T::REGS.cr().write(|w| { - w.set_prescaler(config.prescaler); + // Apply precautionary steps according to the errata... + T::REGS.cr().write_value(Cr(0)); + while T::REGS.sr().read().busy() {} + T::REGS.cr().write_value(Cr(0xFF000001)); + T::REGS.ccr().write(|w| w.set_frcm(true)); + T::REGS.ccr().write(|w| w.set_frcm(true)); + T::REGS.cr().write_value(Cr(0)); + while T::REGS.sr().read().busy() {} + + T::REGS.cr().modify(|w| { w.set_en(true); + //w.set_tcen(false); + w.set_sshift(false); + w.set_fthres(config.fifo_threshold.into()); + w.set_prescaler(config.prescaler); + w.set_fsel(fsel.into()); }); - T::REGS.dcr().write(|w| { + T::REGS.dcr().modify(|w| { w.set_fsize(config.memory_size.into()); w.set_csht(config.cs_high_time.into()); - w.set_ckmode(false); + w.set_ckmode(true); }); + // FOR TESTING ONLY + //T::REGS.ccr().write(|w| w.set_frcm(true)); + // END FOR TESTING ONLY + Self { _peri: peri, sck, @@ -203,6 +224,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { } pub fn command(&mut self, transaction: TransferConfig) { + #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(false)); self.setup_transaction(QspiMode::IndirectWrite, &transaction); @@ -211,6 +233,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { } pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) { + #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(false)); self.setup_transaction(QspiMode::IndirectWrite, &transaction); @@ -234,6 +257,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { } pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) { + #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(false)); self.setup_transaction(QspiMode::IndirectWrite, &transaction); @@ -277,6 +301,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) }; + #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(true)); transfer.blocking_wait(); @@ -303,6 +328,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) }; + #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(true)); transfer.blocking_wait(); From 8c13126cff826a20268f695a7b4d0c2588c69252 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Thu, 7 Sep 2023 20:22:33 +0200 Subject: [PATCH 3/7] make push/pull settings for pins explicit --- embassy-stm32/src/qspi/mod.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 64131506..92219e01 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -8,7 +8,7 @@ use stm32_metapac::quadspi::regs::Cr; use crate::dma::Transfer; use crate::gpio::sealed::AFType; -use crate::gpio::AnyPin; +use crate::gpio::{AnyPin, Pull}; use crate::pac::quadspi::Quadspi as Regs; use crate::rcc::RccPeripheral; use crate::{peripherals, Peripheral}; @@ -97,17 +97,17 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) -> Self { into_ref!(peri, d0, d1, d2, d3, sck, nss); - sck.set_as_af(sck.af_num(), AFType::OutputPushPull); + sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None); sck.set_speed(crate::gpio::Speed::VeryHigh); - nss.set_as_af(nss.af_num(), AFType::OutputPushPull); + nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up); nss.set_speed(crate::gpio::Speed::VeryHigh); - d0.set_as_af(d0.af_num(), AFType::OutputPushPull); + d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None); d0.set_speed(crate::gpio::Speed::VeryHigh); - d1.set_as_af(d1.af_num(), AFType::OutputPushPull); + d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None); d1.set_speed(crate::gpio::Speed::VeryHigh); - d2.set_as_af(d2.af_num(), AFType::OutputPushPull); + d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None); d2.set_speed(crate::gpio::Speed::VeryHigh); - d3.set_as_af(d3.af_num(), AFType::OutputPushPull); + d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None); d3.set_speed(crate::gpio::Speed::VeryHigh); Self::new_inner( @@ -137,17 +137,17 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) -> Self { into_ref!(peri, d0, d1, d2, d3, sck, nss); - sck.set_as_af(sck.af_num(), AFType::OutputPushPull); + sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None); sck.set_speed(crate::gpio::Speed::VeryHigh); - nss.set_as_af(nss.af_num(), AFType::OutputPushPull); + nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up); nss.set_speed(crate::gpio::Speed::VeryHigh); - d0.set_as_af(d0.af_num(), AFType::OutputOpenDrain); + d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None); d0.set_speed(crate::gpio::Speed::VeryHigh); - d1.set_as_af(d1.af_num(), AFType::OutputOpenDrain); + d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None); d1.set_speed(crate::gpio::Speed::VeryHigh); - d2.set_as_af(d2.af_num(), AFType::OutputOpenDrain); + d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None); d2.set_speed(crate::gpio::Speed::VeryHigh); - d3.set_as_af(d3.af_num(), AFType::OutputOpenDrain); + d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None); d3.set_speed(crate::gpio::Speed::VeryHigh); Self::new_inner( From 6ea5aa347db40a0f50b82ff9bc39f2f2c73fb04e Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Sun, 10 Sep 2023 11:05:10 +0200 Subject: [PATCH 4/7] feature-gate errata workaround for h7 --- embassy-stm32/src/qspi/mod.rs | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 92219e01..900dfa83 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -183,14 +183,17 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { while T::REGS.sr().read().busy() {} - // Apply precautionary steps according to the errata... - T::REGS.cr().write_value(Cr(0)); - while T::REGS.sr().read().busy() {} - T::REGS.cr().write_value(Cr(0xFF000001)); - T::REGS.ccr().write(|w| w.set_frcm(true)); - T::REGS.ccr().write(|w| w.set_frcm(true)); - T::REGS.cr().write_value(Cr(0)); - while T::REGS.sr().read().busy() {} + #[cfg(stm32h7)] + { + // Apply precautionary steps according to the errata... + T::REGS.cr().write_value(Cr(0)); + while T::REGS.sr().read().busy() {} + T::REGS.cr().write_value(Cr(0xFF000001)); + T::REGS.ccr().write(|w| w.set_frcm(true)); + T::REGS.ccr().write(|w| w.set_frcm(true)); + T::REGS.cr().write_value(Cr(0)); + while T::REGS.sr().read().busy() {} + } T::REGS.cr().modify(|w| { w.set_en(true); From f3aa0cfe5a7ff98e2fc8a004ea8a2268112d54f3 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 2 Oct 2023 09:33:10 +0200 Subject: [PATCH 5/7] remove debug code, add some comments --- embassy-stm32/src/qspi/mod.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 900dfa83..7d2ae579 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -209,10 +209,6 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { w.set_ckmode(true); }); - // FOR TESTING ONLY - //T::REGS.ccr().write(|w| w.set_frcm(true)); - // END FOR TESTING ONLY - Self { _peri: peri, sck, @@ -260,8 +256,10 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { } pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) { + // STM32H7 does not have dmaen #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(false)); + self.setup_transaction(QspiMode::IndirectWrite, &transaction); if let Some(len) = transaction.data_len { @@ -304,6 +302,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) }; + // STM32H7 does not have dmaen #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(true)); @@ -331,6 +330,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) }; + // STM32H7 does not have dmaen #[cfg(not(stm32h7))] T::REGS.cr().modify(|v| v.set_dmaen(true)); From bd267a647963d38d9865f7876b0e7617cf2b899e Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 2 Oct 2023 09:34:59 +0200 Subject: [PATCH 6/7] move stm32h7 specific import --- embassy-stm32/src/qspi/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 7d2ae579..8fb7df64 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -4,7 +4,6 @@ pub mod enums; use embassy_hal_internal::{into_ref, PeripheralRef}; use enums::*; -use stm32_metapac::quadspi::regs::Cr; use crate::dma::Transfer; use crate::gpio::sealed::AFType; @@ -185,6 +184,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { #[cfg(stm32h7)] { + use stm32_metapac::quadspi::regs::Cr; // Apply precautionary steps according to the errata... T::REGS.cr().write_value(Cr(0)); while T::REGS.sr().read().busy() {} From 923f1851ee02f697989fd25b6e93d22f30cb6b28 Mon Sep 17 00:00:00 2001 From: JuliDi <20155974+JuliDi@users.noreply.github.com> Date: Mon, 2 Oct 2023 09:36:11 +0200 Subject: [PATCH 7/7] remove debug logging in build.rs --- embassy-stm32/build.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 6fa10c7e..ed5fa84d 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -736,7 +736,6 @@ fn main() { if let Some(regs) = &p.registers { for pin in p.pins { let key = (regs.kind, pin.signal); - eprintln!("key: {:#?}", &key); if let Some(tr) = signals.get(&key) { let mut peri = format_ident!("{}", p.name);