stm32/rtc: remove generics and segregate clock sel
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b555af1c5d
commit
6fc5c608f8
@ -1,6 +1,6 @@
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pub use super::common::{AHBPrescaler, APBPrescaler};
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use crate::rcc::Clocks;
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use crate::rtc::{enable as enable_rtc, RtcClockSource};
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use crate::rtc::{Rtc, RtcClockSource};
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use crate::time::{khz, mhz, Hertz};
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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@ -375,5 +375,5 @@ pub(crate) fn configure_clocks(config: &Config) {
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w.set_shdhpre(config.ahb3_pre.into());
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});
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config.rtc.map(|clock_source| enable_rtc(clock_source));
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config.rtc.map(|clock_source| Rtc::set_clock_source(clock_source));
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}
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@ -1,5 +1,4 @@
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//! RTC peripheral abstraction
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use core::marker::PhantomData;
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mod datetime;
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pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
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@ -17,6 +16,9 @@ mod _version;
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pub use _version::*;
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use embassy_hal_internal::Peripheral;
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use crate::peripherals::RTC;
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use crate::rtc::sealed::Instance;
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/// Errors that can occur on methods on [RtcClock]
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#[derive(Clone, Debug, PartialEq, Eq)]
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pub enum RtcError {
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@ -28,22 +30,10 @@ pub enum RtcError {
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}
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/// RTC Abstraction
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pub struct Rtc<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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pub struct Rtc {
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rtc_config: RtcConfig,
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}
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#[allow(dead_code)]
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pub(crate) fn enable(clock_source: RtcClockSource) {
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Rtc::<crate::peripherals::RTC>::enable(clock_source);
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}
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#[cfg(feature = "time")]
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#[allow(dead_code)]
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pub(crate) fn set_wakeup_timer(_duration: embassy_time::Duration) {
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todo!()
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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pub enum RtcClockSource {
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@ -59,8 +49,6 @@ pub enum RtcClockSource {
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#[derive(Copy, Clone, PartialEq)]
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pub struct RtcConfig {
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/// RTC clock source
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clock_source: RtcClockSource,
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/// Asynchronous prescaler factor
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/// This is the asynchronous division factor:
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/// ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
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@ -78,7 +66,6 @@ impl Default for RtcConfig {
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/// Raw sub-seconds in 1/256.
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fn default() -> Self {
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RtcConfig {
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clock_source: RtcClockSource::LSI,
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async_prescaler: 127,
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sync_prescaler: 255,
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}
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@ -86,12 +73,6 @@ impl Default for RtcConfig {
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}
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impl RtcConfig {
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/// Sets the clock source of RTC config
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pub fn clock_source(mut self, clock_source: RtcClockSource) -> Self {
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self.clock_source = clock_source;
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self
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}
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/// Set the asynchronous prescaler of RTC config
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pub fn async_prescaler(mut self, prescaler: u8) -> Self {
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self.async_prescaler = prescaler;
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@ -122,16 +103,13 @@ impl Default for RtcCalibrationCyclePeriod {
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}
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}
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impl<'d, T: Instance> Rtc<'d, T> {
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pub fn new(_rtc: impl Peripheral<P = T> + 'd, rtc_config: RtcConfig) -> Self {
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T::enable_peripheral_clk();
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impl Rtc {
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pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
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RTC::enable_peripheral_clk();
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let mut rtc_struct = Self {
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phantom: PhantomData,
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rtc_config,
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};
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let mut rtc_struct = Self { rtc_config };
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Self::enable(rtc_config.clock_source);
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Self::enable();
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rtc_struct.configure(rtc_config);
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rtc_struct.rtc_config = rtc_config;
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@ -157,7 +135,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
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///
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/// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
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pub fn now(&self) -> Result<DateTime, RtcError> {
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let r = T::regs();
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let r = RTC::regs();
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let tr = r.tr().read();
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let second = bcd2_to_byte((tr.st(), tr.su()));
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let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
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@ -176,7 +154,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
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/// Check if daylight savings time is active.
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pub fn get_daylight_savings(&self) -> bool {
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let cr = T::regs().cr().read();
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let cr = RTC::regs().cr().read();
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cr.bkp()
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}
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@ -191,14 +169,14 @@ impl<'d, T: Instance> Rtc<'d, T> {
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self.rtc_config
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}
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pub const BACKUP_REGISTER_COUNT: usize = T::BACKUP_REGISTER_COUNT;
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pub const BACKUP_REGISTER_COUNT: usize = RTC::BACKUP_REGISTER_COUNT;
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/// Read content of the backup register.
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///
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/// The registers retain their values during wakes from standby mode or system resets. They also
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/// retain their value when Vdd is switched off as long as V_BAT is powered.
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pub fn read_backup_register(&self, register: usize) -> Option<u32> {
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T::read_backup_register(&T::regs(), register)
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RTC::read_backup_register(&RTC::regs(), register)
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}
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/// Set content of the backup register.
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@ -206,7 +184,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
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/// The registers retain their values during wakes from standby mode or system resets. They also
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/// retain their value when Vdd is switched off as long as V_BAT is powered.
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pub fn write_backup_register(&self, register: usize, value: u32) {
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T::write_backup_register(&T::regs(), register, value)
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RTC::write_backup_register(&RTC::regs(), register, value)
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}
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}
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@ -257,5 +235,3 @@ pub(crate) mod sealed {
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// fn apply_config(&mut self, rtc_config: RtcConfig);
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}
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}
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pub trait Instance: sealed::Instance + 'static {}
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@ -1,13 +1,12 @@
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use stm32_metapac::rtc::vals::{Init, Osel, Pol};
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use super::{sealed, Instance, RtcClockSource, RtcConfig};
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use super::{sealed, RtcClockSource, RtcConfig};
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use crate::pac::rtc::Rtc;
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use crate::peripherals::RTC;
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use crate::rtc::sealed::Instance;
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impl<'d, T: Instance> super::Rtc<'d, T> {
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pub(super) fn enable(clock_source: RtcClockSource) {
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#[cfg(not(rtc_v2wb))]
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use stm32_metapac::rcc::vals::Rtcsel;
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impl super::Rtc {
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fn unlock_registers() {
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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let cr = crate::pac::PWR.cr();
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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@ -16,10 +15,35 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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// TODO: Missing from PAC for l0 and f0?
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#[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
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{
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if !cr.read().dbp() {
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cr.modify(|w| w.set_dbp(true));
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while !cr.read().dbp() {}
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}
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}
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}
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#[allow(dead_code)]
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pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
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#[cfg(not(rtc_v2wb))]
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use stm32_metapac::rcc::vals::Rtcsel;
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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Self::unlock_registers();
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cr.modify(|w| {
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// Select RTC source
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#[cfg(not(rtc_v2wb))]
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w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
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#[cfg(rtc_v2wb)]
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w.set_rtcsel(clock_source as u8);
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});
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}
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pub(super) fn enable() {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let reg = crate::pac::RCC.bdcr().read();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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@ -28,12 +52,9 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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#[cfg(rtc_v2wb)]
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let rtcsel = reg.rtcsel();
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#[cfg(not(rtc_v2wb))]
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let rtcsel = reg.rtcsel().to_bits();
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if !reg.rtcen() {
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Self::unlock_registers();
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if !reg.rtcen() || rtcsel != clock_source as u8 {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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@ -46,12 +67,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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w.set_bdrst(false);
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// Select RTC source
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#[cfg(not(rtc_v2wb))]
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w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
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#[cfg(rtc_v2wb)]
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w.set_rtcsel(clock_source as u8);
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w.set_rtcen(true);
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w.set_rtcsel(reg.rtcsel());
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// Restore bcdr
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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@ -157,7 +174,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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where
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F: FnOnce(&crate::pac::rtc::Rtc) -> R,
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{
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let r = T::regs();
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let r = RTC::regs();
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// Disable write protection.
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// This is safe, as we're only writin the correct and expected values.
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r.wpr().write(|w| w.set_key(0xca));
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@ -218,5 +235,3 @@ impl sealed::Instance for crate::peripherals::RTC {
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}
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}
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}
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impl Instance for crate::peripherals::RTC {}
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@ -1,42 +1,62 @@
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use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
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use super::{sealed, Instance, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
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use super::{sealed, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
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use crate::pac::rtc::Rtc;
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use crate::peripherals::RTC;
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use crate::rtc::sealed::Instance;
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impl<'d, T: Instance> super::Rtc<'d, T> {
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pub(super) fn enable(clock_source: RtcClockSource) {
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impl super::Rtc {
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fn unlock_registers() {
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// Unlock the backup domain
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#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
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{
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if !crate::pac::PWR.cr1().read().dbp() {
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
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while !crate::pac::PWR.cr1().read().dbp() {}
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}
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}
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#[cfg(any(rcc_wl5, rcc_wle))]
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{
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use crate::pac::pwr::vals::Dbp;
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if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
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while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
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}
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}
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}
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let reg = crate::pac::RCC.bdcr().read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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#[allow(dead_code)]
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pub(crate) fn set_clock_source(clock_source: RtcClockSource) {
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let clock_source = clock_source as u8;
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#[cfg(not(any(rcc_wl5, rcc_wle)))]
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let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
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if !reg.rtcen() || reg.rtcsel() != clock_source {
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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Self::unlock_registers();
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crate::pac::RCC.bdcr().modify(|w| {
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// Select RTC source
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w.set_rtcsel(clock_source);
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});
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}
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pub(super) fn enable() {
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let bdcr = crate::pac::RCC.bdcr();
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let reg = bdcr.read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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if !reg.rtcen() {
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Self::unlock_registers();
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bdcr.modify(|w| w.set_bdrst(true));
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bdcr.modify(|w| {
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// Reset
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w.set_bdrst(false);
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// Select RTC source
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w.set_rtcsel(clock_source);
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w.set_rtcen(true);
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w.set_rtcsel(reg.rtcsel());
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// Restore bcdr
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w.set_lscosel(reg.lscosel());
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@ -141,7 +161,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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where
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F: FnOnce(&crate::pac::rtc::Rtc) -> R,
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{
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let r = T::regs();
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let r = RTC::regs();
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// Disable write protection.
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// This is safe, as we're only writin the correct and expected values.
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r.wpr().write(|w| w.set_key(Key::DEACTIVATE1));
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@ -188,5 +208,3 @@ impl sealed::Instance for crate::peripherals::RTC {
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}
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}
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}
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impl Instance for crate::peripherals::RTC {}
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@ -27,10 +27,7 @@ async fn main(_spawner: Spawner) {
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.and_hms_opt(10, 30, 15)
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.unwrap();
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let mut rtc = Rtc::new(
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p.RTC,
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RtcConfig::default().clock_source(embassy_stm32::rtc::RtcClockSource::LSE),
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);
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let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
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info!("Got RTC! {:?}", now.timestamp());
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rtc.set_datetime(now.into()).expect("datetime not set");
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