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stm32/otg: fix enumeration on non-f4 chips.

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Fixes regression from #2148
This commit is contained in:
Dario Nieuwenhuis 2023-11-06 04:13:06 +01:00
parent 58719dcb58
commit 7084570478
1 changed files with 16 additions and 5 deletions
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21
embassy-stm32/src/usb_otg/usb.rs
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@ -107,10 +107,10 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
vals::Pktstsd::SETUP_DATA_DONE => { vals::Pktstsd::SETUP_DATA_DONE => {
trace!("SETUP_DATA_DONE ep={}", ep_num); trace!("SETUP_DATA_DONE ep={}", ep_num);
// Clear NAK to indicate we are ready to receive more data if quirk_setup_late_cnak(r) {
T::regs().doepctl(ep_num).modify(|w| { // Clear NAK to indicate we are ready to receive more data
w.set_cnak(true); r.doepctl(ep_num).modify(|w| w.set_cnak(true));
}); }
} }
x => trace!("unknown PKTSTS: {}", x.to_bits()), x => trace!("unknown PKTSTS: {}", x.to_bits()),
} }
@ -1317,16 +1317,23 @@ impl<'d, T: Instance> embassy_usb_driver::ControlPipe for ControlPipe<'d, T> {
state.ep_out_wakers[0].register(cx.waker()); state.ep_out_wakers[0].register(cx.waker());
let r = T::regs();
if state.ep0_setup_ready.load(Ordering::Relaxed) { if state.ep0_setup_ready.load(Ordering::Relaxed) {
let data = unsafe { *state.ep0_setup_data.get() }; let data = unsafe { *state.ep0_setup_data.get() };
state.ep0_setup_ready.store(false, Ordering::Release); state.ep0_setup_ready.store(false, Ordering::Release);
// EP0 should not be controlled by `Bus` so this RMW does not need a critical section // EP0 should not be controlled by `Bus` so this RMW does not need a critical section
// Receive 1 SETUP packet // Receive 1 SETUP packet
T::regs().doeptsiz(self.ep_out.info.addr.index()).modify(|w| { r.doeptsiz(self.ep_out.info.addr.index()).modify(|w| {
w.set_rxdpid_stupcnt(1); w.set_rxdpid_stupcnt(1);
}); });
// Clear NAK to indicate we are ready to receive more data
if !quirk_setup_late_cnak(r) {
r.doepctl(self.ep_out.info.addr.index()).modify(|w| w.set_cnak(true));
}
trace!("SETUP received: {:?}", data); trace!("SETUP received: {:?}", data);
Poll::Ready(data) Poll::Ready(data)
} else { } else {
@ -1461,3 +1468,7 @@ fn calculate_trdt(speed: vals::Dspd, ahb_freq: Hertz) -> u8 {
_ => unimplemented!(), _ => unimplemented!(),
} }
} }
fn quirk_setup_late_cnak(r: crate::pac::otg::Otg) -> bool {
r.cid().read().0 & 0xf000 == 0x1000
}