stm32/otg: fix enumeration on non-f4 chips.
Fixes regression from #2148
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58719dcb58
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@ -107,10 +107,10 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
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vals::Pktstsd::SETUP_DATA_DONE => {
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trace!("SETUP_DATA_DONE ep={}", ep_num);
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// Clear NAK to indicate we are ready to receive more data
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T::regs().doepctl(ep_num).modify(|w| {
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w.set_cnak(true);
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});
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if quirk_setup_late_cnak(r) {
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// Clear NAK to indicate we are ready to receive more data
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r.doepctl(ep_num).modify(|w| w.set_cnak(true));
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}
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}
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x => trace!("unknown PKTSTS: {}", x.to_bits()),
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}
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@ -1317,16 +1317,23 @@ impl<'d, T: Instance> embassy_usb_driver::ControlPipe for ControlPipe<'d, T> {
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state.ep_out_wakers[0].register(cx.waker());
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let r = T::regs();
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if state.ep0_setup_ready.load(Ordering::Relaxed) {
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let data = unsafe { *state.ep0_setup_data.get() };
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state.ep0_setup_ready.store(false, Ordering::Release);
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// EP0 should not be controlled by `Bus` so this RMW does not need a critical section
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// Receive 1 SETUP packet
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T::regs().doeptsiz(self.ep_out.info.addr.index()).modify(|w| {
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r.doeptsiz(self.ep_out.info.addr.index()).modify(|w| {
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w.set_rxdpid_stupcnt(1);
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});
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// Clear NAK to indicate we are ready to receive more data
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if !quirk_setup_late_cnak(r) {
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r.doepctl(self.ep_out.info.addr.index()).modify(|w| w.set_cnak(true));
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}
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trace!("SETUP received: {:?}", data);
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Poll::Ready(data)
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} else {
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@ -1461,3 +1468,7 @@ fn calculate_trdt(speed: vals::Dspd, ahb_freq: Hertz) -> u8 {
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_ => unimplemented!(),
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}
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}
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fn quirk_setup_late_cnak(r: crate::pac::otg::Otg) -> bool {
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r.cid().read().0 & 0xf000 == 0x1000
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}
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