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Reorder args

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This commit is contained in:
Henrik Alsér 2022-08-31 22:12:14 +02:00 committed by Henrik Alsér
parent e2181cb439
commit 71c130488b
1 changed files with 16 additions and 16 deletions
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32
embassy-rp/src/spi.rs
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@ -67,12 +67,12 @@ fn calc_prescs(freq: u32) -> (u8, u8) {
impl<'d, T: Instance, M: Mode> Spi<'d, T, M> { impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
fn new_inner( fn new_inner(
inner: impl Peripheral<P = T> + 'd, inner: impl Peripheral<P = T> + 'd,
tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
clk: Option<PeripheralRef<'d, AnyPin>>, clk: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>, mosi: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>, miso: Option<PeripheralRef<'d, AnyPin>>,
cs: Option<PeripheralRef<'d, AnyPin>>, cs: Option<PeripheralRef<'d, AnyPin>>,
tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(inner); into_ref!(inner);
@ -212,12 +212,12 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
into_ref!(clk, mosi, miso); into_ref!(clk, mosi, miso);
Self::new_inner( Self::new_inner(
inner, inner,
None,
None,
Some(clk.map_into()), Some(clk.map_into()),
Some(mosi.map_into()), Some(mosi.map_into()),
Some(miso.map_into()), Some(miso.map_into()),
None, None,
None,
None,
config, config,
) )
} }
@ -231,12 +231,12 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
into_ref!(clk, mosi); into_ref!(clk, mosi);
Self::new_inner( Self::new_inner(
inner, inner,
None,
None,
Some(clk.map_into()), Some(clk.map_into()),
Some(mosi.map_into()), Some(mosi.map_into()),
None, None,
None, None,
None,
None,
config, config,
) )
} }
@ -250,12 +250,12 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
into_ref!(clk, miso); into_ref!(clk, miso);
Self::new_inner( Self::new_inner(
inner, inner,
None,
None,
Some(clk.map_into()), Some(clk.map_into()),
None, None,
Some(miso.map_into()), Some(miso.map_into()),
None, None,
None,
None,
config, config,
) )
} }
@ -274,52 +274,52 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
into_ref!(tx_dma, rx_dma, clk, mosi, miso); into_ref!(tx_dma, rx_dma, clk, mosi, miso);
Self::new_inner( Self::new_inner(
inner, inner,
Some(tx_dma.map_into()),
Some(rx_dma.map_into()),
Some(clk.map_into()), Some(clk.map_into()),
Some(mosi.map_into()), Some(mosi.map_into()),
Some(miso.map_into()), Some(miso.map_into()),
None, None,
Some(tx_dma.map_into()),
Some(rx_dma.map_into()),
config, config,
) )
} }
pub fn new_txonly( pub fn new_txonly(
inner: impl Peripheral<P = T> + 'd, inner: impl Peripheral<P = T> + 'd,
tx_dma: impl Peripheral<P = impl Channel> + 'd,
clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd, clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd, mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
tx_dma: impl Peripheral<P = impl Channel> + 'd,
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(tx_dma, clk, mosi); into_ref!(tx_dma, clk, mosi);
Self::new_inner( Self::new_inner(
inner, inner,
Some(tx_dma.map_into()),
None,
Some(clk.map_into()), Some(clk.map_into()),
Some(mosi.map_into()), Some(mosi.map_into()),
None, None,
None, None,
Some(tx_dma.map_into()),
None,
config, config,
) )
} }
pub fn new_rxonly( pub fn new_rxonly(
inner: impl Peripheral<P = T> + 'd, inner: impl Peripheral<P = T> + 'd,
rx_dma: impl Peripheral<P = impl Channel> + 'd,
clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd, clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd, miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
rx_dma: impl Peripheral<P = impl Channel> + 'd,
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(rx_dma, clk, miso); into_ref!(rx_dma, clk, miso);
Self::new_inner( Self::new_inner(
inner, inner,
None,
Some(rx_dma.map_into()),
Some(clk.map_into()), Some(clk.map_into()),
None, None,
Some(miso.map_into()), Some(miso.map_into()),
None, None,
None,
Some(rx_dma.map_into()),
config, config,
) )
} }