implement prelim draft
This commit is contained in:
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04944b6379
commit
74b5d4693c
@ -40,4 +40,4 @@ cortex-m-rt = "0.6.13"
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cortex-m = { version = "0.6.4" }
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cortex-m = { version = "0.6.4" }
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embedded-hal = { version = "0.2.4" }
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embedded-hal = { version = "0.2.4" }
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embedded-dma = { version = "0.1.2" }
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embedded-dma = { version = "0.1.2" }
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stm32f4xx-hal = { version = "0.8.3", features = ["rt"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git" }
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stm32f4xx-hal = { version = "0.8.3", features = ["rt"], git = "https://github.com/xoviat/stm32f4xx-hal.git", branch = "dma-is-done"}
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@ -2,6 +2,7 @@
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#![feature(generic_associated_types)]
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#![feature(generic_associated_types)]
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#![feature(asm)]
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#![feature(asm)]
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#![feature(type_alias_impl_trait)]
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#![feature(type_alias_impl_trait)]
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#![feature(let_chains)]
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#[cfg(not(any(
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#[cfg(not(any(
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feature = "stm32f401",
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feature = "stm32f401",
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@ -16,11 +16,14 @@ use core::task::{Context, Poll};
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use cortex_m::singleton;
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use cortex_m::singleton;
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use embassy::util::Signal;
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use embassy::util::Signal;
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use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
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use embedded_dma::{StaticReadBuffer, StaticWriteBuffer, WriteBuffer};
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use crate::fmt::assert;
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use crate::fmt::assert;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::{Channel4, PeripheralToMemory, Stream2, StreamsTuple, Transfer};
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use crate::hal::dma::{
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Channel4, Channel7, MemoryToPeripheral, PeripheralToMemory, Stream2, Stream7, StreamsTuple,
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Transfer,
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};
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use crate::hal::gpio::gpioa::{PA10, PA9};
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use crate::hal::gpio::gpioa::{PA10, PA9};
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use crate::hal::gpio::{Alternate, AF10, AF7, AF9};
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use crate::hal::gpio::{Alternate, AF10, AF7, AF9};
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use crate::hal::gpio::{Floating, Input, Output, PushPull};
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use crate::hal::gpio::{Floating, Input, Output, PushPull};
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@ -94,45 +97,15 @@ impl Uarte {
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)
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)
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.unwrap();
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.unwrap();
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let isr = pins.dma.hisr;0
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// let is_set = dma.hifcr.read().tcif7.bit_is_set();
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Uarte { instance: serial, dma: pins.dma, usart: pins.usart }
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Uarte {
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instance: serial,
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dma: pins.dma,
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usart: pins.usart,
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}
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}
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}
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/// Sets the baudrate, parity and assigns the pins to the UARTE peripheral.
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// TODO: Make it take the same `Pins` structs nrf-hal (with optional RTS/CTS).
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// // TODO: #[cfg()] for smaller device variants without port register (nrf52810, ...).
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// pub fn configure(
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// &mut self,
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// rxd: &Pin<Input<Floating>>,
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// txd: &mut Pin<Output<PushPull>>,
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// parity: Parity,
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// baudrate: Baudrate,
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// ) {
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// let uarte = &self.instance;
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// assert!(uarte.enable.read().enable().is_disabled());
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//
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// uarte.psel.rxd.write(|w| {
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// let w = unsafe { w.pin().bits(rxd.pin()) };
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// let w = w.port().bit(rxd.port().bit());
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// w.connect().connected()
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// });
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//
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// txd.set_high().unwrap();
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// uarte.psel.txd.write(|w| {
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// let w = unsafe { w.pin().bits(txd.pin()) };
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// let w = w.port().bit(txd.port().bit());
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// w.connect().connected()
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// });
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//
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// uarte.baudrate.write(|w| w.baudrate().variant(baudrate));
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// uarte.config.write(|w| w.parity().variant(parity));
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// }
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// fn enable(&mut self) {
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// self.instance.enable.write(|w| w.enable().enabled());
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// }
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/// Sends serial data.
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/// Sends serial data.
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///
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///
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/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
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/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
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@ -140,25 +113,15 @@ impl Uarte {
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/// reused until the future has finished.
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/// reused until the future has finished.
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pub fn send<'a, B>(&'a mut self, tx_buffer: B) -> SendFuture<'a, B>
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pub fn send<'a, B>(&'a mut self, tx_buffer: B) -> SendFuture<'a, B>
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where
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where
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B: StaticReadBuffer<Word = u8>,
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B: WriteBuffer<Word = u8> + 'static,
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{
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{
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// Panic if TX is running which can happen if the user has called
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// `mem::forget()` on a previous future after polling it once.
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assert!(!self.tx_started());
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self.enable();
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SendFuture {
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SendFuture {
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uarte: self,
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uarte: self,
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buf: tx_buffer,
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buf: tx_buffer,
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transfer: None,
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}
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}
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}
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}
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fn tx_started(&self) -> bool {
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// self.instance.events_txstarted.read().bits() != 0
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false
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}
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/// Receives serial data.
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/// Receives serial data.
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///
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///
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/// The future is pending until the buffer is completely filled.
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/// The future is pending until the buffer is completely filled.
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@ -171,83 +134,45 @@ impl Uarte {
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/// reused until the future has finished.
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/// reused until the future has finished.
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pub fn receive<'a, B>(&'a mut self, rx_buffer: B) -> ReceiveFuture<'a, B>
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pub fn receive<'a, B>(&'a mut self, rx_buffer: B) -> ReceiveFuture<'a, B>
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where
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where
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B: StaticWriteBuffer<Word = u8>,
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B: WriteBuffer<Word = u8> + 'static,
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{
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{
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// Panic if RX is running which can happen if the user has called
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// `mem::forget()` on a previous future after polling it once.
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assert!(!self.rx_started());
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self.enable();
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ReceiveFuture {
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ReceiveFuture {
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uarte: self,
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uarte: self,
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buf: Some(rx_buffer),
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buf: rx_buffer,
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transfer: None,
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}
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}
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}
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}
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fn rx_started(&self) -> bool {
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self.instance.events_rxstarted.read().bits() != 0
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}
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}
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}
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/// Future for the [`LowPowerUarte::send()`] method.
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/// Future for the [`LowPowerUarte::send()`] method.
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pub struct SendFuture<'a, B> {
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pub struct SendFuture<'a, B: WriteBuffer<Word = u8> + 'static> {
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uarte: &'a Uarte,
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uarte: &'a Uarte,
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transfer: Option<&'a Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, B>>,
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buf: B,
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buf: B,
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}
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}
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impl<'a, B> Drop for SendFuture<'a, B> {
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impl<'a, B> Drop for SendFuture<'a, B>
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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fn drop(self: &mut Self) {
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fn drop(self: &mut Self) {
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if self.uarte.tx_started() {
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drop(self.transfer);
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trace!("stoptx");
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// Stop the transmitter to minimize the current consumption.
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self.uarte
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.instance
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.tasks_stoptx
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.write(|w| unsafe { w.bits(1) });
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self.uarte.instance.events_txstarted.reset();
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}
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}
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}
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}
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}
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impl<'a, B> Future for SendFuture<'a, B>
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impl<'a, B> Future for SendFuture<'a, B>
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where
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where
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B: StaticReadBuffer<Word = u8>,
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B: WriteBuffer<Word = u8> + 'static,
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{
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{
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type Output = ();
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type Output = ();
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
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if self.is_ready() {
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if !self.transfer.is_none() && self.transfer.unwrap().is_done() {
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Poll::Ready(())
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Poll::Ready(())
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} else {
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} else {
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// Start DMA transaction
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self.transfer = Some(&mut Transfer::init(
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let uarte = &self.uarte.instance;
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StreamsTuple::new(self.uarte.dma).7,
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self.uarte.usart,
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STATE.tx_done.reset();
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let (ptr, len) = unsafe { self.buf.read_buffer() };
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// assert!(len <= EASY_DMA_SIZE);
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// TODO: panic if buffer is not in SRAM
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compiler_fence(Ordering::SeqCst);
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// uarte.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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// uarte
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// .txd
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// .maxcnt
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// .write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Start the DMA transfer
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// See https://github.com/mwkroening/async-stm32f1xx/blob/78c46d1bff124eae4ebc7a2f4d40e6ed74def8b5/src/serial.rs#L118-L129
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// https://github.com/stm32-rs/stm32f1xx-hal/blob/68fd3d6f282173816fd3181e795988d314cb17d0/src/serial.rs#L649-L671
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// let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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// let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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// let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
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let transfer = Transfer::init(
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StreamsTuple::new(self.dma).2,
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self.usart,
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self.buf,
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self.buf,
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// Some(second_buffer),
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// Some(second_buffer),
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None,
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None,
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@ -255,71 +180,7 @@ where
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.transfer_complete_interrupt(true)
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.memory_increment(true)
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.double_buffer(false),
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.double_buffer(false),
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);
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));
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waker_interrupt!(DMA2_STREAM2, cx.waker().clone());
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Poll::Pending
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}
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}
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}
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/// Future for the [`Uarte::receive()`] method.
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pub struct ReceiveFuture<'a, B> {
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uarte: &'a Uarte,
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buf: Option<B>,
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}
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impl<'a, B> Drop for ReceiveFuture<'a, B> {
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fn drop(self: &mut Self) {
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if self.uarte.rx_started() {
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trace!("stoprx");
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self.uarte
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.instance
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.tasks_stoprx
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.write(|w| unsafe { w.bits(1) });
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self.uarte.instance.events_rxstarted.reset();
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}
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}
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}
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impl<'a, B> Future for ReceiveFuture<'a, B>
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where
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B: StaticWriteBuffer<Word = u8>,
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{
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type Output = B;
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> {
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if self.is_ready() {
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Poll::Ready(())
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} else {
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// Start DMA transaction
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compiler_fence(Ordering::SeqCst);
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// uarte.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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// uarte
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// .txd
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// .maxcnt
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// .write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Start the DMA transfer
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// See https://github.com/mwkroening/async-stm32f1xx/blob/78c46d1bff124eae4ebc7a2f4d40e6ed74def8b5/src/serial.rs#L118-L129
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// https://github.com/stm32-rs/stm32f1xx-hal/blob/68fd3d6f282173816fd3181e795988d314cb17d0/src/serial.rs#L649-L671
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// let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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// let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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// let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
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let transfer = Transfer::init(
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StreamsTuple::new(self.dma).7,
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self.usart,
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self.buf,
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// Some(second_buffer),
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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);
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waker_interrupt!(DMA2_STREAM7, cx.waker().clone());
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waker_interrupt!(DMA2_STREAM7, cx.waker().clone());
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Poll::Pending
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Poll::Pending
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@ -327,13 +188,46 @@ where
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}
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}
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}
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}
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/// Future for the [`receive()`] method.
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/// Future for the [`Uarte::receive()`] method.
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impl<'a, B> ReceiveFuture<'a, B> {
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pub struct ReceiveFuture<'a, B: WriteBuffer<Word = u8> + 'static> {
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/// Stops the ongoing reception and returns the number of bytes received.
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uarte: &'a Uarte,
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pub async fn stop(mut self) -> (B, usize) {
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transfer: Option<&'a Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, B>>,
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let buf = self.buf.take().unwrap();
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buf: B,
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drop(self);
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}
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let len = STATE.rx_done.wait().await;
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(buf, len as _)
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impl<'a, B> Drop for ReceiveFuture<'a, B>
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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fn drop(self: &mut Self) {
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drop(self.transfer);
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}
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}
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impl<'a, B> Future for ReceiveFuture<'a, B>
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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type Output = B;
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> {
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if !self.transfer.is_none() && self.transfer.unwrap().is_done() {
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Poll::Ready(self.buf.take());
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} else {
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self.transfer = Some(&mut Transfer::init(
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StreamsTuple::new(self.uarte.dma).2,
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self.uarte.usart,
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self.buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.half_transfer_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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));
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waker_interrupt!(DMA2_STREAM2, cx.waker().clone());
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Poll::Pending
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}
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}
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}
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}
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}
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